[entropy_src] Add boot phase done state
- The main state machine will now hang in a boot phase done state instead
of moving on to the startup state.
- This now requires software intervention after the boot phase runs.
- Also cleans up DV config fields and initialization routines to better reflect
current register names
Fixes #9853.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index a805cac..d9e0cbc 100644
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson
@@ -241,19 +241,11 @@
resval: "false"
},
{ bits: "15:12",
- name: "BOOT_BYPASS_DISABLE",
+ name: "THRESHOLD_SCOPE",
mubi: true,
desc: '''
- Setting this field to kMuBi4True will disable the initial generation of non-FIPS entropy.
- '''
- resval: false
- },
- { bits: "19:16",
- name: "HEALTH_TEST_CLR",
- mubi: true,
- desc: '''
- Setting this field to kMuBi4True will clear all registers related to the
- health test operations.
+ Setting this field to kMuBi4True will enable threshold scope mode.
+ TODO(#9759): add more description.
'''
resval: false
},
@@ -1205,7 +1197,11 @@
name: "MAIN_SM_IDLE",
desc: "The entropy_src main state machine is in the idle state."
}
- { bits: "31:24",
+ { bits: "17",
+ name: "MAIN_SM_BOOT_DONE",
+ desc: "The entropy_src main state machine is in the boot phase done state."
+ }
+ { bits: "28:20",
name: "MAIN_SM_STATE",
desc: "This is the state of the entropy_src main state machine."
}
@@ -1242,17 +1238,9 @@
'''
}
{ bits: "3",
- name: "BOOT_BYPASS_DISABLE_FIELD_ALERT",
+ name: "THRESHOLD_SCOPE_FIELD_ALERT",
desc: '''
- This bit is set when the BOOT_BYPASS_DISABLE field in the !!CONF register is set to
- a value other than 0x5 or 0xA.
- Writing a zero resets this status bit.
- '''
- }
- { bits: "4",
- name: "HEALTH_TEST_CLR_FIELD_ALERT",
- desc: '''
- This bit is set when the HEALTH_TEST_CLR field in the !!CONF register is set to
+ This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to
a value other than 0x5 or 0xA.
Writing a zero resets this status bit.
'''
diff --git a/hw/ip/entropy_src/doc/es_main_sm.svg b/hw/ip/entropy_src/doc/es_main_sm.svg
index e08f32b..4cd9a05 100644
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+ <text x="14.85" y="583.22" class="st13" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Boot<v:newlineChar/><tspan
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+ <g id="shape1381-154" v:mID="1381" v:groupContext="shape" transform="translate(650.701,263.154) rotate(90)">
<title>Sheet.1381</title>
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+ <g id="shape1382-159" v:mID="1382" v:groupContext="shape" transform="translate(39.7692,-324)">
<title>Sheet.1382</title>
<desc>Pass</desc>
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+ <g id="shape1383-162" v:mID="1383" v:groupContext="shape" transform="translate(607.5,-417.442)">
<title>Sheet.1383</title>
<desc>Fail</desc>
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+ <g id="shape1385-165" v:mID="1385" v:groupContext="shape" transform="translate(656.25,-331.531)">
<title>Sheet.1385</title>
<desc>Fail</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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+ <g id="shape1386-168" v:mID="1386" v:groupContext="shape" transform="translate(618.385,-360.369)">
<title>Sheet.1386</title>
<desc>Pass</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<text x="5" y="605.29" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Pass</text> </g>
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+ <g id="shape1387-171" v:mID="1387" v:groupContext="shape" transform="translate(541.885,-372.442)">
<title>Sheet.1387</title>
<desc>Pass</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<text x="5" y="605.29" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Pass</text> </g>
- <g id="shape1388-178" v:mID="1388" v:groupContext="shape" transform="translate(540,-295.942)">
+ <g id="shape1388-174" v:mID="1388" v:groupContext="shape" transform="translate(540,-295.942)">
<title>Sheet.1388</title>
<desc>Pass</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<text x="5" y="605.29" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Pass</text> </g>
- <g id="shape1389-181" v:mID="1389" v:groupContext="shape" transform="translate(655.332,-462.258)">
+ <g id="shape1389-177" v:mID="1389" v:groupContext="shape" transform="translate(655.332,-462.258)">
<title>Sheet.1389</title>
<desc>If 2 fails,then Alert</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<text x="15.15" y="592.57" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>If 2 fails,then <tspan
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- <g id="shape1390-185" v:mID="1390" v:groupContext="shape" transform="translate(405.686,-377.502) rotate(-26.715)">
+ <g id="shape1390-181" v:mID="1390" v:groupContext="shape" transform="translate(405.686,-377.502) rotate(-26.715)">
<title>Sheet.1390</title>
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</g>
- <g id="shape1391-190" v:mID="1391" v:groupContext="shape" transform="translate(-55.2291,865.192) rotate(-120.131)">
+ <g id="shape1391-186" v:mID="1391" v:groupContext="shape" transform="translate(-55.2291,865.192) rotate(-120.131)">
<title>Sheet.1391</title>
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</g>
- <g id="shape1393-195" v:mID="1393" v:groupContext="shape" transform="translate(404.441,-93.0384)">
+ <g id="shape1393-191" v:mID="1393" v:groupContext="shape" transform="translate(404.441,-93.0384)">
<title>Sheet.1393</title>
<desc>If consecutive fail cnt > thresh, then Alert</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -409,7 +401,7 @@
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x="11" dy="1.2em" class="st4">cnt > thresh, then </tspan><tspan x="39.5" dy="1.2em" class="st4">Alert</tspan></text> </g>
- <g id="shape1396-200" v:mID="1396" v:groupContext="shape" transform="translate(18,-486)">
+ <g id="shape1396-196" v:mID="1396" v:groupContext="shape" transform="translate(18,-486)">
<title>Sheet.1396</title>
<desc>Boot Entropy Sub-State Machine (non-FIPS entropy)</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -417,7 +409,7 @@
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<text x="20.87" y="577.52" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Boot Entropy<v:newlineChar/><tspan
x="5.87" dy="1.2em" class="st4"> </tspan>Sub-State Machine <tspan x="7.26" dy="1.2em" class="st4">(non</tspan>-FIPS entropy)</text> </g>
- <g id="shape1398-205" v:mID="1398" v:groupContext="shape" transform="translate(572.336,-541.184)">
+ <g id="shape1398-201" v:mID="1398" v:groupContext="shape" transform="translate(572.336,-541.184)">
<title>Sheet.1398</title>
<desc>Startup Health Test Sub-State Machine</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -425,11 +417,7 @@
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x="7.25" dy="1.2em" class="st4">Sub</tspan>-State Machine</text> </g>
- <g id="shape1400-209" v:mID="1400" v:groupContext="shape" transform="translate(408.087,843.467) rotate(-178.035)">
- <title>Sheet.1400</title>
- <path d="M5.68 611 L6.03 611.07 A153 5.25 -1.97 0 0 153.09 609.83" class="st7"/>
- </g>
- <g id="shape1402-214" v:mID="1402" v:groupContext="shape" transform="translate(474.077,-165.104)">
+ <g id="shape1402-205" v:mID="1402" v:groupContext="shape" transform="translate(474.077,-165.104)">
<title>Sheet.1402</title>
<desc>Continuous Health Test Sub-State Machine</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -437,11 +425,11 @@
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<text x="12.21" y="592.57" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Continuous Health Test <tspan
x="21.94" dy="1.2em" class="st4">Sub</tspan>-State Machine</text> </g>
- <g id="shape1403-218" v:mID="1403" v:groupContext="shape" transform="translate(1187.42,298.092) rotate(90)">
+ <g id="shape1403-209" v:mID="1403" v:groupContext="shape" transform="translate(1187.42,298.092) rotate(90)">
<title>Sheet.1403</title>
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</g>
- <g id="shape1411-223" v:mID="1411" v:groupContext="shape" transform="translate(39.6614,-175.801)">
+ <g id="shape1411-214" v:mID="1411" v:groupContext="shape" transform="translate(39.6614,-175.801)">
<title>Sheet.1411</title>
<desc>If sw directed, then leave Alert state</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -449,11 +437,11 @@
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<text x="7.81" y="592.57" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>If sw directed, then <tspan
x="13.93" dy="1.2em" class="st4">leave Alert state</tspan></text> </g>
- <g id="shape1412-227" v:mID="1412" v:groupContext="shape" transform="translate(-178.092,137.547) rotate(-63.6879)">
+ <g id="shape1412-218" v:mID="1412" v:groupContext="shape" transform="translate(-178.092,137.547) rotate(-63.6879)">
<title>Sheet.1412</title>
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</g>
- <g id="shape1413-232" v:mID="1413" v:groupContext="shape" transform="translate(327,-265.5)">
+ <g id="shape1413-223" v:mID="1413" v:groupContext="shape" transform="translate(327,-265.5)">
<title>Sheet.1413</title>
<desc>SW directed</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<text x="18.95" y="593.32" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>SW <tspan x="9.21"
dy="1.2em" class="st4">directed</tspan></text> </g>
- <g id="shape1414-236" v:mID="1414" v:groupContext="shape" transform="translate(423,-245.75)">
+ <g id="shape1414-227" v:mID="1414" v:groupContext="shape" transform="translate(423,-245.75)">
<title>Sheet.1414</title>
<desc>Startup Passes</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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x="10.6" dy="1.2em" class="st4">Passes</tspan></text> </g>
- <g id="shape1422-240" v:mID="1422" v:groupContext="shape" transform="translate(303.024,-249.919) rotate(16.3322)">
- <title>Sheet.1422</title>
- <path d="M0 609.03 A25.4608 7.46078 -16.33 0 0 20.56 610.55 L20.91 610.46" class="st9"/>
- </g>
- <g id="shape1423-245" v:mID="1423" v:groupContext="shape" transform="translate(884.148,-235.013) rotate(16.8946)">
+ <g id="shape1423-231" v:mID="1423" v:groupContext="shape" transform="translate(884.148,-235.013) rotate(16.8946)">
<title>Sheet.1423</title>
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</g>
- <g id="shape1427-250" v:mID="1427" v:groupContext="shape" transform="translate(781.546,678.343) rotate(165.392)">
+ <g id="shape1427-236" v:mID="1427" v:groupContext="shape" transform="translate(781.546,678.343) rotate(165.392)">
<title>Sheet.1427</title>
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</g>
- <g id="shape1435-255" v:mID="1435" v:groupContext="shape" transform="translate(737.251,-107.133) rotate(22.7)">
+ <g id="shape1435-241" v:mID="1435" v:groupContext="shape" transform="translate(737.251,-107.133) rotate(22.7)">
<title>Sheet.1435</title>
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</g>
- <g id="shape1436-260" v:mID="1436" v:groupContext="shape" transform="translate(411.526,-326.485) rotate(38.9495)">
+ <g id="shape1436-246" v:mID="1436" v:groupContext="shape" transform="translate(411.526,-326.485) rotate(38.9495)">
<title>Sheet.1436</title>
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</g>
- <g id="shape1437-265" v:mID="1437" v:groupContext="shape" transform="translate(301.5,-56.3228)">
+ <g id="shape1437-251" v:mID="1437" v:groupContext="shape" transform="translate(301.5,-56.3228)">
<title>Sheet.1437</title>
<desc>Always Testing</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -497,11 +481,11 @@
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<text x="11.16" y="593.32" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Always<v:newlineChar/><tspan
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- <g id="shape1440-269" v:mID="1440" v:groupContext="shape" transform="translate(600.899,-417.35)">
+ <g id="shape1440-255" v:mID="1440" v:groupContext="shape" transform="translate(600.899,-417.35)">
<title>Sheet.1440</title>
<path d="M0 612 L48.27 612" class="st14"/>
</g>
- <g id="shape1441-274" v:mID="1441" v:groupContext="shape" transform="translate(189,-174)">
+ <g id="shape1441-260" v:mID="1441" v:groupContext="shape" transform="translate(189,-174)">
<title>Circle.1441</title>
<desc>Alert State</desc>
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@@ -512,24 +496,24 @@
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- <g id="shape1444-278" v:mID="1444" v:groupContext="shape" transform="translate(844.5,272.249) rotate(90)">
+ <g id="shape1444-264" v:mID="1444" v:groupContext="shape" transform="translate(844.5,272.249) rotate(90)">
<title>Sheet.1444</title>
<path d="M0 612 L72.59 612" class="st14"/>
</g>
- <g id="shape1448-283" v:mID="1448" v:groupContext="shape" transform="translate(-60.2072,-173.068) rotate(-30.436)">
+ <g id="shape1448-269" v:mID="1448" v:groupContext="shape" transform="translate(-60.2072,-173.068) rotate(-30.436)">
<title>Sheet.1448</title>
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</g>
- <g id="shape1449-288" v:mID="1449" v:groupContext="shape" transform="translate(104.608,975.397) rotate(-156.997)">
+ <g id="shape1449-274" v:mID="1449" v:groupContext="shape" transform="translate(104.608,975.397) rotate(-156.997)">
<title>Sheet.1449</title>
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</g>
- <g id="shape1455-293" v:mID="1455" v:groupContext="shape" transform="translate(306,-90)">
+ <g id="shape1455-279" v:mID="1455" v:groupContext="shape" transform="translate(306,-90)">
<title>Sheet.1455</title>
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- <g id="shape1543-298" v:mID="1543" v:groupContext="shape" transform="translate(168,-112.646)">
+ <g id="shape1543-284" v:mID="1543" v:groupContext="shape" transform="translate(168,-112.646)">
<title>Sheet.1543</title>
<desc>If alert fail, then hang</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -537,16 +521,16 @@
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- <g id="shape1544-302" v:mID="1544" v:groupContext="shape" transform="translate(168,-146.829)">
+ <g id="shape1544-288" v:mID="1544" v:groupContext="shape" transform="translate(168,-146.829)">
<title>Sheet.1544</title>
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- <g id="shape1546-307" v:mID="1546" v:groupContext="shape" transform="translate(-104.382,-159.731) rotate(-22.1134)">
+ <g id="shape1546-293" v:mID="1546" v:groupContext="shape" transform="translate(-104.382,-159.731) rotate(-22.1134)">
<title>Sheet.1546</title>
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- <g id="shape1548-312" v:mID="1548" v:groupContext="shape" transform="translate(104.231,-420.694)">
+ <g id="shape1548-298" v:mID="1548" v:groupContext="shape" transform="translate(104.231,-420.694)">
<title>Sheet.1548</title>
<desc>If consecutive fail cnt > thresh, then Alert</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
@@ -554,28 +538,28 @@
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- <g id="shape1549-317" v:mID="1549" v:groupContext="shape" transform="translate(197.269,-301.534)">
+ <g id="shape1549-303" v:mID="1549" v:groupContext="shape" transform="translate(197.269,-301.534)">
<title>Sheet.1549</title>
<desc>Alert</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
<v:textRect cx="16.1154" cy="602.286" width="32.24" height="19.4272"/>
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<text x="5.83" y="605.29" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Alert</text> </g>
- <g id="shape1550-320" v:mID="1550" v:groupContext="shape" transform="translate(310.885,-322.536)">
+ <g id="shape1550-306" v:mID="1550" v:groupContext="shape" transform="translate(310.885,-322.536)">
<title>Sheet.1550</title>
<desc>Alert</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<text x="5.83" y="605.29" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Alert</text> </g>
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+ <g id="shape1551-309" v:mID="1551" v:groupContext="shape" transform="translate(298.135,-216.411)">
<title>Sheet.1551</title>
<desc>Alert</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
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<rect x="0" y="592.573" width="32.2308" height="19.4272" class="st10"/>
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- <g id="shape1552-326" v:mID="1552" v:groupContext="shape" transform="translate(13.2205,-270)">
+ <g id="shape1552-312" v:mID="1552" v:groupContext="shape" transform="translate(13.2205,-270)">
<title>Circle.1552</title>
<desc>Post Test</desc>
<v:userDefs>
@@ -586,29 +570,41 @@
<path d="M0 586.52 A25.4808 25.4808 0 0 1 50.96 586.52 A25.4808 25.4808 0 1 1 0 586.52 Z" class="st3"/>
<text x="15.75" y="583.22" class="st13" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Post <tspan
x="16.07" dy="1.2em" class="st4">Test </tspan> </text> </g>
- <g id="shape1554-330" v:mID="1554" v:groupContext="shape" transform="translate(64.1821,-369)">
+ <g id="shape1554-316" v:mID="1554" v:groupContext="shape" transform="translate(64.1821,-369)">
<title>Sheet.1554</title>
<path d="M0 606.67 A25.8179 5.32648 -180 0 0 25.82 612 A63 58.5 -180 0 0 88.52 559.21 L88.54 558.86" class="st19"/>
</g>
- <g id="shape1555-336" v:mID="1555" v:groupContext="shape" transform="translate(310.5,-384.823)">
+ <g id="shape1555-322" v:mID="1555" v:groupContext="shape" transform="translate(256.22,-405)">
<title>Sheet.1555</title>
- <desc>Boot Passes</desc>
+ <desc>Boot Passes & MODULE_ENABLE Off</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
- <v:textRect cx="27" cy="596.323" width="54" height="31.3545"/>
- <rect x="0" y="580.646" width="54" height="31.3545" class="st10"/>
- <text x="16.71" y="593.32" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Boot<v:newlineChar/><tspan
- x="10.6" dy="1.2em" class="st4">Passes</tspan></text> </g>
- <g id="shape1556-340" v:mID="1556" v:groupContext="shape" transform="translate(-489.533,358.676) rotate(-96.3972)">
+ <v:textRect cx="49.7795" cy="586.519" width="99.56" height="50.9616"/>
+ <rect x="0" y="561.038" width="99.5591" height="50.9616" class="st10"/>
+ <text x="16.98" y="577.52" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Boot Passes &<v:newlineChar/><tspan
+ x="5.88" dy="1.2em" class="st4">MODULE_ENABLE </tspan><tspan x="43.11" dy="1.2em" class="st4">Off</tspan></text> </g>
+ <g id="shape1556-327" v:mID="1556" v:groupContext="shape" transform="translate(-489.533,358.676) rotate(-96.3972)">
<title>Sheet.1556</title>
<path d="M-0 607.05 A107.194 12.0184 -173.6 0 0 102.51 610.1 L102.82 609.92" class="st9"/>
</g>
- <g id="shape1557-345" v:mID="1557" v:groupContext="shape" transform="translate(108,-318.038)">
+ <g id="shape1557-332" v:mID="1557" v:groupContext="shape" transform="translate(101.25,-306)">
<title>Sheet.1557</title>
- <desc>Always in boot-only mode</desc>
+ <desc>MODULE_ENABLE Off</desc>
<v:textBlock v:margins="rect(4,4,4,4)"/>
- <v:textRect cx="32.25" cy="586.519" width="64.51" height="50.9616"/>
- <rect x="0" y="561.038" width="64.5" height="50.9616" class="st10"/>
- <text x="11.13" y="577.52" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Always in <tspan
- x="11.68" dy="1.2em" class="st4">boot</tspan>-only <tspan x="19.74" dy="1.2em" class="st4">mode</tspan></text> </g>
+ <v:textRect cx="57.375" cy="586.519" width="114.75" height="50.9616"/>
+ <rect x="0" y="561.038" width="114.75" height="50.9616" class="st10"/>
+ <text x="13.47" y="583.52" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>MODULE_ENABLE<v:newlineChar/><tspan
+ x="49.32" dy="1.2em" class="st4"> </tspan>Off</text> </g>
+ <g id="shape1564-336" v:mID="1564" v:groupContext="shape" transform="translate(-197.058,-89.1753) rotate(-52.8565)">
+ <title>Sheet.1564</title>
+ <path d="M0 577.48 A148.971 100.388 -34.14 0 0 174.27 580.85 L174.58 580.65" class="st9"/>
+ </g>
+ <g id="shape1565-341" v:mID="1565" v:groupContext="shape" transform="translate(400.5,-431.735)">
+ <title>Sheet.1565</title>
+ <desc>FIPS_ENABLE On</desc>
+ <v:textBlock v:margins="rect(4,4,4,4)"/>
+ <v:textRect cx="40.5" cy="588.484" width="81" height="47.0317"/>
+ <rect x="0" y="564.968" width="81" height="47.0317" class="st10"/>
+ <text x="6.87" y="585.48" class="st11" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>FIPS_ENABLE <tspan
+ x="33.83" dy="1.2em" class="st4">On</tspan></text> </g>
</g>
</svg>
diff --git a/hw/ip/entropy_src/doc/es_main_sm.vsdx b/hw/ip/entropy_src/doc/es_main_sm.vsdx
index 16b2c6e..6a212c7 100644
--- a/hw/ip/entropy_src/doc/es_main_sm.vsdx
+++ b/hw/ip/entropy_src/doc/es_main_sm.vsdx
Binary files differ
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv b/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv
index 4e97aef..03b5e0b 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv
@@ -41,11 +41,13 @@
// Knobs & Weights //
/////////////////////
- uint enable_pct, route_software_pct, regwen_pct, fw_read_pct, fw_over_pct,
- otp_en_es_fw_read_pct, otp_en_es_fw_over_pct, entropy_data_reg_enable_pct,
- rng_bit_enable_pct, do_check_ht_diag_pct, type_bypass_pct, boot_bypass_disable_pct;
-
+ // Knobs & Weights
+ uint module_enable_pct, fips_enable_pct, route_software_pct,
+ sw_regupd_pct, me_regwen_pct, fw_read_pct, fw_over_pct,
+ otp_en_es_fw_read_pct, otp_en_es_fw_over_pct,
+ type_bypass_pct, entropy_data_reg_enable_pct,
+ rng_bit_enable_pct, do_check_ht_diag_pct;
// Health test knobs:
real adaptp_sigma_max, adaptp_sigma_min;
@@ -56,12 +58,11 @@
// Randomized fields //
///////////////////////
- rand bit regwen;
+ rand bit sw_regupd, me_regwen;
rand bit [1:0] rng_bit_sel;
- rand prim_mubi_pkg::mubi4_t enable, route_software, type_bypass,
- boot_bypass_disable, entropy_data_reg_enable,
- rng_bit_enable;
+ rand prim_mubi_pkg::mubi4_t module_enable, fips_enable, route_software, type_bypass,
+ entropy_data_reg_enable, rng_bit_enable;
rand int observe_fifo_thresh;
@@ -95,9 +96,13 @@
// Constraints //
/////////////////
- constraint regwen_c {regwen dist {
- 1 :/ regwen_pct,
- 0 :/ (100 - regwen_pct) };}
+ constraint sw_regupd_c {sw_regupd dist {
+ 1 :/ sw_regupd_pct,
+ 0 :/ (100 - sw_regupd_pct) };}
+
+ constraint me_regwen_c {me_regwen dist {
+ 1 :/ me_regwen_pct,
+ 0 :/ (100 - me_regwen_pct) };}
constraint otp_en_es_fw_read_c {otp_en_es_fw_read dist {
prim_mubi_pkg::MuBi8True :/ otp_en_es_fw_read_pct,
@@ -115,9 +120,13 @@
prim_mubi_pkg::MuBi4True :/ fw_over_pct,
prim_mubi_pkg::MuBi4False :/ (100 - fw_over_pct) };}
- constraint enable_c {enable dist {
- prim_mubi_pkg::MuBi4True :/ enable_pct,
- prim_mubi_pkg::MuBi4False :/ 100 - enable_pct };}
+ constraint module_enable_c {module_enable dist {
+ prim_mubi_pkg::MuBi4True :/ module_enable_pct,
+ prim_mubi_pkg::MuBi4False :/ 100 - module_enable_pct };}
+
+ constraint fips_enable_c {fips_enable dist {
+ prim_mubi_pkg::MuBi4True :/ fips_enable_pct,
+ prim_mubi_pkg::MuBi4False :/ 100 - fips_enable_pct };}
constraint route_c {route_software dist {
prim_mubi_pkg::MuBi4True :/ route_software_pct,
@@ -127,10 +136,6 @@
prim_mubi_pkg::MuBi4True :/ type_bypass_pct,
prim_mubi_pkg::MuBi4False :/ (100 - type_bypass_pct) };}
- constraint boot_bypass_disable_c {boot_bypass_disable dist {
- prim_mubi_pkg::MuBi4True :/ boot_bypass_disable_pct,
- prim_mubi_pkg::MuBi4False :/ (100 - boot_bypass_disable_pct)};}
-
constraint entropy_data_reg_enable_c {entropy_data_reg_enable dist {
prim_mubi_pkg::MuBi4True :/ entropy_data_reg_enable_pct,
prim_mubi_pkg::MuBi4False :/ (100 - entropy_data_reg_enable_pct)};}
@@ -179,16 +184,16 @@
otp_en_es_fw_read.name()),
$sformatf("\n\t |***** otp_en_es_fw_over : %12s *****| \t",
otp_en_es_fw_over.name()),
- $sformatf("\n\t |***** enable : %12s *****| \t",
- enable.name()),
+ $sformatf("\n\t |***** module_enable : %12s *****| \t",
+ module_enable.name()),
+ $sformatf("\n\t |***** fips_enable : %12s *****| \t",
+ fips_enable.name()),
$sformatf("\n\t |***** route_software : %12s *****| \t",
route_software.name()),
$sformatf("\n\t |***** type_bypass : %12s *****| \t",
type_bypass.name()),
$sformatf("\n\t |***** entropy_data_reg_enable : %12s *****| \t",
entropy_data_reg_enable.name()),
- $sformatf("\n\t |***** boot_bypass_disable : %12s *****| \t",
- boot_bypass_disable.name()),
$sformatf("\n\t |***** rng_bit_enable : %12s *****| \t",
rng_bit_enable.name()),
$sformatf("\n\t |***** rng_bit_sel : %12d *****| \t",
@@ -229,16 +234,16 @@
fw_read_pct),
$sformatf("\n\t |***** fw_over_pct : %12d *****| \t",
fw_over_pct),
- $sformatf("\n\t |***** enable_pct : %12d *****| \t",
- enable_pct),
+ $sformatf("\n\t |***** module_enable_pct : %12d *****| \t",
+ module_enable_pct),
+ $sformatf("\n\t |***** fips_enable_pct : %12d *****| \t",
+ fips_enable_pct),
$sformatf("\n\t |***** route_software_pct : %12d *****| \t",
route_software_pct),
$sformatf("\n\t |***** type_bypass_pct : %12d *****| \t",
type_bypass_pct),
$sformatf("\n\t |***** entropy_data_reg_enable_pct : %12d *****| \t",
entropy_data_reg_enable_pct),
- $sformatf("\n\t |***** boot_bypass_disable_pct : %12d *****| \t",
- boot_bypass_disable_pct),
$sformatf("\n\t |***** rng_bit_enable_pct : %12d *****| \t",
rng_bit_enable_pct),
$sformatf("\n\t |***** adaptp_sigma range : (%04.2f, %04.2f) *****| \t",
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv b/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv
index 748034d..785d0f7 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv
@@ -34,7 +34,7 @@
NumEntropySrcIntr = 4
} entropy_src_intr_e;
- typedef enum { BOOT, STARTUP, CONTINUOUS } entropy_phase_e;
+ typedef enum { BOOT, STARTUP, CONTINUOUS, HALTED } entropy_phase_e;
typedef bit [RNG_BUS_WIDTH-1:0] rng_val_t;
typedef rng_val_t queue_of_rng_val_t[$];
@@ -51,18 +51,13 @@
// satisfy both the startup and (optional) boot phases.
//
function automatic entropy_phase_e convert_seed_idx_to_phase(int seed_idx,
- bit conditioning_bypass,
- bit boot_disable);
+ bit fips_enable);
- if (conditioning_bypass) begin
- return BOOT;
- end else if (!boot_disable) begin
+ if (!fips_enable) begin
if (seed_idx == 0) begin
return BOOT;
- end else if (seed_idx == 1) begin
- return STARTUP;
end else begin
- return CONTINUOUS;
+ return HALTED;
end
end else begin
if (seed_idx == 0) begin
@@ -82,14 +77,13 @@
//
// The window size also dictates the ammount of data needed to create a single seed.
//
- function automatic int rng_window_size(int seed_idx, bit bypass,
- bit boot_disable, int fips_window_size);
+ function automatic int rng_window_size(int seed_idx, bit fips_enable, int fips_window_size);
entropy_phase_e phase;
// Counts the number of seeds that have been successfully generated
// in any post-boot phase.
- phase = convert_seed_idx_to_phase(seed_idx, bypass, boot_disable);
+ phase = convert_seed_idx_to_phase(seed_idx, fips_enable);
return (phase == BOOT) ? entropy_src_pkg::CSRNG_BUS_WIDTH : fips_window_size;
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
index d01f6c5..4d85cb0 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
@@ -740,7 +740,9 @@
end
"intr_test": begin
end
- "regwen_me": begin
+ "me_regwen": begin
+ end
+ "sw_regupd": begin
end
"regwen": begin
end
@@ -882,8 +884,7 @@
int pass_cnt;
dut_phase = convert_seed_idx_to_phase(seed_idx,
- cfg.type_bypass == prim_mubi_pkg::MuBi4True,
- cfg.boot_bypass_disable == prim_mubi_pkg::MuBi4True);
+ cfg.fips_enable == prim_mubi_pkg::MuBi4True);
sample_rng_frames = sample.size();
@@ -1017,8 +1018,7 @@
`uvm_info(`gfn, $sformatf("SEED_IDX: %01d", seed_idx), UVM_FULL)
dut_fsm_phase = convert_seed_idx_to_phase(seed_idx,
- cfg.type_bypass == prim_mubi_pkg::MuBi4True,
- cfg.boot_bypass_disable == prim_mubi_pkg::MuBi4True);
+ cfg.fips_enable == prim_mubi_pkg::MuBi4True);
case (dut_fsm_phase)
BOOT: begin
@@ -1033,6 +1033,10 @@
pass_requirement = 1;
ht_fips_mode = 1;
end
+ HALTED: begin
+ // exit this task.
+ return;
+ end
default: begin
`uvm_fatal(`gfn, "Invalid predicted dut state (bug in environment)")
end
@@ -1040,8 +1044,7 @@
`uvm_info(`gfn, $sformatf("phase: %s\n", dut_fsm_phase.name), UVM_HIGH)
- window_size = rng_window_size(seed_idx, cfg.type_bypass == prim_mubi_pkg::MuBi4True,
- cfg.boot_bypass_disable == prim_mubi_pkg::MuBi4True,
+ window_size = rng_window_size(seed_idx, cfg.fips_enable == prim_mubi_pkg::MuBi4True,
cfg.fips_window_size);
`uvm_info(`gfn, $sformatf("window_size: %08d\n", window_size), UVM_HIGH)
diff --git a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
index addf334..c8bc13f 100644
--- a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
+++ b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
@@ -106,6 +106,7 @@
csr_update(.csr(ral.entropy_control));
// Thresholds managed in derived vseq classes
+ // TODO: Study how this interacts with sw_regupd/regwen
// FW_OV registers
ral.fw_ov_control.fw_ov_mode.set(cfg.fw_read_enable);
@@ -116,27 +117,29 @@
csr_update(ral.observe_fifo_thresh);
// Enables (should be done last)
- ral.conf.fips_enable.set(cfg.enable);
-
+ ral.conf.fips_enable.set(cfg.fips_enable);
ral.conf.entropy_data_reg_enable.set(cfg.entropy_data_reg_enable);
- ral.conf.boot_bypass_disable.set(cfg.boot_bypass_disable);
ral.conf.rng_bit_enable.set(cfg.rng_bit_enable);
ral.conf.rng_bit_sel.set(cfg.rng_bit_sel);
csr_update(.csr(ral.conf));
+ // Register write enable lock is on be default
+ // Setting this to zero will lock future writes
+ // TODO Do we need to check main_sm_idle before writing DUT registers?
+ csr_wr(.ptr(ral.sw_regupd), .value(cfg.sw_regupd));
- ral.module_enable.set(cfg.enable); // TODO: Change config here?
+ // Module_enables (should be done last)
+ ral.module_enable.set(cfg.module_enable); // TODO: Change config here?
csr_update(.csr(ral.module_enable));
+ ral.me_regwen.set(cfg.me_regwen);
+ csr_update(.csr(ral.me_regwen));
+
if (do_interrupt) begin
ral.intr_enable.set(en_intr);
csr_update(ral.intr_enable);
end
- // Register write enable lock is on be default
- // Setting this to zero will lock future writes
- // TODO Do we need to check main_sm_idle before writing DUT registers?
- csr_wr(.ptr(ral.regwen), .value(cfg.regwen));
endtask
diff --git a/hw/ip/entropy_src/dv/tests/entropy_src_base_test.sv b/hw/ip/entropy_src/dv/tests/entropy_src_base_test.sv
index 0bc0e27..cf70ed2 100644
--- a/hw/ip/entropy_src/dv/tests/entropy_src_base_test.sv
+++ b/hw/ip/entropy_src/dv/tests/entropy_src_base_test.sv
@@ -31,8 +31,8 @@
cfg.seed_cnt = 1;
cfg.otp_en_es_fw_read_pct = 100;
cfg.otp_en_es_fw_over_pct = 100;
- cfg.regwen_pct = 100;
- cfg.enable_pct = 100;
+ cfg.me_regwen_pct = 100;
+ cfg.module_enable_pct = 100;
cfg.type_bypass_pct = 100;
endfunction
diff --git a/hw/ip/entropy_src/dv/tests/entropy_src_rng_test.sv b/hw/ip/entropy_src/dv/tests/entropy_src_rng_test.sv
index df2792f..976f824 100644
--- a/hw/ip/entropy_src/dv/tests/entropy_src_rng_test.sv
+++ b/hw/ip/entropy_src/dv/tests/entropy_src_rng_test.sv
@@ -30,7 +30,8 @@
// Allow for software reads, but let the vseq body do the enabling
cfg.route_software_pct = 0;
- cfg.enable_pct = 0;
+ cfg.module_enable_pct = 0;
+ cfg.fips_enable_pct = 100;
`DV_CHECK_RANDOMIZE_FATAL(cfg)
`uvm_info(`gfn, $sformatf("%s", cfg.convert2string()), UVM_LOW)
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index 5bb085a..b2c9420 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -85,7 +85,6 @@
logic fw_ov_fifo_rd_pulse;
logic fw_ov_fifo_wr_pulse;
logic es_enable_pfa;
- logic es_enable_early;
logic fips_enable_pfe;
logic fips_enable_pfa;
@@ -140,6 +139,7 @@
logic any_fail_pulse;
logic main_stage_push;
logic bypass_stage_pop;
+ logic boot_phase_done;
logic [HalfRegWidth-1:0] any_fail_count;
logic any_fails_cntr_err;
logic alert_threshold_fail;
@@ -155,8 +155,6 @@
logic extht_active;
logic alert_cntrs_clr;
logic health_test_clr;
- logic health_test_clr_pfe;
- logic health_test_clr_pfa;
logic health_test_done_pulse;
logic [RngBusWidth-1:0] health_test_esbus;
logic health_test_esbus_vld;
@@ -167,11 +165,11 @@
logic es_route_to_sw;
logic es_bypass_to_sw;
logic es_bypass_mode;
- logic rst_bypass_mode;
logic rst_alert_cntr;
- logic boot_bypass_disable;
- logic boot_bypass_disable_pfe;
- logic boot_bypass_disable_pfa;
+ logic threshold_scope;
+ logic unused_threshold_scope;
+ logic threshold_scope_pfe;
+ logic threshold_scope_pfa;
logic fips_compliance;
logic [HalfRegWidth-1:0] health_test_fips_window;
@@ -374,7 +372,7 @@
logic es_bus_cmp_alert;
logic es_thresh_cfg_alert;
logic es_main_sm_idle;
- logic [7:0] es_main_sm_state;
+ logic [8:0] es_main_sm_state;
logic fifo_write_err_sum;
logic fifo_read_err_sum;
logic fifo_status_err_sum;
@@ -417,7 +415,6 @@
logic unused_sha3_state;
logic unused_entropy_data;
logic unused_fw_ov_rd_data;
- logic unused_health_test_clr_pfe;
prim_mubi_pkg::mubi8_t en_entropy_src_fw_read;
prim_mubi_pkg::mubi8_t en_entropy_src_fw_over;
@@ -427,7 +424,6 @@
logic [RngBusWidth-1:0] ht_esbus_dly_q, ht_esbus_dly_d;
logic ht_esbus_vld_dly_q, ht_esbus_vld_dly_d;
logic ht_esbus_vld_dly2_q, ht_esbus_vld_dly2_d;
- logic boot_bypass_q, boot_bypass_d;
logic ht_failed_q, ht_failed_d;
logic ht_done_pulse_q, ht_done_pulse_d;
logic sha3_msg_rdy_q, sha3_msg_rdy_d;
@@ -438,7 +434,6 @@
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
- boot_bypass_q <= 1'b1;
ht_failed_q <= '0;
ht_done_pulse_q <= '0;
ht_esbus_dly_q <= '0;
@@ -450,7 +445,6 @@
es_rdata_capt_q <= '0;
es_rdata_capt_vld_q <= '0;
end else begin
- boot_bypass_q <= boot_bypass_d;
ht_failed_q <= ht_failed_d;
ht_done_pulse_q <= ht_done_pulse_d;
ht_esbus_dly_q <= ht_esbus_dly_d;
@@ -468,13 +462,13 @@
import prim_mubi_pkg::mubi4_test_false_loose;
import prim_mubi_pkg::mubi4_test_invalid;
- mubi4_t [4:0] mubi_module_en_fanout;
+ mubi4_t [3:0] mubi_module_en_fanout;
//--------------------------------------------
// register lock gating
//--------------------------------------------
- assign es_hw_regwen = reg2hw.sw_regupd.q && mubi4_test_false_loose(mubi_module_en_fanout[4]);
+ assign es_hw_regwen = reg2hw.sw_regupd.q && mubi4_test_false_loose(mubi_module_en_fanout[3]);
assign hw2reg.regwen.de = 1'b1;
assign hw2reg.regwen.d = es_hw_regwen;
@@ -492,7 +486,7 @@
assign hw2reg.recov_alert_sts.module_enable_field_alert.d = es_enable_pfa;
prim_mubi4_sync #(
- .NumCopies(5),
+ .NumCopies(4),
.AsyncOn(0)
) u_prim_mubi4_sync_entropy_module_en (
.clk_i,
@@ -552,7 +546,6 @@
.mubi_o(mubi_entropy_reg_en_fanout)
);
- assign es_enable_early = mubi4_test_true_strict(mubi_module_en_fanout[2]);
assign observe_fifo_thresh = reg2hw.observe_fifo_thresh.q;
// SEC_CM: CONFIG.MUBI
@@ -796,6 +789,7 @@
// state machine status
assign hw2reg.debug_status.main_sm_idle.d = es_main_sm_idle;
+ assign hw2reg.debug_status.main_sm_boot_done.d = boot_phase_done;
assign hw2reg.debug_status.main_sm_state.d = es_main_sm_state;
//--------------------------------------------
@@ -908,16 +902,7 @@
assign markov_active = es_enable_q_fo[22];
assign extht_active = es_enable_q_fo[23];
- // TODO: Remove health_test_clr bit
- // SEC_CM: CONFIG.MUBI
- mubi4_t mubi_ht_clr;
- assign mubi_ht_clr = mubi4_t'(reg2hw.conf.health_test_clr.q);
- assign health_test_clr_pfe = mubi4_test_true_strict(mubi_ht_clr);
- assign health_test_clr_pfa = mubi4_test_invalid(mubi_ht_clr);
- assign hw2reg.recov_alert_sts.health_test_clr_field_alert.de = health_test_clr_pfa;
- assign hw2reg.recov_alert_sts.health_test_clr_field_alert.d = health_test_clr_pfa;
-
- assign health_test_clr = mubi4_test_true_strict(mubi_module_en_fanout[3]) && !es_enable_q_fo[24];
+ assign health_test_clr = mubi4_test_true_strict(mubi_module_en_fanout[2]) && !es_enable_q_fo[24];
assign health_test_fips_window = reg2hw.health_test_windows.fips_window.q;
assign health_test_bypass_window = reg2hw.health_test_windows.bypass_window.q;
@@ -1306,26 +1291,21 @@
.mubi_o(mubi_es_type_fanout)
);
- // TODO: Remove boot_bypass_disable Issue #9853
+ // TODO(#9759): add more description.
// SEC_CM: CONFIG.MUBI
- mubi4_t mubi_boot_byp_dis;
- assign mubi_boot_byp_dis = mubi4_t'(reg2hw.conf.boot_bypass_disable.q);
- assign boot_bypass_disable_pfe = mubi4_test_true_strict(mubi_boot_byp_dis);
- assign boot_bypass_disable_pfa = mubi4_test_invalid(mubi_boot_byp_dis);
- assign hw2reg.recov_alert_sts.boot_bypass_disable_field_alert.de = boot_bypass_disable_pfa;
- assign hw2reg.recov_alert_sts.boot_bypass_disable_field_alert.d = boot_bypass_disable_pfa;
+ mubi4_t mubi_thresh_scope;
+ assign mubi_thresh_scope = mubi4_t'(reg2hw.conf.threshold_scope.q);
+ assign threshold_scope_pfe = mubi4_test_true_strict(mubi_thresh_scope);
+ assign threshold_scope_pfa = mubi4_test_invalid(mubi_thresh_scope);
+ assign hw2reg.recov_alert_sts.threshold_scope_field_alert.de = threshold_scope_pfa;
+ assign hw2reg.recov_alert_sts.threshold_scope_field_alert.d = threshold_scope_pfa;
+ assign unused_threshold_scope = threshold_scope;
assign es_route_to_sw = es_route_pfe;
assign es_bypass_to_sw = es_type_pfe;
- assign boot_bypass_disable = boot_bypass_disable_pfe;
+ assign threshold_scope = threshold_scope_pfe;
- assign boot_bypass_d =
- (!es_enable_early) ? 1'b1 : // special case for reset
- boot_bypass_disable ? 1'b0 :
- rst_bypass_mode ? 1'b0 :
- boot_bypass_q;
-
- assign es_bypass_mode = boot_bypass_q || es_bypass_to_sw;
+ assign es_bypass_mode = (!fips_enable_pfe) || es_bypass_to_sw;
// send off to AST RNG for possibly faster entropy generation
assign rng_fips_o = es_bypass_mode;
@@ -1940,8 +1920,7 @@
es_enable_pfa ||
fips_enable_pfa ||
entropy_data_reg_en_pfa ||
- boot_bypass_disable_pfa ||
- health_test_clr_pfa ||
+ threshold_scope_pfa ||
rng_bit_enable_pfa ||
fw_ov_mode_pfa ||
fw_ov_entropy_insert_pfa ||
@@ -2321,12 +2300,12 @@
.sfifo_esfinal_full_i (sfifo_esfinal_full),
.rst_alert_cntr_o (rst_alert_cntr),
.bypass_mode_i (es_bypass_mode),
- .rst_bypass_mode_o (rst_bypass_mode),
.main_stage_rdy_i (pfifo_cond_not_empty),
.bypass_stage_rdy_i (pfifo_bypass_not_empty),
.sha3_state_vld_i (sha3_state_vld),
.main_stage_push_o (main_stage_push),
.bypass_stage_pop_o (bypass_stage_pop),
+ .boot_phase_done_o (boot_phase_done),
.sha3_start_o (sha3_start),
.sha3_process_o (sha3_process),
.sha3_done_o (sha3_done),
@@ -2385,15 +2364,7 @@
assign es_hw_if_req = entropy_src_hw_if_i.es_req;
assign entropy_src_hw_if_o.es_ack = es_hw_if_ack;
assign entropy_src_hw_if_o.es_bits = esfinal_data;
- // TODO: The following is a placeholder for the final implementation
- // for blocking non-FIPS data. Please see PR #9949 & Issue 9853
- // for details.
- //
- // For now data is simply masked if fips_enable is not set
- // but this does not prevent previously queued seeds from
- // exiting once FIPS_ENABLE is asserted.
- assign entropy_src_hw_if_o.es_fips = esfinal_fips_flag
- && fips_enable_pfe; // TODO: Fix fips_enable_pfe
+ assign entropy_src_hw_if_o.es_fips = esfinal_fips_flag;
// SEC_CM: ACK_SM.FSM.SPARSE
entropy_src_ack_sm u_entropy_src_ack_sm (
@@ -2484,7 +2455,6 @@
assign unused_sha3_state = (|sha3_state[0][sha3_pkg::StateW-1:SeedLen]);
assign unused_entropy_data = (|reg2hw.entropy_data.q);
assign unused_fw_ov_rd_data = (|reg2hw.fw_ov_rd_data.q);
- assign unused_health_test_clr_pfe = health_test_clr_pfe;
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
index 77f03f9..7090966 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
@@ -7,7 +7,7 @@
// determines when new entropy is ready to be forwarded
module entropy_src_main_sm #(
- localparam int StateWidth = 8
+ localparam int StateWidth = 9
) (
input logic clk_i,
input logic rst_ni,
@@ -19,12 +19,12 @@
input logic sfifo_esfinal_full_i,
output logic rst_alert_cntr_o,
input logic bypass_mode_i,
- output logic rst_bypass_mode_o,
input logic main_stage_rdy_i,
input logic bypass_stage_rdy_i,
input logic sha3_state_vld_i,
output logic main_stage_push_o,
output logic bypass_stage_pop_o,
+ output logic boot_phase_done_o,
output logic sha3_start_o,
output logic sha3_process_o,
output logic sha3_done_o,
@@ -38,46 +38,48 @@
);
// Encoding generated with:
-// $ ./util/design/sparse-fsm-encode.py -d 3 -m 18 -n 8 \
-// -s 281987796 --language=sv
+// $ ./util/design/sparse-fsm-encode.py -d 3 -m 19 -n 9 \
+// -s 1097041703 --language=sv
//
// Hamming distance histogram:
//
// 0: --
// 1: --
// 2: --
-// 3: |||||||||||||||| (31.37%)
-// 4: |||||||||||||||||||| (37.91%)
-// 5: |||||||| (15.69%)
-// 6: |||| (9.15%)
-// 7: ||| (5.88%)
-// 8: --
+// 3: |||||||||||||| (19.88%)
+// 4: |||||||||||||||||||| (27.49%)
+// 5: |||||||||||||||||| (25.73%)
+// 6: |||||||||||| (17.54%)
+// 7: ||||| (7.02%)
+// 8: | (2.34%)
+// 9: --
//
// Minimum Hamming distance: 3
-// Maximum Hamming distance: 7
+// Maximum Hamming distance: 8
// Minimum Hamming weight: 2
// Maximum Hamming weight: 7
//
typedef enum logic [StateWidth-1:0] {
- Idle = 8'b10001000, // idle
- BootHTRunning = 8'b11101100, // boot mode, wait for health test done pulse
- BootPostHTChk = 8'b01000001, // boot mode, wait for post health test packer not empty state
- StartupHTStart = 8'b00100110, // startup mode, pulse the sha3 start input
- StartupPhase1 = 8'b11110110, // startup mode, look for first test pass/fail
- StartupPass1 = 8'b01110000, // startup mode, look for first test pass/fail, done if pass
- StartupFail1 = 8'b00101101, // startup mode, look for second fail, alert if fail
- ContHTStart = 8'b01101010, // continuous test mode, pulse the sha3 start input
- ContHTRunning = 8'b11111001, // continuous test mode, wait for health test done pulse
- Sha3MsgDone = 8'b10010011, // sha3 mode, all input messages added, ready to process
- Sha3Prep = 8'b00001011, // sha3 mode, request csrng arb to reduce power
- Sha3Process = 8'b01111111, // sha3 mode, pulse the sha3 process input
- Sha3Valid = 8'b00010101, // sha3 mode, wait for sha3 valid indication
- Sha3Done = 8'b10111010, // sha3 mode, capture sha3 result, pulse done input
- Sha3Quiesce = 8'b00011110, // sha3 mode, goto alert state or continuous check mode
- AlertState = 8'b11000010, // if some alert condition occurs, pulse an alert indication
- AlertHang = 8'b10100001, // after pulsing alert signal, hang here until sw handles
- Error = 8'b11001111 // illegal state reached and hang
+ Idle = 9'b001011110, // idle
+ BootHTRunning = 9'b010101111, // boot mode, wait for health test done pulse
+ BootPostHTChk = 9'b011001101, // boot mode, wait for post health test packer not empty state
+ BootPhaseDone = 9'b101011000, // boot mode, stay here until master enable is off
+ StartupHTStart = 9'b000111011, // startup mode, pulse the sha3 start input
+ StartupPhase1 = 9'b010111000, // startup mode, look for first test pass/fail
+ StartupPass1 = 9'b000010101, // startup mode, look for first test pass/fail, done if pass
+ StartupFail1 = 9'b001100100, // startup mode, look for second fail, alert if fail
+ ContHTStart = 9'b111010011, // continuous test mode, pulse the sha3 start input
+ ContHTRunning = 9'b100101000, // continuous test mode, wait for health test done pulse
+ Sha3MsgDone = 9'b000100001, // sha3 mode, all input messages added, ready to process
+ Sha3Prep = 9'b011100010, // sha3 mode, request csrng arb to reduce power
+ Sha3Process = 9'b101001111, // sha3 mode, pulse the sha3 process input
+ Sha3Valid = 9'b110111110, // sha3 mode, wait for sha3 valid indication
+ Sha3Done = 9'b011010000, // sha3 mode, capture sha3 result, pulse done input
+ Sha3Quiesce = 9'b110010100, // sha3 mode, goto alert state or continuous check mode
+ AlertState = 9'b110100011, // if some alert condition occurs, pulse an alert indication
+ AlertHang = 9'b100010010, // after pulsing alert signal, hang here until sw handles
+ Error = 9'b100100110 // illegal state reached and hang
} state_e;
state_e state_d, state_q;
@@ -103,10 +105,10 @@
always_comb begin
state_d = state_q;
- rst_bypass_mode_o = 1'b0;
rst_alert_cntr_o = 1'b0;
main_stage_push_o = 1'b0;
bypass_stage_pop_o = 1'b0;
+ boot_phase_done_o = 1'b0;
sha3_start_o = 1'b0;
sha3_process_o = 1'b0;
sha3_done_o = 1'b0;
@@ -152,18 +154,21 @@
if (!bypass_stage_rdy_i) begin
end else begin
rst_alert_cntr_o = 1'b1;
- rst_bypass_mode_o = 1'b1;
bypass_stage_pop_o = 1'b1;
main_stage_push_o = 1'b1;
- state_d = StartupHTStart;
+ state_d = BootPhaseDone;
end
end
end
+ BootPhaseDone: begin
+ boot_phase_done_o = 1'b1;
+ if (!enable_i) begin
+ state_d = Idle;
+ end
+ end
StartupHTStart: begin
if (!enable_i || sfifo_esfinal_full_i) begin
state_d = Idle;
- end else if (bypass_mode_i) begin
- state_d = BootHTRunning;
end else begin
sha3_start_o = 1'b1;
state_d = StartupPhase1;
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index cffe8f0..51a4925 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -93,10 +93,7 @@
} entropy_data_reg_enable;
struct packed {
logic [3:0] q;
- } boot_bypass_disable;
- struct packed {
- logic [3:0] q;
- } health_test_clr;
+ } threshold_scope;
struct packed {
logic [3:0] q;
} rng_bit_enable;
@@ -554,7 +551,10 @@
logic d;
} main_sm_idle;
struct packed {
- logic [7:0] d;
+ logic d;
+ } main_sm_boot_done;
+ struct packed {
+ logic [8:0] d;
} main_sm_state;
} entropy_src_hw2reg_debug_status_reg_t;
@@ -574,11 +574,7 @@
struct packed {
logic d;
logic de;
- } boot_bypass_disable_field_alert;
- struct packed {
- logic d;
- logic de;
- } health_test_clr_field_alert;
+ } threshold_scope_field_alert;
struct packed {
logic d;
logic de;
@@ -654,13 +650,13 @@
// Register -> HW type
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [544:541]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [540:537]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [536:529]
- entropy_src_reg2hw_alert_test_reg_t alert_test; // [528:525]
- entropy_src_reg2hw_sw_regupd_reg_t sw_regupd; // [524:524]
- entropy_src_reg2hw_module_enable_reg_t module_enable; // [523:520]
- entropy_src_reg2hw_conf_reg_t conf; // [519:498]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [540:537]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [536:533]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [532:525]
+ entropy_src_reg2hw_alert_test_reg_t alert_test; // [524:521]
+ entropy_src_reg2hw_sw_regupd_reg_t sw_regupd; // [520:520]
+ entropy_src_reg2hw_module_enable_reg_t module_enable; // [519:516]
+ entropy_src_reg2hw_conf_reg_t conf; // [515:498]
entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [497:490]
entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [489:457]
entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [456:425]
@@ -717,8 +713,8 @@
entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [130:103]
entropy_src_hw2reg_extht_fail_counts_reg_t extht_fail_counts; // [102:95]
entropy_src_hw2reg_fw_ov_rd_data_reg_t fw_ov_rd_data; // [94:63]
- entropy_src_hw2reg_debug_status_reg_t debug_status; // [62:44]
- entropy_src_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [43:18]
+ entropy_src_hw2reg_debug_status_reg_t debug_status; // [62:42]
+ entropy_src_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [41:18]
entropy_src_hw2reg_err_code_reg_t err_code; // [17:0]
} entropy_src_hw2reg_t;
@@ -842,7 +838,7 @@
parameter logic [7:0] ENTROPY_SRC_EXTHT_FAIL_COUNTS_RESVAL = 8'h 0;
parameter logic [31:0] ENTROPY_SRC_FW_OV_RD_DATA_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_FW_OV_WR_DATA_RESVAL = 32'h 0;
- parameter logic [31:0] ENTROPY_SRC_DEBUG_STATUS_RESVAL = 32'h 0;
+ parameter logic [28:0] ENTROPY_SRC_DEBUG_STATUS_RESVAL = 29'h 0;
// Register index
typedef enum int {
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index 461d170..d0cb6e1 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -152,10 +152,8 @@
logic [3:0] conf_fips_enable_wd;
logic [3:0] conf_entropy_data_reg_enable_qs;
logic [3:0] conf_entropy_data_reg_enable_wd;
- logic [3:0] conf_boot_bypass_disable_qs;
- logic [3:0] conf_boot_bypass_disable_wd;
- logic [3:0] conf_health_test_clr_qs;
- logic [3:0] conf_health_test_clr_wd;
+ logic [3:0] conf_threshold_scope_qs;
+ logic [3:0] conf_threshold_scope_wd;
logic [3:0] conf_rng_bit_enable_qs;
logic [3:0] conf_rng_bit_enable_wd;
logic [1:0] conf_rng_bit_sel_qs;
@@ -309,7 +307,8 @@
logic debug_status_sha3_absorbed_qs;
logic debug_status_sha3_err_qs;
logic debug_status_main_sm_idle_qs;
- logic [7:0] debug_status_main_sm_state_qs;
+ logic debug_status_main_sm_boot_done_qs;
+ logic [8:0] debug_status_main_sm_state_qs;
logic recov_alert_sts_we;
logic recov_alert_sts_fips_enable_field_alert_qs;
logic recov_alert_sts_fips_enable_field_alert_wd;
@@ -317,10 +316,8 @@
logic recov_alert_sts_entropy_data_reg_en_field_alert_wd;
logic recov_alert_sts_module_enable_field_alert_qs;
logic recov_alert_sts_module_enable_field_alert_wd;
- logic recov_alert_sts_boot_bypass_disable_field_alert_qs;
- logic recov_alert_sts_boot_bypass_disable_field_alert_wd;
- logic recov_alert_sts_health_test_clr_field_alert_qs;
- logic recov_alert_sts_health_test_clr_field_alert_wd;
+ logic recov_alert_sts_threshold_scope_field_alert_qs;
+ logic recov_alert_sts_threshold_scope_field_alert_wd;
logic recov_alert_sts_rng_bit_enable_field_alert_qs;
logic recov_alert_sts_rng_bit_enable_field_alert_wd;
logic recov_alert_sts_fw_ov_mode_field_alert_qs;
@@ -812,18 +809,18 @@
.qs (conf_entropy_data_reg_enable_qs)
);
- // F[boot_bypass_disable]: 15:12
+ // F[threshold_scope]: 15:12
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h5)
- ) u_conf_boot_bypass_disable (
+ ) u_conf_threshold_scope (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (conf_we & regwen_qs),
- .wd (conf_boot_bypass_disable_wd),
+ .wd (conf_threshold_scope_wd),
// from internal hardware
.de (1'b0),
@@ -831,35 +828,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.conf.boot_bypass_disable.q),
+ .q (reg2hw.conf.threshold_scope.q),
// to register interface (read)
- .qs (conf_boot_bypass_disable_qs)
- );
-
- // F[health_test_clr]: 19:16
- prim_subreg #(
- .DW (4),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (4'h5)
- ) u_conf_health_test_clr (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we & regwen_qs),
- .wd (conf_health_test_clr_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.health_test_clr.q),
-
- // to register interface (read)
- .qs (conf_health_test_clr_qs)
+ .qs (conf_threshold_scope_qs)
);
// F[rng_bit_enable]: 23:20
@@ -2111,9 +2083,23 @@
.qs (debug_status_main_sm_idle_qs)
);
- // F[main_sm_state]: 31:24
+ // F[main_sm_boot_done]: 17:17
prim_subreg_ext #(
- .DW (8)
+ .DW (1)
+ ) u_debug_status_main_sm_boot_done (
+ .re (debug_status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.debug_status.main_sm_boot_done.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (debug_status_main_sm_boot_done_qs)
+ );
+
+ // F[main_sm_state]: 28:20
+ prim_subreg_ext #(
+ .DW (9)
) u_debug_status_main_sm_state (
.re (debug_status_re),
.we (1'b0),
@@ -2202,54 +2188,29 @@
.qs (recov_alert_sts_module_enable_field_alert_qs)
);
- // F[boot_bypass_disable_field_alert]: 3:3
+ // F[threshold_scope_field_alert]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
- ) u_recov_alert_sts_boot_bypass_disable_field_alert (
+ ) u_recov_alert_sts_threshold_scope_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
- .wd (recov_alert_sts_boot_bypass_disable_field_alert_wd),
+ .wd (recov_alert_sts_threshold_scope_field_alert_wd),
// from internal hardware
- .de (hw2reg.recov_alert_sts.boot_bypass_disable_field_alert.de),
- .d (hw2reg.recov_alert_sts.boot_bypass_disable_field_alert.d),
+ .de (hw2reg.recov_alert_sts.threshold_scope_field_alert.de),
+ .d (hw2reg.recov_alert_sts.threshold_scope_field_alert.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (recov_alert_sts_boot_bypass_disable_field_alert_qs)
- );
-
- // F[health_test_clr_field_alert]: 4:4
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessW0C),
- .RESVAL (1'h0)
- ) u_recov_alert_sts_health_test_clr_field_alert (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (recov_alert_sts_we),
- .wd (recov_alert_sts_health_test_clr_field_alert_wd),
-
- // from internal hardware
- .de (hw2reg.recov_alert_sts.health_test_clr_field_alert.de),
- .d (hw2reg.recov_alert_sts.health_test_clr_field_alert.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (recov_alert_sts_health_test_clr_field_alert_qs)
+ .qs (recov_alert_sts_threshold_scope_field_alert_qs)
);
// F[rng_bit_enable_field_alert]: 5:5
@@ -2869,9 +2830,7 @@
assign conf_entropy_data_reg_enable_wd = reg_wdata[7:4];
- assign conf_boot_bypass_disable_wd = reg_wdata[15:12];
-
- assign conf_health_test_clr_wd = reg_wdata[19:16];
+ assign conf_threshold_scope_wd = reg_wdata[15:12];
assign conf_rng_bit_enable_wd = reg_wdata[23:20];
@@ -2988,9 +2947,7 @@
assign recov_alert_sts_module_enable_field_alert_wd = reg_wdata[2];
- assign recov_alert_sts_boot_bypass_disable_field_alert_wd = reg_wdata[3];
-
- assign recov_alert_sts_health_test_clr_field_alert_wd = reg_wdata[4];
+ assign recov_alert_sts_threshold_scope_field_alert_wd = reg_wdata[3];
assign recov_alert_sts_rng_bit_enable_field_alert_wd = reg_wdata[5];
@@ -3066,8 +3023,7 @@
addr_hit[9]: begin
reg_rdata_next[3:0] = conf_fips_enable_qs;
reg_rdata_next[7:4] = conf_entropy_data_reg_enable_qs;
- reg_rdata_next[15:12] = conf_boot_bypass_disable_qs;
- reg_rdata_next[19:16] = conf_health_test_clr_qs;
+ reg_rdata_next[15:12] = conf_threshold_scope_qs;
reg_rdata_next[23:20] = conf_rng_bit_enable_qs;
reg_rdata_next[25:24] = conf_rng_bit_sel_qs;
end
@@ -3261,15 +3217,15 @@
reg_rdata_next[8] = debug_status_sha3_absorbed_qs;
reg_rdata_next[9] = debug_status_sha3_err_qs;
reg_rdata_next[16] = debug_status_main_sm_idle_qs;
- reg_rdata_next[31:24] = debug_status_main_sm_state_qs;
+ reg_rdata_next[17] = debug_status_main_sm_boot_done_qs;
+ reg_rdata_next[28:20] = debug_status_main_sm_state_qs;
end
addr_hit[49]: begin
reg_rdata_next[0] = recov_alert_sts_fips_enable_field_alert_qs;
reg_rdata_next[1] = recov_alert_sts_entropy_data_reg_en_field_alert_qs;
reg_rdata_next[2] = recov_alert_sts_module_enable_field_alert_qs;
- reg_rdata_next[3] = recov_alert_sts_boot_bypass_disable_field_alert_qs;
- reg_rdata_next[4] = recov_alert_sts_health_test_clr_field_alert_qs;
+ reg_rdata_next[3] = recov_alert_sts_threshold_scope_field_alert_qs;
reg_rdata_next[5] = recov_alert_sts_rng_bit_enable_field_alert_qs;
reg_rdata_next[8] = recov_alert_sts_fw_ov_mode_field_alert_qs;
reg_rdata_next[9] = recov_alert_sts_fw_ov_entropy_insert_field_alert_qs;
diff --git a/hw/top_englishbreakfast/util/sw_sources.patch b/hw/top_englishbreakfast/util/sw_sources.patch
index 2a93e3f..33232e0 100644
--- a/hw/top_englishbreakfast/util/sw_sources.patch
+++ b/hw/top_englishbreakfast/util/sw_sources.patch
@@ -63,7 +63,7 @@
-.L_ast_init_skip:
- // Enable entropy complex - this is not the full enable
- li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
-- li t0, 0x55505a
+- li t0, 0x555055
- sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
-
- li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
diff --git a/sw/device/lib/dif/dif_entropy_src.c b/sw/device/lib/dif/dif_entropy_src.c
index 0e2489c..3604f90 100644
--- a/sw/device/lib/dif/dif_entropy_src.c
+++ b/sw/device/lib/dif/dif_entropy_src.c
@@ -21,13 +21,7 @@
const dif_entropy_src_config_t *config) {
// TODO: Make this configurable at the API level.
uint32_t reg = bitfield_field32_write(
- 0, ENTROPY_SRC_CONF_BOOT_BYPASS_DISABLE_FIELD, kMultiBitBool4False);
-
- uint32_t health_clr_sel = config->reset_health_test_registers
- ? kMultiBitBool4True
- : kMultiBitBool4False;
- reg = bitfield_field32_write(reg, ENTROPY_SRC_CONF_HEALTH_TEST_CLR_FIELD,
- health_clr_sel);
+ 0, ENTROPY_SRC_CONF_THRESHOLD_SCOPE_FIELD, kMultiBitBool4False);
reg = bitfield_field32_write(
reg, ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_FIELD,
diff --git a/sw/device/lib/dif/dif_entropy_src_unittest.cc b/sw/device/lib/dif/dif_entropy_src_unittest.cc
index 14da700..1fd2947 100644
--- a/sw/device/lib/dif/dif_entropy_src_unittest.cc
+++ b/sw/device/lib/dif/dif_entropy_src_unittest.cc
@@ -109,17 +109,12 @@
uint32_t enable = test_param.expected_mode != kDifEntropySrcModeDisabled
? kMultiBitBool4True
: kMultiBitBool4False;
-
- uint32_t reset_ht = test_param.reset_health_test_registers
- ? kMultiBitBool4True
- : kMultiBitBool4False;
EXPECT_WRITE32(
ENTROPY_SRC_CONF_REG_OFFSET,
{
{ENTROPY_SRC_CONF_RNG_BIT_SEL_OFFSET, test_param.expected_rng_sel},
{ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET, rng_bit_enable},
- {ENTROPY_SRC_CONF_HEALTH_TEST_CLR_OFFSET, reset_ht},
- {ENTROPY_SRC_CONF_BOOT_BYPASS_DISABLE_OFFSET, kMultiBitBool4False},
+ {ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET, kMultiBitBool4False},
{ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET, route_to_fw},
{ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET, enable},
});
diff --git a/sw/device/lib/testing/test_rom/test_rom_start.S b/sw/device/lib/testing/test_rom/test_rom_start.S
index ab2fb7b..00bc722 100644
--- a/sw/device/lib/testing/test_rom/test_rom_start.S
+++ b/sw/device/lib/testing/test_rom/test_rom_start.S
@@ -164,7 +164,7 @@
.L_ast_init_skip:
// Enable entropy complex - this is not the full enable
li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
- li t0, 0x55505a
+ li t0, 0x555055
sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
diff --git a/sw/device/silicon_creator/mask_rom/mask_rom_start.S b/sw/device/silicon_creator/mask_rom/mask_rom_start.S
index fa4c552..02fcc02 100644
--- a/sw/device/silicon_creator/mask_rom/mask_rom_start.S
+++ b/sw/device/silicon_creator/mask_rom/mask_rom_start.S
@@ -202,8 +202,7 @@
// to prevent the release of FIPS entropy until all the thresholds are set
li t0, (0x5 << ENTROPY_SRC_CONF_FIPS_ENABLE_OFFSET) | \
(0x5 << ENTROPY_SRC_CONF_ENTROPY_DATA_REG_ENABLE_OFFSET) | \
- (0x5 << ENTROPY_SRC_CONF_BOOT_BYPASS_DISABLE_OFFSET) | \
- (0x5 << ENTROPY_SRC_CONF_HEALTH_TEST_CLR_OFFSET) | \
+ (0x5 << ENTROPY_SRC_CONF_THRESHOLD_SCOPE_OFFSET) | \
(0x5 << ENTROPY_SRC_CONF_RNG_BIT_ENABLE_OFFSET)
sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
diff --git a/sw/device/tests/entropy_src_smoketest.c b/sw/device/tests/entropy_src_smoketest.c
index 19aec03..0cedc1d 100644
--- a/sw/device/tests/entropy_src_smoketest.c
+++ b/sw/device/tests/entropy_src_smoketest.c
@@ -22,8 +22,8 @@
// Issue #10092 has been opened to discuss this.
const uint32_t kExpectedEntropyData[] = {
- 0xdaf90306, 0x466d674, 0x9691df54, 0xd2e3c93f, 0xdcbc993e, 0x64bfd173,
- 0xaba04e99, 0xf8ae1105, 0xd01dc17a, 0x608c5480, 0x373c5dcc, 0xc4e6cd55};
+ 0x38a9e15d, 0xc615d072, 0x15f21dc9, 0x38f06e56, 0x790a2a87, 0x8bff3d11,
+ 0xd56913da, 0x75dc72c3, 0xee2d38a2, 0xabfddaec, 0x3837e88b, 0x29cf1c12};
bool test_main() {
dif_entropy_src_t entropy_src;
