[csrng/rtl] added read internal state enable field
To be consistant with other enable functions, the internal state can only be read when this new enable field is set, and the efuse that enables sw register reads is set.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson
index 52d9106..85e8755 100644
--- a/hw/ip/csrng/data/csrng.hjson
+++ b/hw/ip/csrng/data/csrng.hjson
@@ -122,6 +122,16 @@
'''
resval: "0x5"
},
+ {
+ bits: "11:8",
+ name: "READ_INT_STATE",
+ desc: '''
+ Setting this field to 0xA will enable reading from the INT_STATE_VAL register.
+ Reading the internal state of the enable instances will be enabled
+ only if the efuse_sw_app_enable input is set.
+ '''
+ resval: "0x5"
+ },
]
},
{
diff --git a/hw/ip/csrng/doc/_index.md b/hw/ip/csrng/doc/_index.md
index b0d58a1..a16936e 100644
--- a/hw/ip/csrng/doc/_index.md
+++ b/hw/ip/csrng/doc/_index.md
@@ -142,8 +142,8 @@
Signal | Direction | Type | Description
-----------------------------|------------------|-----------------------------|---------------
-`otp_en_csrng_sw_app_read_i` | `input ` | `otp_en_t ` | An efuse that will enable firmware to access the NIST ctr_drbg internal state through registers.
-`lc_hw_debug_en_i` | `input` | `lc_tx_t ` | A life-cycle that will allow disabling of the AES encryption block, to be used for debug only.
+`otp_en_csrng_sw_app_read_i` | `input ` | `otp_en_t ` | An efuse that will enable firmware to access the NIST ctr_drbg internal state and genbits through registers.
+`lc_hw_debug_en_i` | `input` | `lc_tx_t ` | A life-cycle that will select which diversification value is used for xoring with the seed from ENTROPY_SRC.
`entropy_src_hw_if_o` | `output` | `entropy_src_hw_if_req_t` | Seed request made to the ENTROPY_SRC module.
`entropy_src_hw_if_i` | `input` | `entropy_src_hw_if_rsp_t` | Seed response from the ENTROPY_SRC module.
`cs_aes_halt_i` | `input` | `cs_aes_halt_req_t` | Request to CSRNG from ENTROPY_SRC to halt requests to the AES block for power leveling purposes.
diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv
index 48b76d2..e3e4c51 100644
--- a/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv
+++ b/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv
@@ -9,6 +9,7 @@
`uvm_object_new
task body();
+ ral.ctrl.read_int_state.set(4'hA);
// Wait for CSRNG cmd_rdy
csr_spinwait(.ptr(ral.sw_cmd_sts.cmd_rdy), .exp_data(1'b1));
diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv
index af006d7..58af24f 100644
--- a/hw/ip/csrng/rtl/csrng_core.sv
+++ b/hw/ip/csrng/rtl/csrng_core.sv
@@ -74,6 +74,7 @@
logic event_cs_fatal_err;
logic cs_enable;
logic sw_app_enable;
+ logic read_int_state;
logic acmd_avail;
logic acmd_sop;
logic acmd_mop;
@@ -308,6 +309,7 @@
logic [14:0] hw_exception_sts;
logic lc_hw_debug_on;
+ logic state_db_is_dump_en;
logic state_db_reg_rd_sel;
logic state_db_reg_rd_id_pulse;
logic [StateId-1:0] state_db_reg_rd_id;
@@ -655,6 +657,7 @@
// master module enable
assign cs_enable = (cs_enb_e'(reg2hw.ctrl.enable.q) == CS_FIELD_ON);
assign sw_app_enable = (cs_enb_e'(reg2hw.ctrl.sw_app_enable.q) == CS_FIELD_ON);
+ assign read_int_state = (cs_enb_e'(reg2hw.ctrl.read_int_state.q) == CS_FIELD_ON);
//------------------------------------------
// application interface
@@ -926,6 +929,7 @@
assign state_db_reg_rd_id = reg2hw.int_state_num.q;
assign state_db_reg_rd_id_pulse = reg2hw.int_state_num.qe;
assign hw2reg.int_state_val.d = state_db_reg_rd_val;
+ assign state_db_is_dump_en = cs_enable && read_int_state && efuse_sw_app_enable_i;
csrng_state_db #(
@@ -956,7 +960,7 @@
.state_db_wr_res_ctr_i(state_db_wr_rc),
.state_db_wr_sts_i(state_db_wr_sts),
- .state_db_is_dump_en_i(cs_enable), // TODO: add efuse and new config bit
+ .state_db_is_dump_en_i(state_db_is_dump_en),
.state_db_reg_rd_sel_i(state_db_reg_rd_sel),
.state_db_reg_rd_id_pulse_i(state_db_reg_rd_id_pulse),
.state_db_reg_rd_id_i(state_db_reg_rd_id),
diff --git a/hw/ip/csrng/rtl/csrng_reg_pkg.sv b/hw/ip/csrng/rtl/csrng_reg_pkg.sv
index 8e7d798..68c0621 100644
--- a/hw/ip/csrng/rtl/csrng_reg_pkg.sv
+++ b/hw/ip/csrng/rtl/csrng_reg_pkg.sv
@@ -77,6 +77,9 @@
struct packed {
logic [3:0] q;
} sw_app_enable;
+ struct packed {
+ logic [3:0] q;
+ } read_int_state;
} csrng_reg2hw_ctrl_reg_t;
typedef struct packed {
@@ -284,11 +287,11 @@
// Register -> HW type
typedef struct packed {
- csrng_reg2hw_intr_state_reg_t intr_state; // [137:134]
- csrng_reg2hw_intr_enable_reg_t intr_enable; // [133:130]
- csrng_reg2hw_intr_test_reg_t intr_test; // [129:122]
- csrng_reg2hw_alert_test_reg_t alert_test; // [121:120]
- csrng_reg2hw_ctrl_reg_t ctrl; // [119:112]
+ csrng_reg2hw_intr_state_reg_t intr_state; // [141:138]
+ csrng_reg2hw_intr_enable_reg_t intr_enable; // [137:134]
+ csrng_reg2hw_intr_test_reg_t intr_test; // [133:126]
+ csrng_reg2hw_alert_test_reg_t alert_test; // [125:124]
+ csrng_reg2hw_ctrl_reg_t ctrl; // [123:112]
csrng_reg2hw_cmd_req_reg_t cmd_req; // [111:79]
csrng_reg2hw_genbits_reg_t genbits; // [78:46]
csrng_reg2hw_int_state_num_reg_t int_state_num; // [45:41]
@@ -368,7 +371,7 @@
4'b 0001, // index[ 2] CSRNG_INTR_TEST
4'b 0001, // index[ 3] CSRNG_ALERT_TEST
4'b 0001, // index[ 4] CSRNG_REGWEN
- 4'b 0001, // index[ 5] CSRNG_CTRL
+ 4'b 0011, // index[ 5] CSRNG_CTRL
4'b 1111, // index[ 6] CSRNG_CMD_REQ
4'b 0001, // index[ 7] CSRNG_SW_CMD_STS
4'b 0001, // index[ 8] CSRNG_GENBITS_VLD
diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv
index 8f3c240..d68fe67 100644
--- a/hw/ip/csrng/rtl/csrng_reg_top.sv
+++ b/hw/ip/csrng/rtl/csrng_reg_top.sv
@@ -141,6 +141,8 @@
logic [3:0] ctrl_enable_wd;
logic [3:0] ctrl_sw_app_enable_qs;
logic [3:0] ctrl_sw_app_enable_wd;
+ logic [3:0] ctrl_read_int_state_qs;
+ logic [3:0] ctrl_read_int_state_wd;
logic cmd_req_we;
logic [31:0] cmd_req_wd;
logic sw_cmd_sts_cmd_rdy_qs;
@@ -565,6 +567,32 @@
);
+ // F[read_int_state]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SWACCESS("RW"),
+ .RESVAL (4'h5)
+ ) u_ctrl_read_int_state (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ctrl_we & regwen_qs),
+ .wd (ctrl_read_int_state_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ctrl.read_int_state.q),
+
+ // to register interface (read)
+ .qs (ctrl_read_int_state_qs)
+ );
+
+
// R[cmd_req]: V(False)
prim_subreg #(
@@ -1661,6 +1689,8 @@
assign ctrl_enable_wd = reg_wdata[3:0];
assign ctrl_sw_app_enable_wd = reg_wdata[7:4];
+
+ assign ctrl_read_int_state_wd = reg_wdata[11:8];
assign cmd_req_we = addr_hit[6] & reg_we & !reg_error;
assign cmd_req_wd = reg_wdata[31:0];
@@ -1716,6 +1746,7 @@
addr_hit[5]: begin
reg_rdata_next[3:0] = ctrl_enable_qs;
reg_rdata_next[7:4] = ctrl_sw_app_enable_qs;
+ reg_rdata_next[11:8] = ctrl_read_int_state_qs;
end
addr_hit[6]: begin
