[i2c, dv] Rename variables in v2 tests for consistency
Signed-off-by: Tung Hoang <hoang.tung@wdc.com>
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv
index db79a8e..803d6da 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv
@@ -9,9 +9,8 @@
`uvm_object_new
// counting the number of received overflow interrupts
- local uint num_fmt_overflow;
- local uint num_rx_overflow;
- rand uint num_data_rx_ovf;
+ local uint cnt_fmt_overflow;
+ local uint cnt_rx_overflow;
// send more one data than rx_fifo depth to trigger rx_overflow
constraint num_rd_bytes_c {
@@ -31,10 +30,10 @@
`DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_trans)
for (int i = 0; i < num_trans; i++) begin
- check_fmt_overflow = 1'b1; // set to gracefully stop check_fmt_overflow_intr
- check_rx_overflow = 1'b1; // set to gracefully stop check_rx_overflow_intr
- num_fmt_overflow = 0;
- num_rx_overflow = 0;
+ check_fmt_overflow = 1'b1; // set to gracefully stop process_fmt_overflow_intr
+ check_rx_overflow = 1'b1; // set to gracefully stop process_rx_overflow_intr
+ cnt_fmt_overflow = 0;
+ cnt_rx_overflow = 0;
fork
begin
@@ -47,12 +46,12 @@
host_send_trans(.num_trans(1), .trans_type(WriteOnly));
csr_spinwait(.ptr(ral.status.fmtempty), .exp_data(1'b1));
check_fmt_overflow = 1'b0;
- // number of fmt_overflow received is at most num_data_rx_ovf
- // since fmt_fifo can be drained thus decreasing num_fmt_overflow counter
- `DV_CHECK_GT(num_fmt_overflow, 0)
- `DV_CHECK_LE(num_fmt_overflow, num_data_ovf)
- `uvm_info(`gfn, $sformatf("\nRun %0d, num_fmt_overflow %0d",
- i, num_fmt_overflow), UVM_DEBUG)
+ // number of fmt_overflow received is at most num_data_ovf
+ // since fmt_fifo can be drained thus decreasing cnt_fmt_overflow counter
+ `DV_CHECK_GT(cnt_fmt_overflow, 0)
+ `DV_CHECK_LE(cnt_fmt_overflow, num_data_ovf)
+ `uvm_info(`gfn, $sformatf("\nRun %0d, cnt_fmt_overflow %0d",
+ i, cnt_fmt_overflow), UVM_DEBUG)
end
//*** verify rx_overflow irq:
@@ -64,39 +63,39 @@
host_send_trans(.num_trans(1), .trans_type(ReadOnly));
csr_spinwait(.ptr(ral.status.rxempty), .exp_data(1'b1));
check_rx_overflow = 1'b0;
- `DV_CHECK_EQ(num_rx_overflow, 1)
- `uvm_info(`gfn, $sformatf("\nRun %0d, num_rx_overflow %d",
- i, num_rx_overflow), UVM_DEBUG)
+ `DV_CHECK_EQ(cnt_rx_overflow, 1)
+ `uvm_info(`gfn, $sformatf("\nRun %0d, cnt_rx_overflow %d",
+ i, cnt_rx_overflow), UVM_DEBUG)
end
end
begin
- while (check_fmt_overflow) check_fmt_overflow_intr();
+ while (check_fmt_overflow) process_fmt_overflow_intr();
end
begin
- while (check_rx_overflow) check_rx_overflow_intr();
+ while (check_rx_overflow) process_rx_overflow_intr();
end
join
end
endtask : body
- task check_fmt_overflow_intr();
+ task process_fmt_overflow_intr();
bit fmt_overflow;
csr_rd(.ptr(ral.intr_state.fmt_overflow), .value(fmt_overflow));
if (fmt_overflow) begin
clear_interrupt(FmtOverflow);
- num_fmt_overflow++;
+ cnt_fmt_overflow++;
end
- endtask : check_fmt_overflow_intr
+ endtask : process_fmt_overflow_intr
- task check_rx_overflow_intr();
+ task process_rx_overflow_intr();
bit rx_overflow;
csr_rd(.ptr(ral.intr_state.rx_overflow), .value(rx_overflow));
if (rx_overflow) begin
clear_interrupt(RxOverflow);
- num_rx_overflow++;
+ cnt_rx_overflow++;
end
- endtask : check_rx_overflow_intr
+ endtask : process_rx_overflow_intr
endclass : i2c_fifo_overflow_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv
index 19c7d7a..65ab4e4 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv
@@ -9,8 +9,8 @@
`uvm_object_new
// counting the number of received watermark interrupts
- local uint num_fmt_watermark;
- local uint num_rx_watermark;
+ local uint cnt_fmt_watermark;
+ local uint cnt_rx_watermark;
// fast write data to fmt_fifo to quickly trigger fmt_watermark interrupt
constraint fmt_fifo_access_dly_c { fmt_fifo_access_dly == 0;}
@@ -39,8 +39,8 @@
for (int i = 0; i < num_trans; i++) begin
check_fmt_watermark = 1'b1;
check_rx_watermark = 1'b1;
- num_fmt_watermark = 0;
- num_rx_watermark = 0;
+ cnt_fmt_watermark = 0;
+ cnt_rx_watermark = 0;
fork
begin
@@ -51,15 +51,15 @@
if (check_fmt_watermark) begin
host_send_trans(.num_trans(1), .trans_type(WriteOnly));
csr_spinwait(.ptr(ral.status.fmtempty), .exp_data(1'b1));
- check_fmt_watermark = 1'b0; // gracefully stop check_fmt_watermark_intr
+ check_fmt_watermark = 1'b0; // gracefully stop process_fmt_watermark_intr
// depending the programmed fmtivl and the DUT configuration
- // (timing regsisters), num_fmt_watermark could be
+ // (timing regsisters), cnt_fmt_watermark could be
// 1: fmtilvl is crossed one when data drains from fmt_fifo
// 2: fmtilvl is crossed twice when data fills up or drains from fmt_fifo
- `DV_CHECK_GT(num_fmt_watermark, 0)
- `DV_CHECK_LE(num_fmt_watermark, 2)
- `uvm_info(`gfn, $sformatf("\nRun %0d, num_fmt_watermark %0d",
- i, num_fmt_watermark), UVM_DEBUG)
+ `DV_CHECK_GT(cnt_fmt_watermark, 0)
+ `DV_CHECK_LE(cnt_fmt_watermark, 2)
+ `uvm_info(`gfn, $sformatf("\nRun %0d, cnt_fmt_watermark %0d",
+ i, cnt_fmt_watermark), UVM_DEBUG)
end
//*** verify rx_watermark irq:
@@ -72,13 +72,13 @@
// until rx_fifo becomes full, en_rx_watermark is set to start reading rx_fifo
host_send_trans(.num_trans(1), .trans_type(ReadOnly));
csr_spinwait(.ptr(ral.status.rxempty), .exp_data(1'b1));
- check_rx_watermark = 1'b0; // gracefully stop check_rx_watermark_intr
- // for fmtilvl > 4, rx_watermark is disable (num_rx_watermark = 0)
- // otherwise, num_rx_watermark must be 1
+ check_rx_watermark = 1'b0; // gracefully stop process_rx_watermark_intr
+ // for fmtilvl > 4, rx_watermark is disable (cnt_rx_watermark = 0)
+ // otherwise, cnt_rx_watermark must be 1
if ( rxilvl <= 4) begin
- `DV_CHECK_EQ(num_rx_watermark, 1)
+ `DV_CHECK_EQ(cnt_rx_watermark, 1)
end else begin
- `DV_CHECK_EQ(num_rx_watermark, 0)
+ `DV_CHECK_EQ(cnt_rx_watermark, 0)
end
// during a read transaction, fmt_watermark could be triggered since read address
// and control byte are programmed to fmt_fifo and possibly cross fmtilvl
@@ -89,34 +89,34 @@
end
end
begin
- while (check_fmt_watermark) check_fmt_watermark_intr();
+ while (check_fmt_watermark) process_fmt_watermark_intr();
end
begin
- while (check_rx_watermark) check_rx_watermark_intr();
+ while (check_rx_watermark) process_rx_watermark_intr();
end
join
end
endtask : body
- task check_fmt_watermark_intr();
+ task process_fmt_watermark_intr();
bit fmt_watermark;
csr_rd(.ptr(ral.intr_state.fmt_watermark), .value(fmt_watermark));
if (fmt_watermark) begin
clear_interrupt(FmtWatermark);
- num_fmt_watermark++;
+ cnt_fmt_watermark++;
end
- endtask : check_fmt_watermark_intr
+ endtask : process_fmt_watermark_intr
- task check_rx_watermark_intr();
+ task process_rx_watermark_intr();
bit rx_watermark;
csr_rd(.ptr(ral.intr_state.rx_watermark), .value(rx_watermark));
if (rx_watermark) begin
clear_interrupt(RxWatermark);
- num_rx_watermark++;
+ cnt_rx_watermark++;
end
- endtask : check_rx_watermark_intr
+ endtask : process_rx_watermark_intr
endclass : i2c_fifo_watermark_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv
index 2243fc9..4ff3e2f 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv
@@ -29,7 +29,7 @@
// clear interrupt immediately
constraint clear_intr_dly_c { clear_intr_dly == 0; }
- // zero fifo access latency
+ // set latency to zero values for fatest access fmt_fifo and rx_fifo
constraint fmt_fifo_access_dly_c { fmt_fifo_access_dly == 0;}
constraint rx_fifo_access_dly_c { rx_fifo_access_dly == 0;}
