[top] Auto-generated files
There should be no RTL / DV changes.
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index f430319..a889a7b 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -141,112 +141,120 @@
]
}
resets:
- [
+ {
+ hier_paths:
{
- name: rst_ni
- gen: 0
- type: ext
+ top: rstmgr_resets.
+ ext: ""
}
- {
- name: por_aon
- gen: 0
- type: top
- root: rst_ni
- clk: aon
- }
- {
- name: lc_src
- gen: 0
- type: int
- root: por
- clk: io_div2
- }
- {
- name: sys_src
- gen: 0
- type: int
- root: por
- clk: io_div2
- }
- {
- name: por
- gen: 1
- type: top
- root: por_aon
- clk: main
- }
- {
- name: por_io
- gen: 1
- type: top
- root: por_aon
- clk: io
- }
- {
- name: por_io_div2
- gen: 1
- type: top
- root: por_aon
- clk: io_div2
- }
- {
- name: por_usb
- gen: 1
- type: top
- root: por_aon
- clk: usb
- }
- {
- name: lc
- gen: 1
- type: top
- domain: "0"
- root: lc_src
- clk: io_div2
- }
- {
- name: sys
- gen: 1
- type: top
- domain: "0"
- root: sys_src
- clk: main
- }
- {
- name: sys_io
- gen: 1
- type: top
- domain: "0"
- root: sys_src
- clk: io_div2
- }
- {
- name: sys_aon
- gen: 1
- type: top
- domain: "0"
- root: sys_src
- clk: aon
- }
- {
- name: spi_device
- gen: 1
- type: top
- domain: "0"
- root: sys_src
- clk: io_div2
- sw: 1
- }
- {
- name: usb
- gen: 1
- type: top
- domain: "0"
- root: sys_src
- clk: usb
- sw: 1
- }
- ]
+ nodes:
+ [
+ {
+ name: rst_ni
+ gen: false
+ type: ext
+ }
+ {
+ name: por_aon
+ gen: false
+ type: top
+ parent: rst_ni
+ clk: aon
+ }
+ {
+ name: lc_src
+ gen: false
+ type: int
+ parent: por
+ clk: io_div2
+ }
+ {
+ name: sys_src
+ gen: false
+ type: int
+ parent: por
+ clk: io_div2
+ }
+ {
+ name: por
+ gen: true
+ type: top
+ parent: por_aon
+ clk: main
+ }
+ {
+ name: por_io
+ gen: true
+ type: top
+ parent: por_aon
+ clk: io
+ }
+ {
+ name: por_io_div2
+ gen: true
+ type: top
+ parent: por_aon
+ clk: io_div2
+ }
+ {
+ name: por_usb
+ gen: true
+ type: top
+ parent: por_aon
+ clk: usb
+ }
+ {
+ name: lc
+ gen: true
+ type: top
+ domain: "0"
+ parent: lc_src
+ clk: io_div2
+ }
+ {
+ name: sys
+ gen: true
+ type: top
+ domain: "0"
+ parent: sys_src
+ clk: main
+ }
+ {
+ name: sys_io
+ gen: true
+ type: top
+ domain: "0"
+ parent: sys_src
+ clk: io_div2
+ }
+ {
+ name: sys_aon
+ gen: true
+ type: top
+ domain: "0"
+ parent: sys_src
+ clk: aon
+ }
+ {
+ name: spi_device
+ gen: true
+ type: top
+ domain: "0"
+ parent: sys_src
+ clk: io_div2
+ sw: 1
+ }
+ {
+ name: usb
+ gen: true
+ type: top
+ domain: "0"
+ parent: sys_src
+ clk: usb
+ sw: 1
+ }
+ ]
+ }
num_cores: "1"
module:
[
