| commit | 6913573c70e0bd2916c76294bb0229f38a8f9fac | [log] [tgz] |
|---|---|---|
| author | Miguel Osorio <miguelosorio@google.com> | Mon Oct 03 17:20:24 2022 -0700 |
| committer | moidx <migue48@gmail.com> | Sun Oct 09 13:19:22 2022 -0700 |
| tree | 6e60a96f06967548c5d83d0353d0c8df1cc9bbb5 | |
| parent | c2a8c64ccbca39707be7883dfd2f8c1100813730 [diff] |
[top-test] csrng_lc_hw_debug_en_test This commits adds a default OTP image for unlocked_test0 LC state, and implements the csrng_lc_hw_debug_en_test as a sim_dv target. There are additional changes made to the entropy_src firmware override interface to enable conditioner bypass mode. An additional test case will be added later to cover that functionality. Signed-off-by: Miguel Osorio <miguelosorio@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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