[regtool] Fail properly if something goes wrong
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/util/reggen/gen_cheader.py b/util/reggen/gen_cheader.py
index ffdc64b..87b2d8c 100644
--- a/util/reggen/gen_cheader.py
+++ b/util/reggen/gen_cheader.py
@@ -379,7 +379,7 @@
genout(outfile, '// End generated register defines for ' + component)
- return
+ return 0
def test_gen_define():
diff --git a/util/reggen/gen_dv.py b/util/reggen/gen_dv.py
index de74c0c..c44559f 100644
--- a/util/reggen/gen_dv.py
+++ b/util/reggen/gen_dv.py
@@ -60,9 +60,11 @@
SwWrAccess=SwWrAccess)
except: # noqa: E722
log.error(exceptions.text_error_template().render())
- sys.exit(1)
+ return 1
# Dump to output file
dest_path = '{}/{}_ral_pkg.sv'.format(outdir, block.name)
with open(dest_path, 'w') as fout:
fout.write(to_write)
+
+ return 0
diff --git a/util/reggen/gen_fpv.py b/util/reggen/gen_fpv.py
index ee43ced..d29c562 100644
--- a/util/reggen/gen_fpv.py
+++ b/util/reggen/gen_fpv.py
@@ -13,7 +13,6 @@
from pkg_resources import resource_filename
from .access import HwAccess, SwRdAccess, SwWrAccess
-from .data import *
from .gen_rtl import json_to_reg
@@ -46,5 +45,8 @@
HwAccess=HwAccess,
SwRdAccess=SwRdAccess,
SwWrAccess=SwWrAccess))
- except:
+ except: # noqa: 722
log.error(exceptions.text_error_template().render())
+ return 1
+
+ return 0
diff --git a/util/reggen/gen_html.py b/util/reggen/gen_html.py
index 5515255..0a53f1d 100644
--- a/util/reggen/gen_html.py
+++ b/util/reggen/gen_html.py
@@ -296,4 +296,4 @@
toclist, toclevel)
continue
- return
+ return 0
diff --git a/util/reggen/gen_json.py b/util/reggen/gen_json.py
index 86eb217..c593cc1 100644
--- a/util/reggen/gen_json.py
+++ b/util/reggen/gen_json.py
@@ -30,3 +30,5 @@
use_decimal=True)
else:
raise ValueError('Invalid JSON format ' + format)
+
+ return 0
diff --git a/util/reggen/gen_rtl.py b/util/reggen/gen_rtl.py
index 06faa49..ea546fc 100644
--- a/util/reggen/gen_rtl.py
+++ b/util/reggen/gen_rtl.py
@@ -180,8 +180,9 @@
HwAccess=HwAccess,
SwRdAccess=SwRdAccess,
SwWrAccess=SwWrAccess))
- except: # noqa: F722 for template Exception handling
+ except: # noqa F722 for template Exception handling
log.error(exceptions.text_error_template().render())
+ return 1
# Generate top.sv
with open(outdir + "/" + block.name + "_reg_top.sv", 'w',
@@ -192,5 +193,8 @@
HwAccess=HwAccess,
SwRdAccess=SwRdAccess,
SwWrAccess=SwWrAccess))
- except: # noqa: F722 for template Exception handling
+ except: # noqa F722 for template Exception handling
log.error(exceptions.text_error_template().render())
+ return 1
+
+ return 0
diff --git a/util/regtool.py b/util/regtool.py
index fc1c59c..7effbf0 100755
--- a/util/regtool.py
+++ b/util/regtool.py
@@ -192,14 +192,11 @@
validate.validate(obj, params=params)
if format == 'rtl':
- gen_rtl.gen_rtl(obj, outdir)
- return 0
+ return gen_rtl.gen_rtl(obj, outdir)
if format == 'dv':
- gen_dv.gen_dv(obj, args.dv_base_prefix, outdir)
- return 0
+ return gen_dv.gen_dv(obj, args.dv_base_prefix, outdir)
if format == 'fpv':
- gen_fpv.gen_fpv(obj, outdir)
- return 0
+ return gen_fpv.gen_fpv(obj, outdir)
src_lic = None
src_copy = ''
found_spdx = None
@@ -224,16 +221,16 @@
with outfile:
if format == 'html':
- gen_html.gen_html(obj, outfile)
+ return gen_html.gen_html(obj, outfile)
elif format == 'cdh':
- gen_cheader.gen_cdefines(obj, outfile, src_lic, src_copy)
+ return gen_cheader.gen_cdefines(obj, outfile, src_lic, src_copy)
elif format == 'cth':
- gen_ctheader.gen_cdefines(obj, outfile, src_lic, src_copy)
+ return gen_ctheader.gen_cdefines(obj, outfile, src_lic, src_copy)
else:
- gen_json.gen_json(obj, outfile, format)
+ return gen_json.gen_json(obj, outfile, format)
outfile.write('\n')
if __name__ == '__main__':
- main()
+ sys.exit(main())
