Added missing include prim_assert.sv
Signed-off-by: Dawid Zimonczyk <dawidz@aldec.com.pl>
diff --git a/hw/ip/prim/rtl/prim_gate_gen.sv b/hw/ip/prim/rtl/prim_gate_gen.sv
index e97c7d5..bb7bde2 100644
--- a/hw/ip/prim/rtl/prim_gate_gen.sv
+++ b/hw/ip/prim/rtl/prim_gate_gen.sv
@@ -45,7 +45,7 @@
// Note that the generator is not very accurate for smaller gate counts due
// to the generate loop granularity. Hence, do not use for fever than 500 GE.
-
+`include "prim_assert.sv"
module prim_gate_gen #(
parameter int DataWidth = 32,
parameter int NumGates = 1000
diff --git a/hw/ip/prim/rtl/prim_keccak.sv b/hw/ip/prim/rtl/prim_keccak.sv
index 7c3a526..d247078 100644
--- a/hw/ip/prim/rtl/prim_keccak.sv
+++ b/hw/ip/prim/rtl/prim_keccak.sv
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
//
// prim_keccak is single round permutation module
-
+`include "prim_assert.sv"
module prim_keccak #(
parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600}
diff --git a/hw/ip/prim/rtl/prim_present.sv b/hw/ip/prim/rtl/prim_present.sv
index bf3321c..6727914 100644
--- a/hw/ip/prim/rtl/prim_present.sv
+++ b/hw/ip/prim/rtl/prim_present.sv
@@ -22,7 +22,7 @@
// TODO: this module has not been verified yet, and has only been used in
// synthesis experiments.
-
+`include "prim_assert.sv"
module prim_present #(
parameter int DataWidth = 64, // {32, 64}
parameter int KeyWidth = 128, // {64, 80, 128}
diff --git a/hw/ip/prim/rtl/prim_prince.sv b/hw/ip/prim/rtl/prim_prince.sv
index 655835f..423a7ca 100644
--- a/hw/ip/prim/rtl/prim_prince.sv
+++ b/hw/ip/prim/rtl/prim_prince.sv
@@ -24,7 +24,7 @@
// TODO: this module has not been verified yet, and has only been used in
// synthesis experiments.
-
+`include "prim_assert.sv"
module prim_prince #(
parameter int DataWidth = 64,
parameter int KeyWidth = 128,
diff --git a/hw/ip/prim_generic/prim_generic_ram_2p.core b/hw/ip/prim_generic/prim_generic_ram_2p.core
index 196a9b9..0db36d5 100644
--- a/hw/ip/prim_generic/prim_generic_ram_2p.core
+++ b/hw/ip/prim_generic/prim_generic_ram_2p.core
@@ -8,6 +8,7 @@
filesets:
files_rtl:
depend:
+ - lowrisc:prim:assert
- lowrisc:prim:util_memload
files:
- rtl/prim_generic_ram_2p.sv
diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv
index de017d9..4277d32 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_ram_2p.sv
@@ -5,7 +5,7 @@
// Synchronous dual-port SRAM register model
// This module is for simulation and small size SRAM.
// Implementing ECC should be done inside wrapper not this model.
-
+`include "prim_assert.sv"
module prim_generic_ram_2p #(
parameter int Width = 32, // bit
parameter int Depth = 128,
