[hmac] Remove irrelevant TODOs
Remove irrelevant TODOs from RTL. Some TODOs are still remained and need
discussions.
This is related to #761
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index 32c1ae4..df3b10b 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -180,7 +180,6 @@
// Instances //
///////////////
- // TODO: Revise logic to assert rvalid only after grant asserted.
assign msg_fifo_rvalid = msg_fifo_req & ~msg_fifo_we;
assign msg_fifo_rdata = '1; // Return all F
assign msg_fifo_rerror = '1; // Return error for read access
diff --git a/hw/ip/hmac/rtl/hmac_core.sv b/hw/ip/hmac/rtl/hmac_core.sv
index 3183cfe..e1693f2 100644
--- a/hw/ip/hmac/rtl/hmac_core.sv
+++ b/hw/ip/hmac/rtl/hmac_core.sv
@@ -118,8 +118,6 @@
(sel_rdata == SelFifo) ? fifo_rdata :
'{default: '0};
- // TODO: Block size and hash size can differ based on the hash algorithm.
- // Shall this be flexible or HMAC sticks to SHA256 always?
assign sha_message_length = (!hmac_en) ? message_length :
(sel_msglen == SelIPadMsg) ? message_length + BlockSize :
(sel_msglen == SelOPadMsg) ? BlockSize + 256 :
@@ -258,7 +256,6 @@
end
StPushToMsgFifo: begin
- // TODO: Accelerate by parallel process of PushToMsgFifo and OPad hash
hmac_sha_rvalid = 1'b0;
fifo_wsel = 1'b1;
fifo_wvalid = 1'b1;
diff --git a/hw/ip/hmac/rtl/sha2.sv b/hw/ip/hmac/rtl/sha2.sv
index f9ae439..5dd529f 100644
--- a/hw/ip/hmac/rtl/sha2.sv
+++ b/hw/ip/hmac/rtl/sha2.sv
@@ -4,8 +4,6 @@
//
// SHA-256 algorithm
//
-// TODO: Consider the input data isn't big endian (should be outside of this module)
-// TODO: Support SHA-224 as it is almost same as SHA-256
module sha2 import hmac_pkg::*; (
input clk_i,
@@ -24,7 +22,6 @@
input hash_start,
input hash_process,
output logic hash_done,
- // TODO: random pause
input [63:0] message_length, // bits but byte based
output sha_word_t [7:0] digest
@@ -55,8 +52,6 @@
if (!rst_ni) begin
w <= '0;
end else if (wipe_secret) begin
- // TODO: Determine fill with wipe_v? or XOR?
- // both can be detected if `wipe_v` can be probed
w <= w ^ {16{wipe_v}};
end else if (!sha_en) begin
w <= '0;
@@ -70,7 +65,7 @@
// // to fill the register if available. If FIFO goes to empty, w_index doesn't increase
// // and it cannot reach 15. Then the sha engine doesn't start, which introduces latency.
// //
- // // TODO: But in this case, still w should be shifted to feed SHA compress engine. Then
+ // // But in this case, still w should be shifted to feed SHA compress engine. Then
// // fifo_rdata should be inserted in the middle of w index.
// // w[64-round + w_index] <= fifo_rdata;
// for (int i = 0 ; i < 16 ; i++) begin
@@ -206,15 +201,10 @@
FifoWait: begin
// Wait until next fetch begins (begin at round == 48)a
- // TODO: Detect at the end of the message
if (msg_feed_complete && complete_one_chunk) begin
- // TODO: Should we wait until round hits 63?
fifo_st_d = FifoIdle;
hash_done_next = 1'b1;
- // TODO: make below FIFO feeding logic concrete.
- // currently, with below commented logic, it doesn't fill FIFO correctly.
- //end else if (!in_end_chunk && round == 6'd47) begin
end else if (complete_one_chunk) begin
fifo_st_d = FifoLoadFromFifo;
end else begin
diff --git a/hw/ip/hmac/rtl/sha2_pad.sv b/hw/ip/hmac/rtl/sha2_pad.sv
index a7f70f9..79d12c9 100644
--- a/hw/ip/hmac/rtl/sha2_pad.sv
+++ b/hw/ip/hmac/rtl/sha2_pad.sv
@@ -31,8 +31,6 @@
output logic msg_feed_complete // Indicates, all message is feeded
);
- // TODO: Thorough scenario for sha_en turn off in the middle of the ops.
-
//logic [8:0] length_added;
logic [63:0] tx_count; // fin received data count.
@@ -142,7 +140,6 @@
end
// Next state
- // TODO: Error handling (shaf_rready with shaf_rvalid == 1)
always_comb begin
shaf_rvalid = 1'b0;
inc_txcount = 1'b0;
