| commit | 62bdf5b03f43ce08935c737deadc3e0f4034eb88 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Aug 24 14:01:42 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue Aug 31 17:29:16 2021 +0100 |
| tree | 88bf4e99f0258803946524a121e7878be759e084 | |
| parent | 2ae83d90a289c8d159466bc693a96c341ae9913b [diff] |
[otbn,dv] Add loop warping support to otbn_top_sim This is the testbench that we use for Verilator simulations. Since Verilator doesn't support the SystemVerilog "force" statement, we call back to C++ and update the signals manually there. To do this, we install a DPI hook on each negedge: this would probably be very inefficient in some simulators, but the "context switch" shouldn't be a big deal in Verilator. One slight difficulty is that the RTL doesn't count "loop K of N". Instead, it counts down from N. That's (obviously) more efficient, but doesn't really match the intuitive way to count loop iterations, so we want to convert between it and the "K of N" scheme. To do so, you need "N", but the RTL doesn't store that value (since it doesn't need it), so we have some extra tracking code that tracks the stack of initial loop counts. Obviously, adding this sort of invasive test code might be worrying: what happens if it goes wrong?! But the result of something coming unstuck here will be spuriously failing tests, not that we miss a bug in the design, so I'm not too worried about it. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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