| commit | 597283e3f6ba66294e0d486bd5eeccb5ab3b7630 | [log] [tgz] |
|---|---|---|
| author | Guillermo Maturana <maturana@google.com> | Tue Feb 22 19:02:29 2022 -0800 |
| committer | Matute <maturana@google.com> | Tue Mar 01 11:57:25 2022 -0800 |
| tree | f85dcfec6100cc968cb65375a61aebaf7a7c79d5 | |
| parent | 0c221f50eed440bec102a7c6ba69e3f4a5d168ad [diff] |
[dv,full_chip,clkmgr] Test access to disabled peripheral Configure a watchdog bite. Disable the clock to some peripheral and perform a CSR access to it. The access should cause the CPU to freeze, so the watchdog will bite. Detect if a reset is due to the watchdog, indicating test success. Introduce a simple aon_timer testutils function. Minor cleanup of aon_timer_irq_test. Minor updates to the full chip testplan. Signed-off-by: Guillermo Maturana <maturana@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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