[top] Add multiple clocks at the top.
Also add multiple resets sync'ed to each clock. The multi-clock
and resets are still connected to the same source, a separate PR will
bring true clock and reset sources.
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 2eb89e0..a803c59 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -15,6 +15,10 @@
name: main
freq: "100000000"
}
+ {
+ name: fixed
+ freq: "100000000"
+ }
]
resets:
[
@@ -29,10 +33,16 @@
clk: main
}
{
+ name: sys_fixed
+ type: leaf
+ root: sys
+ clk: fixed
+ }
+ {
name: spi_device
type: leaf
root: sys
- clk: main
+ clk: fixed
}
]
num_cores: "1"
@@ -43,11 +53,11 @@
type: uart
clock_connections:
{
- clk_i: main
+ clk_i: fixed
}
reset_connections:
{
- rst_ni: sys
+ rst_ni: sys_fixed
}
base_addr: 0x40000000
size: 0x1000
@@ -121,11 +131,11 @@
type: gpio
clock_connections:
{
- clk_i: main
+ clk_i: fixed
}
reset_connections:
{
- rst_ni: sys
+ rst_ni: sys_fixed
}
base_addr: 0x40010000
size: 0x1000
@@ -157,7 +167,7 @@
type: spi_device
clock_connections:
{
- clk_i: main
+ clk_i: fixed
}
reset_connections:
{
@@ -289,11 +299,11 @@
type: rv_timer
clock_connections:
{
- clk_i: main
+ clk_i: fixed
}
reset_connections:
{
- rst_ni: sys
+ rst_ni: sys_fixed
}
base_addr: 0x40080000
size: 0x1000
@@ -577,11 +587,13 @@
clock_connections:
{
clk_main_i: main
+ clk_fixed_i: fixed
}
- reset: sys
+ reset: rst_main_ni
reset_connections:
{
rst_main_ni: sys
+ rst_fixed_ni: sys_fixed
}
connections:
{
@@ -633,7 +645,8 @@
{
name: corei
type: host
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: rv_core_ibex
pipeline_byp: "true"
@@ -641,7 +654,8 @@
{
name: cored
type: host
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: rv_core_ibex
pipeline_byp: "true"
@@ -649,7 +663,8 @@
{
name: dm_sba
type: host
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
pipeline: "true"
@@ -657,7 +672,8 @@
{
name: rom
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: rom
base_addr: 0x00008000
@@ -667,7 +683,8 @@
{
name: debug_mem
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
base_addr: 0x1A110000
@@ -677,7 +694,8 @@
{
name: ram_main
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: ram_1p
base_addr: 0x10000000
@@ -687,7 +705,8 @@
{
name: eflash
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: eflash
base_addr: 0x20000000
@@ -697,7 +716,8 @@
{
name: uart
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: uart
base_addr: 0x40000000
@@ -707,7 +727,8 @@
{
name: gpio
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: gpio
base_addr: 0x40010000
@@ -717,7 +738,8 @@
{
name: spi_device
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: spi_device
base_addr: 0x40020000
@@ -727,7 +749,8 @@
{
name: flash_ctrl
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: flash_ctrl
base_addr: 0x40030000
@@ -737,7 +760,8 @@
{
name: rv_timer
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: rv_timer
base_addr: 0x40080000
@@ -747,7 +771,8 @@
{
name: hmac
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: hmac
base_addr: 0x40120000
@@ -757,7 +782,8 @@
{
name: aes
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: aes
base_addr: 0x40110000
@@ -767,7 +793,8 @@
{
name: rv_plic
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
inst_type: rv_plic
base_addr: 0x40090000
size_byte: 0x1000
@@ -777,7 +804,8 @@
{
name: pinmux
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_fixed_ni
inst_type: pinmux
base_addr: 0x40070000
size_byte: 0x1000
@@ -787,7 +815,7 @@
{
name: alert_handler
type: device
- clock: main
+ clock: clk_main_i
inst_type: alert_handler
pipeline_byp: "false"
base_addr: 0x40130000
@@ -797,7 +825,7 @@
{
name: nmi_gen
type: device
- clock: main
+ clock: clk_main_i
inst_type: nmi_gen
pipeline_byp: "false"
base_addr: 0x40140000
@@ -805,7 +833,7 @@
pipeline: "true"
}
]
- clock: main
+ clock: clk_main_i
}
]
interrupt_module:
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 326236b..f3c41d7 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -10,6 +10,7 @@
clocks: [
{ name: "main", freq: "100000000" }
+ { name: "fixed", freq: "100000000" }
]
// Reset attributes
@@ -20,7 +21,8 @@
resets: [
{ name: "lc", type: "root", clk: "main"}
{ name: "sys", type: "root", clk: "main"}
- { name: "spi_device", type: "leaf", root: "sys", clk: "main"}
+ { name: "sys_fixed", type: "leaf", root: "sys", clk: "fixed"}
+ { name: "spi_device", type: "leaf", root: "sys", clk: "fixed"}
]
// Number of cores: used in rv_plic and timer
@@ -37,25 +39,25 @@
// clock connections defines the port to top level clock connection
// the ip.hjson will declare the clock port names
// If none are defined at ip.hjson, clk_i is used by default
- clock_connections: {clk_i: "main"},
+ clock_connections: {clk_i: "fixed"},
// reset connections defines the port to top level reset connection
// the ip.hjson will declare the reset port names
// If none are defined at ip.hjson, rst_ni is used by default
- reset_connections: {rst_ni: "sys"},
+ reset_connections: {rst_ni: "sys_fixed"},
base_addr: "0x40000000",
},
{ name: "gpio",
type: "gpio",
- clock_connections: {clk_i: "main"},
- reset_connections: {rst_ni: "sys"},
+ clock_connections: {clk_i: "fixed"},
+ reset_connections: {rst_ni: "sys_fixed"},
base_addr: "0x40010000",
}
{ name: "spi_device",
type: "spi_device",
- clock_connections: {clk_i: "main"},
+ clock_connections: {clk_i: "fixed"},
reset_connections: {rst_ni: "spi_device"},
base_addr: "0x40020000",
},
@@ -67,8 +69,8 @@
},
{ name: "rv_timer",
type: "rv_timer",
- clock_connections: {clk_i: "main"},
- reset_connections: {rst_ni: "sys"},
+ clock_connections: {clk_i: "fixed"},
+ reset_connections: {rst_ni: "sys_fixed"},
base_addr: "0x40080000",
},
{ name: "aes",
@@ -151,9 +153,9 @@
// Assume xbar.hjson is located in the same directory of top.hjson
xbar: [
{ name: "main",
- clock_connections: {clk_main_i: "main"},
+ clock_connections: {clk_main_i: "main", clk_fixed_i: "fixed"},
reset: "sys",
- reset_connections: {rst_main_ni: "sys"}
+ reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_fixed"}
},
],
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson
index 1eff346..e95d0b0 100644
--- a/hw/top_earlgrey/data/xbar_main.hjson
+++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -1,89 +1,102 @@
{ name: "main",
type: "xbar",
- clock: "main",
clock_primary: "clk_main_i", // Main clock, used in sockets
+ other_clock_list: [ "clk_fixed_i" ] // Secondary clocks used by specific nodes
reset_primary: "rst_main_ni", // Main reset, used in sockets
+ other_reset_list: [ "rst_fixed_ni" ] // Secondary clocks used by specific nodes
nodes: [
{ name: "corei",
type: "host",
- clock: "main",
-
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline: "false"
},
{ name: "cored",
type: "host",
- clock: "main",
-
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline: "false"
},
{ name: "dm_sba", // DM
type: "host",
- clock: "main",
-
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline_byp: "false"
},
{ name: "rom",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline: "false",
},
{ name: "debug_mem",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline_byp: "false"
},
{ name: "ram_main",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline: "false",
},
{ name: "eflash",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline: "false",
},
{ name: "uart",
type: "device",
- clock: "main",
+ clock: "clk_fixed_i",
+ reset: "rst_fixed_ni",
pipeline_byp: "false"
},
{ name: "gpio",
type: "device",
- clock: "main",
+ clock: "clk_fixed_i",
+ reset: "rst_fixed_ni",
pipeline_byp: "false"
},
{ name: "spi_device",
type: "device",
- clock: "main",
+ clock: "clk_fixed_i",
+ reset: "rst_fixed_ni",
pipeline_byp: "false"
},
{ name: "flash_ctrl",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline_byp: "false"
},
{ name: "rv_timer",
type: "device",
- clock: "main",
+ clock: "clk_fixed_i",
+ reset: "rst_fixed_ni",
pipeline_byp: "false"
},
{ name: "hmac",
type: "device",
- clock: "main"
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
pipeline_byp: "false"
},
{ name: "aes",
type: "device",
- clock: "main"
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
pipeline_byp: "false"
},
{ name: "rv_plic",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_main_ni",
inst_type: "rv_plic",
base_addr: "0x40090000",
size_byte: "0x1000",
@@ -91,7 +104,8 @@
},
{ name: "pinmux",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
+ reset: "rst_fixed_ni",
inst_type: "pinmux",
base_addr: "0x40070000",
size_byte: "0x1000",
@@ -99,7 +113,7 @@
},
{ name: "alert_handler",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
inst_type: "alert_handler",
pipeline_byp: "false"
},
@@ -107,7 +121,7 @@
// and test them by converting them into IRQs
{ name: "nmi_gen",
type: "device",
- clock: "main",
+ clock: "clk_main_i",
inst_type: "nmi_gen",
pipeline_byp: "false"
}
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index c9390e9..ed3bdd9 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -12,7 +12,7 @@
//
# ALERT_HANDLER register template
#
-# Parameter (given by python tool)
+# Parameter (given by Python tool)
# - n_alerts: Number of alert sources
# - esc_cnt_dw: Width of escalation counter
# - accu_cnt_dw: Width of accumulator
diff --git a/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson
index e377830..bdff50c 100644
--- a/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar/data/autogen/xbar_main.gen.hjson
@@ -11,11 +11,13 @@
clock_connections:
{
clk_main_i: main
+ clk_fixed_i: fixed
}
- reset: sys
+ reset: rst_main_ni
reset_connections:
{
rst_main_ni: sys
+ rst_fixed_ni: sys_fixed
}
connections:
{
@@ -67,7 +69,8 @@
{
name: corei
type: host
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: rv_core_ibex
pipeline_byp: "true"
@@ -75,7 +78,8 @@
{
name: cored
type: host
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: rv_core_ibex
pipeline_byp: "true"
@@ -83,7 +87,8 @@
{
name: dm_sba
type: host
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
pipeline: "true"
@@ -91,7 +96,8 @@
{
name: rom
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: rom
base_addr: 0x00008000
@@ -101,7 +107,8 @@
{
name: debug_mem
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
base_addr: 0x1A110000
@@ -111,7 +118,8 @@
{
name: ram_main
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: ram_1p
base_addr: 0x10000000
@@ -121,7 +129,8 @@
{
name: eflash
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline: "false"
inst_type: eflash
base_addr: 0x20000000
@@ -131,7 +140,8 @@
{
name: uart
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: uart
base_addr: 0x40000000
@@ -141,7 +151,8 @@
{
name: gpio
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: gpio
base_addr: 0x40010000
@@ -151,7 +162,8 @@
{
name: spi_device
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: spi_device
base_addr: 0x40020000
@@ -161,7 +173,8 @@
{
name: flash_ctrl
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: flash_ctrl
base_addr: 0x40030000
@@ -171,7 +184,8 @@
{
name: rv_timer
type: device
- clock: main
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
pipeline_byp: "false"
inst_type: rv_timer
base_addr: 0x40080000
@@ -181,7 +195,8 @@
{
name: hmac
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: hmac
base_addr: 0x40120000
@@ -191,7 +206,8 @@
{
name: aes
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
pipeline_byp: "false"
inst_type: aes
base_addr: 0x40110000
@@ -201,7 +217,8 @@
{
name: rv_plic
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_main_ni
inst_type: rv_plic
base_addr: 0x40090000
size_byte: 0x1000
@@ -211,7 +228,8 @@
{
name: pinmux
type: device
- clock: main
+ clock: clk_main_i
+ reset: rst_fixed_ni
inst_type: pinmux
base_addr: 0x40070000
size_byte: 0x1000
@@ -221,7 +239,7 @@
{
name: alert_handler
type: device
- clock: main
+ clock: clk_main_i
inst_type: alert_handler
pipeline_byp: "false"
base_addr: 0x40130000
@@ -231,7 +249,7 @@
{
name: nmi_gen
type: device
- clock: main
+ clock: clk_main_i
inst_type: nmi_gen
pipeline_byp: "false"
base_addr: 0x40140000
@@ -239,6 +257,6 @@
pipeline: "true"
}
]
- clock: main
+ clock: clk_main_i
type: xbar
}
\ No newline at end of file
diff --git a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
index 913f600..01cc9bf 100644
--- a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
+++ b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
@@ -51,20 +51,20 @@
.d2h (tl_eflash_i)
);
bind xbar_main tlul_assert tlul_assert_device_uart (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
+ .clk_i (clk_fixed_i),
+ .rst_ni (rst_fixed_ni),
.h2d (tl_uart_o),
.d2h (tl_uart_i)
);
bind xbar_main tlul_assert tlul_assert_device_gpio (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
+ .clk_i (clk_fixed_i),
+ .rst_ni (rst_fixed_ni),
.h2d (tl_gpio_o),
.d2h (tl_gpio_i)
);
bind xbar_main tlul_assert tlul_assert_device_spi_device (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
+ .clk_i (clk_fixed_i),
+ .rst_ni (rst_fixed_ni),
.h2d (tl_spi_device_o),
.d2h (tl_spi_device_i)
);
@@ -75,8 +75,8 @@
.d2h (tl_flash_ctrl_i)
);
bind xbar_main tlul_assert tlul_assert_device_rv_timer (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
+ .clk_i (clk_fixed_i),
+ .rst_ni (rst_fixed_ni),
.h2d (tl_rv_timer_o),
.d2h (tl_rv_timer_i)
);
@@ -100,7 +100,7 @@
);
bind xbar_main tlul_assert tlul_assert_device_pinmux (
.clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
+ .rst_ni (rst_fixed_ni),
.h2d (tl_pinmux_o),
.d2h (tl_pinmux_i)
);
@@ -118,5 +118,3 @@
);
endmodule
-
-
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
index 2d3d421..bc02862 100644
--- a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
@@ -26,62 +26,72 @@
// -> ram_main
// -> sm1_22
// -> eflash
-// -> sm1_24
-// -> uart
// -> sm1_25
-// -> gpio
-// -> sm1_26
-// -> spi_device
+// -> asf_24
+// -> uart
// -> sm1_27
-// -> flash_ctrl
-// -> sm1_28
-// -> rv_timer
+// -> asf_26
+// -> gpio
// -> sm1_29
-// -> aes
+// -> asf_28
+// -> spi_device
// -> sm1_30
-// -> hmac
-// -> sm1_31
-// -> rv_plic
+// -> flash_ctrl
// -> sm1_32
-// -> pinmux
+// -> asf_31
+// -> rv_timer
// -> sm1_33
-// -> alert_handler
+// -> aes
// -> sm1_34
+// -> hmac
+// -> sm1_35
+// -> rv_plic
+// -> sm1_36
+// -> pinmux
+// -> sm1_37
+// -> alert_handler
+// -> sm1_38
// -> nmi_gen
// dm_sba
-// -> s1n_35
+// -> s1n_39
// -> sm1_19
// -> rom
// -> sm1_21
// -> ram_main
// -> sm1_22
// -> eflash
-// -> sm1_24
-// -> uart
// -> sm1_25
-// -> gpio
-// -> sm1_26
-// -> spi_device
+// -> asf_24
+// -> uart
// -> sm1_27
-// -> flash_ctrl
-// -> sm1_28
-// -> rv_timer
+// -> asf_26
+// -> gpio
// -> sm1_29
-// -> aes
+// -> asf_28
+// -> spi_device
// -> sm1_30
-// -> hmac
-// -> sm1_31
-// -> rv_plic
+// -> flash_ctrl
// -> sm1_32
-// -> pinmux
+// -> asf_31
+// -> rv_timer
// -> sm1_33
-// -> alert_handler
+// -> aes
// -> sm1_34
+// -> hmac
+// -> sm1_35
+// -> rv_plic
+// -> sm1_36
+// -> pinmux
+// -> sm1_37
+// -> alert_handler
+// -> sm1_38
// -> nmi_gen
module xbar_main (
input clk_main_i,
+ input clk_fixed_i,
input rst_main_ni,
+ input rst_fixed_ni,
// Host interfaces
input tlul_pkg::tl_h2d_t tl_corei_i,
@@ -182,12 +192,10 @@
// Create steering signal
logic [3:0] dev_sel_s1n_23;
-
- tl_h2d_t tl_sm1_24_us_h2d [2];
- tl_d2h_t tl_sm1_24_us_d2h [2];
-
- tl_h2d_t tl_sm1_24_ds_h2d ;
- tl_d2h_t tl_sm1_24_ds_d2h ;
+ tl_h2d_t tl_asf_24_us_h2d ;
+ tl_d2h_t tl_asf_24_us_d2h ;
+ tl_h2d_t tl_asf_24_ds_h2d ;
+ tl_d2h_t tl_asf_24_ds_d2h ;
tl_h2d_t tl_sm1_25_us_h2d [2];
@@ -196,12 +204,10 @@
tl_h2d_t tl_sm1_25_ds_h2d ;
tl_d2h_t tl_sm1_25_ds_d2h ;
-
- tl_h2d_t tl_sm1_26_us_h2d [2];
- tl_d2h_t tl_sm1_26_us_d2h [2];
-
- tl_h2d_t tl_sm1_26_ds_h2d ;
- tl_d2h_t tl_sm1_26_ds_d2h ;
+ tl_h2d_t tl_asf_26_us_h2d ;
+ tl_d2h_t tl_asf_26_us_d2h ;
+ tl_h2d_t tl_asf_26_ds_h2d ;
+ tl_d2h_t tl_asf_26_ds_d2h ;
tl_h2d_t tl_sm1_27_us_h2d [2];
@@ -210,12 +216,10 @@
tl_h2d_t tl_sm1_27_ds_h2d ;
tl_d2h_t tl_sm1_27_ds_d2h ;
-
- tl_h2d_t tl_sm1_28_us_h2d [2];
- tl_d2h_t tl_sm1_28_us_d2h [2];
-
- tl_h2d_t tl_sm1_28_ds_h2d ;
- tl_d2h_t tl_sm1_28_ds_d2h ;
+ tl_h2d_t tl_asf_28_us_h2d ;
+ tl_d2h_t tl_asf_28_us_d2h ;
+ tl_h2d_t tl_asf_28_ds_h2d ;
+ tl_d2h_t tl_asf_28_ds_d2h ;
tl_h2d_t tl_sm1_29_us_h2d [2];
@@ -231,12 +235,10 @@
tl_h2d_t tl_sm1_30_ds_h2d ;
tl_d2h_t tl_sm1_30_ds_d2h ;
-
- tl_h2d_t tl_sm1_31_us_h2d [2];
- tl_d2h_t tl_sm1_31_us_d2h [2];
-
- tl_h2d_t tl_sm1_31_ds_h2d ;
- tl_d2h_t tl_sm1_31_ds_d2h ;
+ tl_h2d_t tl_asf_31_us_h2d ;
+ tl_d2h_t tl_asf_31_us_d2h ;
+ tl_h2d_t tl_asf_31_ds_h2d ;
+ tl_d2h_t tl_asf_31_ds_d2h ;
tl_h2d_t tl_sm1_32_us_h2d [2];
@@ -259,15 +261,43 @@
tl_h2d_t tl_sm1_34_ds_h2d ;
tl_d2h_t tl_sm1_34_ds_d2h ;
- tl_h2d_t tl_s1n_35_us_h2d ;
- tl_d2h_t tl_s1n_35_us_d2h ;
+
+ tl_h2d_t tl_sm1_35_us_h2d [2];
+ tl_d2h_t tl_sm1_35_us_d2h [2];
+
+ tl_h2d_t tl_sm1_35_ds_h2d ;
+ tl_d2h_t tl_sm1_35_ds_d2h ;
- tl_h2d_t tl_s1n_35_ds_h2d [14];
- tl_d2h_t tl_s1n_35_ds_d2h [14];
+ tl_h2d_t tl_sm1_36_us_h2d [2];
+ tl_d2h_t tl_sm1_36_us_d2h [2];
+
+ tl_h2d_t tl_sm1_36_ds_h2d ;
+ tl_d2h_t tl_sm1_36_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_37_us_h2d [2];
+ tl_d2h_t tl_sm1_37_us_d2h [2];
+
+ tl_h2d_t tl_sm1_37_ds_h2d ;
+ tl_d2h_t tl_sm1_37_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_38_us_h2d [2];
+ tl_d2h_t tl_sm1_38_us_d2h [2];
+
+ tl_h2d_t tl_sm1_38_ds_h2d ;
+ tl_d2h_t tl_sm1_38_ds_d2h ;
+
+ tl_h2d_t tl_s1n_39_us_h2d ;
+ tl_d2h_t tl_s1n_39_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_39_ds_h2d [14];
+ tl_d2h_t tl_s1n_39_ds_d2h [14];
// Create steering signal
- logic [3:0] dev_sel_s1n_35;
+ logic [3:0] dev_sel_s1n_39;
@@ -295,80 +325,80 @@
assign tl_sm1_22_us_h2d[1] = tl_s1n_23_ds_h2d[3];
assign tl_s1n_23_ds_d2h[3] = tl_sm1_22_us_d2h[1];
- assign tl_sm1_24_us_h2d[0] = tl_s1n_23_ds_h2d[4];
- assign tl_s1n_23_ds_d2h[4] = tl_sm1_24_us_d2h[0];
+ assign tl_sm1_25_us_h2d[0] = tl_s1n_23_ds_h2d[4];
+ assign tl_s1n_23_ds_d2h[4] = tl_sm1_25_us_d2h[0];
- assign tl_sm1_25_us_h2d[0] = tl_s1n_23_ds_h2d[5];
- assign tl_s1n_23_ds_d2h[5] = tl_sm1_25_us_d2h[0];
+ assign tl_sm1_27_us_h2d[0] = tl_s1n_23_ds_h2d[5];
+ assign tl_s1n_23_ds_d2h[5] = tl_sm1_27_us_d2h[0];
- assign tl_sm1_26_us_h2d[0] = tl_s1n_23_ds_h2d[6];
- assign tl_s1n_23_ds_d2h[6] = tl_sm1_26_us_d2h[0];
+ assign tl_sm1_29_us_h2d[0] = tl_s1n_23_ds_h2d[6];
+ assign tl_s1n_23_ds_d2h[6] = tl_sm1_29_us_d2h[0];
- assign tl_sm1_27_us_h2d[0] = tl_s1n_23_ds_h2d[7];
- assign tl_s1n_23_ds_d2h[7] = tl_sm1_27_us_d2h[0];
+ assign tl_sm1_30_us_h2d[0] = tl_s1n_23_ds_h2d[7];
+ assign tl_s1n_23_ds_d2h[7] = tl_sm1_30_us_d2h[0];
- assign tl_sm1_28_us_h2d[0] = tl_s1n_23_ds_h2d[8];
- assign tl_s1n_23_ds_d2h[8] = tl_sm1_28_us_d2h[0];
+ assign tl_sm1_32_us_h2d[0] = tl_s1n_23_ds_h2d[8];
+ assign tl_s1n_23_ds_d2h[8] = tl_sm1_32_us_d2h[0];
- assign tl_sm1_29_us_h2d[0] = tl_s1n_23_ds_h2d[9];
- assign tl_s1n_23_ds_d2h[9] = tl_sm1_29_us_d2h[0];
+ assign tl_sm1_33_us_h2d[0] = tl_s1n_23_ds_h2d[9];
+ assign tl_s1n_23_ds_d2h[9] = tl_sm1_33_us_d2h[0];
- assign tl_sm1_30_us_h2d[0] = tl_s1n_23_ds_h2d[10];
- assign tl_s1n_23_ds_d2h[10] = tl_sm1_30_us_d2h[0];
+ assign tl_sm1_34_us_h2d[0] = tl_s1n_23_ds_h2d[10];
+ assign tl_s1n_23_ds_d2h[10] = tl_sm1_34_us_d2h[0];
- assign tl_sm1_31_us_h2d[0] = tl_s1n_23_ds_h2d[11];
- assign tl_s1n_23_ds_d2h[11] = tl_sm1_31_us_d2h[0];
+ assign tl_sm1_35_us_h2d[0] = tl_s1n_23_ds_h2d[11];
+ assign tl_s1n_23_ds_d2h[11] = tl_sm1_35_us_d2h[0];
- assign tl_sm1_32_us_h2d[0] = tl_s1n_23_ds_h2d[12];
- assign tl_s1n_23_ds_d2h[12] = tl_sm1_32_us_d2h[0];
+ assign tl_sm1_36_us_h2d[0] = tl_s1n_23_ds_h2d[12];
+ assign tl_s1n_23_ds_d2h[12] = tl_sm1_36_us_d2h[0];
- assign tl_sm1_33_us_h2d[0] = tl_s1n_23_ds_h2d[13];
- assign tl_s1n_23_ds_d2h[13] = tl_sm1_33_us_d2h[0];
+ assign tl_sm1_37_us_h2d[0] = tl_s1n_23_ds_h2d[13];
+ assign tl_s1n_23_ds_d2h[13] = tl_sm1_37_us_d2h[0];
- assign tl_sm1_34_us_h2d[0] = tl_s1n_23_ds_h2d[14];
- assign tl_s1n_23_ds_d2h[14] = tl_sm1_34_us_d2h[0];
+ assign tl_sm1_38_us_h2d[0] = tl_s1n_23_ds_h2d[14];
+ assign tl_s1n_23_ds_d2h[14] = tl_sm1_38_us_d2h[0];
- assign tl_sm1_19_us_h2d[2] = tl_s1n_35_ds_h2d[0];
- assign tl_s1n_35_ds_d2h[0] = tl_sm1_19_us_d2h[2];
+ assign tl_sm1_19_us_h2d[2] = tl_s1n_39_ds_h2d[0];
+ assign tl_s1n_39_ds_d2h[0] = tl_sm1_19_us_d2h[2];
- assign tl_sm1_21_us_h2d[2] = tl_s1n_35_ds_h2d[1];
- assign tl_s1n_35_ds_d2h[1] = tl_sm1_21_us_d2h[2];
+ assign tl_sm1_21_us_h2d[2] = tl_s1n_39_ds_h2d[1];
+ assign tl_s1n_39_ds_d2h[1] = tl_sm1_21_us_d2h[2];
- assign tl_sm1_22_us_h2d[2] = tl_s1n_35_ds_h2d[2];
- assign tl_s1n_35_ds_d2h[2] = tl_sm1_22_us_d2h[2];
+ assign tl_sm1_22_us_h2d[2] = tl_s1n_39_ds_h2d[2];
+ assign tl_s1n_39_ds_d2h[2] = tl_sm1_22_us_d2h[2];
- assign tl_sm1_24_us_h2d[1] = tl_s1n_35_ds_h2d[3];
- assign tl_s1n_35_ds_d2h[3] = tl_sm1_24_us_d2h[1];
+ assign tl_sm1_25_us_h2d[1] = tl_s1n_39_ds_h2d[3];
+ assign tl_s1n_39_ds_d2h[3] = tl_sm1_25_us_d2h[1];
- assign tl_sm1_25_us_h2d[1] = tl_s1n_35_ds_h2d[4];
- assign tl_s1n_35_ds_d2h[4] = tl_sm1_25_us_d2h[1];
+ assign tl_sm1_27_us_h2d[1] = tl_s1n_39_ds_h2d[4];
+ assign tl_s1n_39_ds_d2h[4] = tl_sm1_27_us_d2h[1];
- assign tl_sm1_26_us_h2d[1] = tl_s1n_35_ds_h2d[5];
- assign tl_s1n_35_ds_d2h[5] = tl_sm1_26_us_d2h[1];
+ assign tl_sm1_29_us_h2d[1] = tl_s1n_39_ds_h2d[5];
+ assign tl_s1n_39_ds_d2h[5] = tl_sm1_29_us_d2h[1];
- assign tl_sm1_27_us_h2d[1] = tl_s1n_35_ds_h2d[6];
- assign tl_s1n_35_ds_d2h[6] = tl_sm1_27_us_d2h[1];
+ assign tl_sm1_30_us_h2d[1] = tl_s1n_39_ds_h2d[6];
+ assign tl_s1n_39_ds_d2h[6] = tl_sm1_30_us_d2h[1];
- assign tl_sm1_28_us_h2d[1] = tl_s1n_35_ds_h2d[7];
- assign tl_s1n_35_ds_d2h[7] = tl_sm1_28_us_d2h[1];
+ assign tl_sm1_32_us_h2d[1] = tl_s1n_39_ds_h2d[7];
+ assign tl_s1n_39_ds_d2h[7] = tl_sm1_32_us_d2h[1];
- assign tl_sm1_29_us_h2d[1] = tl_s1n_35_ds_h2d[8];
- assign tl_s1n_35_ds_d2h[8] = tl_sm1_29_us_d2h[1];
+ assign tl_sm1_33_us_h2d[1] = tl_s1n_39_ds_h2d[8];
+ assign tl_s1n_39_ds_d2h[8] = tl_sm1_33_us_d2h[1];
- assign tl_sm1_30_us_h2d[1] = tl_s1n_35_ds_h2d[9];
- assign tl_s1n_35_ds_d2h[9] = tl_sm1_30_us_d2h[1];
+ assign tl_sm1_34_us_h2d[1] = tl_s1n_39_ds_h2d[9];
+ assign tl_s1n_39_ds_d2h[9] = tl_sm1_34_us_d2h[1];
- assign tl_sm1_31_us_h2d[1] = tl_s1n_35_ds_h2d[10];
- assign tl_s1n_35_ds_d2h[10] = tl_sm1_31_us_d2h[1];
+ assign tl_sm1_35_us_h2d[1] = tl_s1n_39_ds_h2d[10];
+ assign tl_s1n_39_ds_d2h[10] = tl_sm1_35_us_d2h[1];
- assign tl_sm1_32_us_h2d[1] = tl_s1n_35_ds_h2d[11];
- assign tl_s1n_35_ds_d2h[11] = tl_sm1_32_us_d2h[1];
+ assign tl_sm1_36_us_h2d[1] = tl_s1n_39_ds_h2d[11];
+ assign tl_s1n_39_ds_d2h[11] = tl_sm1_36_us_d2h[1];
- assign tl_sm1_33_us_h2d[1] = tl_s1n_35_ds_h2d[12];
- assign tl_s1n_35_ds_d2h[12] = tl_sm1_33_us_d2h[1];
+ assign tl_sm1_37_us_h2d[1] = tl_s1n_39_ds_h2d[12];
+ assign tl_s1n_39_ds_d2h[12] = tl_sm1_37_us_d2h[1];
- assign tl_sm1_34_us_h2d[1] = tl_s1n_35_ds_h2d[13];
- assign tl_s1n_35_ds_d2h[13] = tl_sm1_34_us_d2h[1];
+ assign tl_sm1_38_us_h2d[1] = tl_s1n_39_ds_h2d[13];
+ assign tl_s1n_39_ds_d2h[13] = tl_sm1_38_us_d2h[1];
assign tl_s1n_18_us_h2d = tl_corei_i;
assign tl_corei_o = tl_s1n_18_us_d2h;
@@ -388,41 +418,53 @@
assign tl_s1n_23_us_h2d = tl_cored_i;
assign tl_cored_o = tl_s1n_23_us_d2h;
- assign tl_uart_o = tl_sm1_24_ds_h2d;
- assign tl_sm1_24_ds_d2h = tl_uart_i;
+ assign tl_uart_o = tl_asf_24_ds_h2d;
+ assign tl_asf_24_ds_d2h = tl_uart_i;
- assign tl_gpio_o = tl_sm1_25_ds_h2d;
- assign tl_sm1_25_ds_d2h = tl_gpio_i;
+ assign tl_asf_24_us_h2d = tl_sm1_25_ds_h2d;
+ assign tl_sm1_25_ds_d2h = tl_asf_24_us_d2h;
- assign tl_spi_device_o = tl_sm1_26_ds_h2d;
- assign tl_sm1_26_ds_d2h = tl_spi_device_i;
+ assign tl_gpio_o = tl_asf_26_ds_h2d;
+ assign tl_asf_26_ds_d2h = tl_gpio_i;
- assign tl_flash_ctrl_o = tl_sm1_27_ds_h2d;
- assign tl_sm1_27_ds_d2h = tl_flash_ctrl_i;
+ assign tl_asf_26_us_h2d = tl_sm1_27_ds_h2d;
+ assign tl_sm1_27_ds_d2h = tl_asf_26_us_d2h;
- assign tl_rv_timer_o = tl_sm1_28_ds_h2d;
- assign tl_sm1_28_ds_d2h = tl_rv_timer_i;
+ assign tl_spi_device_o = tl_asf_28_ds_h2d;
+ assign tl_asf_28_ds_d2h = tl_spi_device_i;
- assign tl_aes_o = tl_sm1_29_ds_h2d;
- assign tl_sm1_29_ds_d2h = tl_aes_i;
+ assign tl_asf_28_us_h2d = tl_sm1_29_ds_h2d;
+ assign tl_sm1_29_ds_d2h = tl_asf_28_us_d2h;
- assign tl_hmac_o = tl_sm1_30_ds_h2d;
- assign tl_sm1_30_ds_d2h = tl_hmac_i;
+ assign tl_flash_ctrl_o = tl_sm1_30_ds_h2d;
+ assign tl_sm1_30_ds_d2h = tl_flash_ctrl_i;
- assign tl_rv_plic_o = tl_sm1_31_ds_h2d;
- assign tl_sm1_31_ds_d2h = tl_rv_plic_i;
+ assign tl_rv_timer_o = tl_asf_31_ds_h2d;
+ assign tl_asf_31_ds_d2h = tl_rv_timer_i;
- assign tl_pinmux_o = tl_sm1_32_ds_h2d;
- assign tl_sm1_32_ds_d2h = tl_pinmux_i;
+ assign tl_asf_31_us_h2d = tl_sm1_32_ds_h2d;
+ assign tl_sm1_32_ds_d2h = tl_asf_31_us_d2h;
- assign tl_alert_handler_o = tl_sm1_33_ds_h2d;
- assign tl_sm1_33_ds_d2h = tl_alert_handler_i;
+ assign tl_aes_o = tl_sm1_33_ds_h2d;
+ assign tl_sm1_33_ds_d2h = tl_aes_i;
- assign tl_nmi_gen_o = tl_sm1_34_ds_h2d;
- assign tl_sm1_34_ds_d2h = tl_nmi_gen_i;
+ assign tl_hmac_o = tl_sm1_34_ds_h2d;
+ assign tl_sm1_34_ds_d2h = tl_hmac_i;
- assign tl_s1n_35_us_h2d = tl_dm_sba_i;
- assign tl_dm_sba_o = tl_s1n_35_us_d2h;
+ assign tl_rv_plic_o = tl_sm1_35_ds_h2d;
+ assign tl_sm1_35_ds_d2h = tl_rv_plic_i;
+
+ assign tl_pinmux_o = tl_sm1_36_ds_h2d;
+ assign tl_sm1_36_ds_d2h = tl_pinmux_i;
+
+ assign tl_alert_handler_o = tl_sm1_37_ds_h2d;
+ assign tl_sm1_37_ds_d2h = tl_alert_handler_i;
+
+ assign tl_nmi_gen_o = tl_sm1_38_ds_h2d;
+ assign tl_sm1_38_ds_d2h = tl_nmi_gen_i;
+
+ assign tl_s1n_39_us_h2d = tl_dm_sba_i;
+ assign tl_dm_sba_o = tl_s1n_39_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
@@ -476,35 +518,35 @@
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_35 = 4'd14;
- if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_35 = 4'd0;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_35 = 4'd1;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_35 = 4'd2;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
- dev_sel_s1n_35 = 4'd3;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_35 = 4'd4;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_35 = 4'd5;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_35 = 4'd6;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_35 = 4'd7;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_35 = 4'd8;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_35 = 4'd9;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_35 = 4'd10;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
- dev_sel_s1n_35 = 4'd11;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
- dev_sel_s1n_35 = 4'd12;
- end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
- dev_sel_s1n_35 = 4'd13;
+ dev_sel_s1n_39 = 4'd14;
+ if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_39 = 4'd0;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_39 = 4'd1;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_39 = 4'd2;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+ dev_sel_s1n_39 = 4'd3;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_39 = 4'd4;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_39 = 4'd5;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_39 = 4'd6;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_39 = 4'd7;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_39 = 4'd8;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_39 = 4'd9;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_39 = 4'd10;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+ dev_sel_s1n_39 = 4'd11;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+ dev_sel_s1n_39 = 4'd12;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+ dev_sel_s1n_39 = 4'd13;
end
end
@@ -596,25 +638,20 @@
.tl_d_i (tl_s1n_23_ds_d2h),
.dev_select (dev_sel_s1n_23)
);
- tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_24 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_24_us_h2d),
- .tl_h_o (tl_sm1_24_us_d2h),
- .tl_d_o (tl_sm1_24_ds_h2d),
- .tl_d_i (tl_sm1_24_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (3),// At least 3 to make async work
+ .RspDepth (3) // At least 3 to make async work
+ ) u_asf_24 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_fixed_i),
+ .rst_d_ni (rst_fixed_ni),
+ .tl_h_i (tl_asf_24_us_h2d),
+ .tl_h_o (tl_asf_24_us_d2h),
+ .tl_d_o (tl_asf_24_ds_h2d),
+ .tl_d_i (tl_asf_24_ds_d2h)
);
tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
.M (2)
) u_sm1_25 (
.clk_i (clk_main_i),
@@ -624,25 +661,20 @@
.tl_d_o (tl_sm1_25_ds_h2d),
.tl_d_i (tl_sm1_25_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_26 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_26_us_h2d),
- .tl_h_o (tl_sm1_26_us_d2h),
- .tl_d_o (tl_sm1_26_ds_h2d),
- .tl_d_i (tl_sm1_26_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (3),// At least 3 to make async work
+ .RspDepth (3) // At least 3 to make async work
+ ) u_asf_26 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_fixed_i),
+ .rst_d_ni (rst_fixed_ni),
+ .tl_h_i (tl_asf_26_us_h2d),
+ .tl_h_o (tl_asf_26_us_d2h),
+ .tl_d_o (tl_asf_26_ds_h2d),
+ .tl_d_i (tl_asf_26_ds_d2h)
);
tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
.M (2)
) u_sm1_27 (
.clk_i (clk_main_i),
@@ -652,25 +684,20 @@
.tl_d_o (tl_sm1_27_ds_h2d),
.tl_d_i (tl_sm1_27_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_28 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_28_us_h2d),
- .tl_h_o (tl_sm1_28_us_d2h),
- .tl_d_o (tl_sm1_28_ds_h2d),
- .tl_d_i (tl_sm1_28_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (3),// At least 3 to make async work
+ .RspDepth (3) // At least 3 to make async work
+ ) u_asf_28 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_fixed_i),
+ .rst_d_ni (rst_fixed_ni),
+ .tl_h_i (tl_asf_28_us_h2d),
+ .tl_h_o (tl_asf_28_us_d2h),
+ .tl_d_o (tl_asf_28_ds_h2d),
+ .tl_d_i (tl_asf_28_ds_d2h)
);
tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
.M (2)
) u_sm1_29 (
.clk_i (clk_main_i),
@@ -694,25 +721,20 @@
.tl_d_o (tl_sm1_30_ds_h2d),
.tl_d_i (tl_sm1_30_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_31 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_31_us_h2d),
- .tl_h_o (tl_sm1_31_us_d2h),
- .tl_d_o (tl_sm1_31_ds_h2d),
- .tl_d_i (tl_sm1_31_ds_d2h)
+ tlul_fifo_async #(
+ .ReqDepth (3),// At least 3 to make async work
+ .RspDepth (3) // At least 3 to make async work
+ ) u_asf_31 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_fixed_i),
+ .rst_d_ni (rst_fixed_ni),
+ .tl_h_i (tl_asf_31_us_h2d),
+ .tl_h_o (tl_asf_31_us_d2h),
+ .tl_d_o (tl_asf_31_ds_h2d),
+ .tl_d_i (tl_asf_31_ds_d2h)
);
tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
.M (2)
) u_sm1_32 (
.clk_i (clk_main_i),
@@ -750,20 +772,76 @@
.tl_d_o (tl_sm1_34_ds_h2d),
.tl_d_i (tl_sm1_34_ds_d2h)
);
+ tlul_socket_m1 #(
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_35 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_35_us_h2d),
+ .tl_h_o (tl_sm1_35_us_d2h),
+ .tl_d_o (tl_sm1_35_ds_h2d),
+ .tl_d_i (tl_sm1_35_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_36 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_36_us_h2d),
+ .tl_h_o (tl_sm1_36_us_d2h),
+ .tl_d_o (tl_sm1_36_ds_h2d),
+ .tl_d_i (tl_sm1_36_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_37 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_37_us_h2d),
+ .tl_h_o (tl_sm1_37_us_d2h),
+ .tl_d_o (tl_sm1_37_ds_h2d),
+ .tl_d_i (tl_sm1_37_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_38 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_38_us_h2d),
+ .tl_h_o (tl_sm1_38_us_d2h),
+ .tl_d_o (tl_sm1_38_ds_h2d),
+ .tl_d_i (tl_sm1_38_ds_d2h)
+ );
tlul_socket_1n #(
.HReqPass (1'b0),
.HRspPass (1'b0),
.DReqPass (14'h0),
.DRspPass (14'h0),
.N (14)
- ) u_s1n_35 (
+ ) u_s1n_39 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_35_us_h2d),
- .tl_h_o (tl_s1n_35_us_d2h),
- .tl_d_o (tl_s1n_35_ds_h2d),
- .tl_d_i (tl_s1n_35_ds_d2h),
- .dev_select (dev_sel_s1n_35)
+ .tl_h_i (tl_s1n_39_us_h2d),
+ .tl_h_o (tl_s1n_39_us_d2h),
+ .tl_d_o (tl_s1n_39_ds_h2d),
+ .tl_d_i (tl_s1n_39_ds_d2h),
+ .dev_select (dev_sel_s1n_39)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 0720b72..b79ceb0 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -96,10 +96,12 @@
//reset wires declaration
logic lc_rst_n;
logic sys_rst_n;
+ logic sys_fixed_rst_n;
logic spi_device_rst_n;
//clock wires declaration
logic main_clk;
+ logic fixed_clk;
// Signals
logic [31:0] m2p;
@@ -185,6 +187,7 @@
// clock assignments
assign main_clk = clk_i;
+ assign fixed_clk = clk_i;
// Non-debug module reset == reset for everything except for the debug module
logic ndmreset_req;
@@ -196,6 +199,7 @@
assign sys_rst_n = (scanmode_i) ? lc_rst_n : ~ndmreset_req & lc_rst_n;
//non-root reset assignments
+ assign sys_fixed_rst_n = sys_rst_n;
assign spi_device_rst_n = sys_rst_n;
// debug request from rv_dm to core
@@ -434,8 +438,8 @@
.intr_rx_timeout_o (intr_uart_rx_timeout),
.intr_rx_parity_err_o (intr_uart_rx_parity_err),
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
+ .clk_i (fixed_clk),
+ .rst_ni (sys_fixed_rst_n)
);
gpio gpio (
@@ -452,8 +456,8 @@
// Interrupt
.intr_gpio_o (intr_gpio_gpio),
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
+ .clk_i (fixed_clk),
+ .rst_ni (sys_fixed_rst_n)
);
spi_device spi_device (
@@ -478,7 +482,7 @@
.intr_txunderflow_o (intr_spi_device_txunderflow),
.scanmode_i (scanmode_i),
- .clk_i (main_clk),
+ .clk_i (fixed_clk),
.rst_ni (spi_device_rst_n)
);
@@ -508,8 +512,8 @@
// Interrupt
.intr_timer_expired_0_0_o (intr_rv_timer_timer_expired_0_0),
- .clk_i (main_clk),
- .rst_ni (sys_rst_n)
+ .clk_i (fixed_clk),
+ .rst_ni (sys_fixed_rst_n)
);
aes aes (
@@ -646,7 +650,9 @@
// TL-UL Crossbar
xbar_main u_xbar_main (
.clk_main_i (main_clk),
+ .clk_fixed_i (fixed_clk),
.rst_main_ni (sys_rst_n),
+ .rst_fixed_ni (sys_fixed_rst_n),
.tl_corei_i (tl_corei_h_h2d),
.tl_corei_o (tl_corei_h_d2h),
.tl_cored_i (tl_cored_h_h2d),
