[rv_plic] Import package only once
The rv_plic template imported the rv_plic_reg_pkg once in the header and
once in the body; remove the import in the body to avoid a NOTE from
VCS during regression runs.
Regenerated SystemVerilog files after changes to the template.
```
Parsing design file '../src/lowrisc_top_earlgrey_rv_plic_0.1/rtl/autogen/rv_plic.sv'
Note-[SV-LCM-PPWI] Package previously wildcard imported
../src/lowrisc_top_earlgrey_rv_plic_0.1/rtl/autogen/rv_plic.sv, 46
rv_plic
Package 'rv_plic_reg_pkg' already wildcard imported.
Ignoring rv_plic_reg_pkg::*
See the SystemVerilog LRM(1800-2005), section 19.2.1.
```
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/rv_plic/data/rv_plic.sv.tpl b/hw/ip/rv_plic/data/rv_plic.sv.tpl
index a4fe14d..b0c93f7 100644
--- a/hw/ip/rv_plic/data/rv_plic.sv.tpl
+++ b/hw/ip/rv_plic/data/rv_plic.sv.tpl
@@ -35,8 +35,6 @@
output logic [NumTarget-1:0] msip_o
);
- import rv_plic_reg_pkg::*;
-
rv_plic_reg2hw_t reg2hw;
rv_plic_hw2reg_t hw2reg;
diff --git a/hw/ip/rv_plic/rtl/rv_plic.sv b/hw/ip/rv_plic/rtl/rv_plic.sv
index a5aae45..a96210f 100644
--- a/hw/ip/rv_plic/rtl/rv_plic.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic.sv
@@ -14,8 +14,6 @@
// Verilog parameter
// MAX_PRIO: Maximum value of interrupt priority
-`include "prim_assert.sv"
-
module rv_plic import rv_plic_reg_pkg::*; #(
// derived parameter
localparam int SRCW = $clog2(NumSrc+1)
@@ -37,8 +35,6 @@
output logic [NumTarget-1:0] msip_o
);
- import rv_plic_reg_pkg::*;
-
rv_plic_reg2hw_t reg2hw;
rv_plic_hw2reg_t hw2reg;
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index 0719500..c8d36ed 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -43,8 +43,6 @@
output logic [NumTarget-1:0] msip_o
);
- import rv_plic_reg_pkg::*;
-
rv_plic_reg2hw_t reg2hw;
rv_plic_hw2reg_t hw2reg;
