[doc] Clarify lc requested external clock switch
- fixes #12092
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/clkmgr/doc/_index.md b/hw/ip/clkmgr/doc/_index.md
index fe7f079..486078c 100644
--- a/hw/ip/clkmgr/doc/_index.md
+++ b/hw/ip/clkmgr/doc/_index.md
@@ -242,11 +242,12 @@
This table assumes that the internal clock source is 96MHz.
This table also assumes that high speed external clock is 96MHz, while low speed external clock is 48MHz.
-| Mode | div_1_clock | div_2_clock | div_4_clock |
-| ------------- | ------------- | --------------- | -------------|
-| Internal Clocks | 96MHz | 48MHz | 24MHz |
-| Software external high speed | 96MHz | 48MHz | 24MHz |
-| Software external low speed | 48MHz | 48MHz | 24MHz |
+| Mode | External Clock Frequency | div_1_clock | div_2_clock | div_4_clock |
+| ------------- | ------------------------ | ------------- | --------------- | -------------|
+| Internal Clocks | Not applicable | 96MHz | 48MHz | 24MHz |
+| Life cycle transition | 48MHz | 48MHz | 48MHz | 24MHz |
+| Software external high speed | 96MHz | 96MHz | 48MHz | 24MHz |
+| Software external low speed | 48MHz | 48MHz | 48MHz | 24MHz |
As can be seen from the table, the external clock switch scheme prioritizes the stability of the divided clocks, while allowing the undivided clocks to slow down.
diff --git a/hw/ip/lc_ctrl/doc/_index.md b/hw/ip/lc_ctrl/doc/_index.md
index 479d28a..656ea11 100644
--- a/hw/ip/lc_ctrl/doc/_index.md
+++ b/hw/ip/lc_ctrl/doc/_index.md
@@ -222,11 +222,13 @@
#### CLK_BYP_REQ
-If the life cycle state is in RAW, TEST* or RMA, and if {{< regref OTP_TEST_CTRL.EXT_CLOCK >}} is set to one, the CLK_BYP_REQ signal is asserted in order to switch the main system clock to an external clock signal.
+If the life cycle state is in RAW, TEST* or RMA, and if {{< regref TRANSITION_CTRL.EXT_CLOCK_EN >}} is set to one, the CLK_BYP_REQ signal is asserted in order to switch the main system clock to an external clock signal.
This functionality is needed in certain life cycle states where the internal clock source may not be fully calibrated yet, since the OTP macro requires a stable clock frequency in order to reliably program the fuse array.
The CLK_BYP_REQ signal is only asserted when a transition command is issued.
This function is not available in production life cycle states.
+For details on the clock switch, please see [clkmgr]({{< relref "hw/ip/clkmgr/doc/_index.md#life-cycle-requested-external-clock" >}}).
+
### Life Cycle Access Control Signals
