commit 64b7a6ea08ed1cf7bba8970cf993ae2b502cad59
author Srikrishna Iyer <sriyer@google.com> Sat Apr 25 02:15:14 2020 -0700
committer Garret Kelly <Garret.Kelly@gmail.com> Fri May 01 16:06:06 2020 -0400
tree e63a495fd24979e2c56df1c83c31631047d8643c
parent e89bc961d0ab2f6f7a73b158d4b9a1ff337789d1

[chip dv] Add `aes_test` to chip level DV

Signed-off-by: Srikrishna Iyer <sriyer@google.com>

hw/top_earlgrey/dv/chip_sim_cfg.hjson

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 0f1c3b4..d5c9481 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -81,6 +81,13 @@
       sw_dir: examples/hello_world
     }
     {
+      name: chip_aes_test
+      uvm_test_seq: chip_sw_test_base_vseq
+      sw_name: aes_test
+      sw_dir: tests
+      run_opts: ["+sw_test_timeout_ns=15000000"]
+    }
+    {
       name: chip_flash_test
       uvm_test_seq: chip_sw_test_base_vseq
       sw_name: flash_test