[prim_mubi] Make sure waiver file is listed in core file
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/prim/lint/prim_mubi.waiver b/hw/ip/prim/lint/prim_mubi.waiver
index 630bb2c..c7527fb 100644
--- a/hw/ip/prim/lint/prim_mubi.waiver
+++ b/hw/ip/prim/lint/prim_mubi.waiver
@@ -4,7 +4,7 @@
#
# waiver file for prim_mubi modules
-waive -rules SAME_NAME_TYPE -location {prim_mubi4_sync.sv} -regexp {'ResetValue' is used as an enumeration value here, and as a parameter at prim.*} \
+waive -rules {SAME_NAME_TYPE} -location {prim_mubi*.sv} -regexp {'ResetValue' is used as an enumeration value here, and as a parameter at prim.*} \
-comment "Parameter name reuse"
diff --git a/hw/ip/prim/prim_mubi.core b/hw/ip/prim/prim_mubi.core
index 55014d7..f51e455 100644
--- a/hw/ip/prim/prim_mubi.core
+++ b/hw/ip/prim/prim_mubi.core
@@ -32,7 +32,41 @@
- rtl/prim_mubi16_dec.sv
file_type: systemVerilogSource
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/prim_mubi.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
targets:
- default:
+ default: &default_target
filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/prim/rtl/prim_onehot_check.sv b/hw/ip/prim/rtl/prim_onehot_check.sv
index e2137a5..ccfb810 100644
--- a/hw/ip/prim/rtl/prim_onehot_check.sv
+++ b/hw/ip/prim/rtl/prim_onehot_check.sv
@@ -119,6 +119,8 @@
`ASSERT(EnableCheck_A, !en_i && (|oh_i) |-> err_o)
end
end else begin : gen_no_enable_check
+ logic unused_or_tree;
+ assign unused_or_tree = or_tree[0];
assign enable_err = 1'b0;
end
@@ -127,6 +129,8 @@
assign addr_err = or_tree[0] ^ and_tree[0];
`ASSERT(AddrCheck_A, oh_i[addr_i] != (|oh_i) |-> err_o)
end else begin : gen_no_addr_check_strict
+ logic unused_and_tree;
+ assign unused_and_tree = and_tree[0];
assign addr_err = 1'b0;
end
diff --git a/util/design/data/prim_mubi.core.tpl b/util/design/data/prim_mubi.core.tpl
index 56cda84..fe423e8 100644
--- a/util/design/data/prim_mubi.core.tpl
+++ b/util/design/data/prim_mubi.core.tpl
@@ -25,7 +25,41 @@
% endfor
file_type: systemVerilogSource
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/prim_mubi.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
targets:
- default:
+ default: &default_target
filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
