[top] Auto generate Signed-off-by: Timothy Chen <timothytim@google.com>

commit: 63a0f5e3f58641fe53c7df0d52db551219b282f4 [log] [tgz]
author: Timothy Chen <timothytim@google.com> Wed Sep 15 15:33:06 2021 -0700
committer: tjaychen <timothytim@google.com> Tue Sep 21 15:40:21 2021 -0700
tree: 3c8911da6aaf486f88b9c0af506502bc49bee364
parent: 37eec2cbcb02ab1639382d3dbb8ab2bc5b3b904d [diff]
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 3b457aa..8680884 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson

@@ -12929,7 +12929,7 @@
       module_name: flash_ctrl
     }
     {
-      name: flash_ctrl_err
+      name: flash_ctrl_corr_err
       width: 1
       type: interrupt
       module_name: flash_ctrl
@@ -13333,21 +13333,7 @@
       module_name: flash_ctrl
     }
     {
-      name: flash_ctrl_recov_mp_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_recov_ecc_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_fatal_intg_err
+      name: flash_ctrl_fatal_err
       width: 1
       type: alert
       async: "1"

diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 51ce487..dc850f9 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv

@@ -38,29 +38,27 @@
 assign alert_if[31].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
 assign alert_if[32].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
 assign alert_if[33].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[34].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
-assign alert_if[37].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[43].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[44].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[45].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
-assign alert_if[46].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[47].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[48].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[49].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
-assign alert_if[50].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[51].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
-assign alert_if[52].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[53].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[54].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[55].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
-assign alert_if[56].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
-assign alert_if[57].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
-assign alert_if[58].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
-assign alert_if[59].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
+assign alert_if[48].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[49].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
+assign alert_if[50].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[51].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[52].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[53].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[54].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
+assign alert_if[55].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
+assign alert_if[56].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
+assign alert_if[57].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];

diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 42202e5..0f07e04 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv

@@ -38,9 +38,7 @@
   "sensor_ctrl_fatal_alert",
   "sram_ctrl_ret_aon_fatal_error",
   "flash_ctrl_recov_err",
-  "flash_ctrl_recov_mp_err",
-  "flash_ctrl_recov_ecc_err",
-  "flash_ctrl_fatal_intg_err",
+  "flash_ctrl_fatal_err",
   "rv_dm_fatal_fault",
   "rv_plic_fatal_fault",
   "aes_recov_ctrl_update_err",
@@ -67,4 +65,4 @@
   "rv_core_ibex_recov_hw_err"
 };
 
-parameter uint NUM_ALERTS = 60;
+parameter uint NUM_ALERTS = 58;

diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 8d782bf..b6a572a 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson

@@ -48,7 +48,7 @@
     { name: "NAlerts",
       desc: "Number of alert channels.",
       type: "int",
-      default: "60",
+      default: "58",
       local: "true"
     },
     { name: "EscCntDw",
@@ -69,7 +69,7 @@
             defines whether the protocol is synchronous (0) or asynchronous (1).
             '''
       type: "logic [NAlerts-1:0]",
-      default: "60'hfffffffffffffff",
+      default: "58'h3ffffffffffffff",
       local: "true"
     },
     { name: "N_CLASSES",

diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 26c6a24..5313579 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv

@@ -7,10 +7,10 @@
 package alert_handler_reg_pkg;
 
   // Param list
-  parameter int NAlerts = 60;
+  parameter int NAlerts = 58;
   parameter int EscCntDw = 32;
   parameter int AccuCntDw = 16;
-  parameter logic [NAlerts-1:0] AsyncOn = 60'hfffffffffffffff;
+  parameter logic [NAlerts-1:0] AsyncOn = 58'h3ffffffffffffff;
   parameter int N_CLASSES = 4;
   parameter int N_ESC_SEV = 4;
   parameter int N_PHASES = 4;
@@ -638,15 +638,15 @@
 
   // Register -> HW type
   typedef struct packed {
-    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1136:1133]
-    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1132:1129]
-    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1128:1121]
-    alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1120:1105]
-    alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1104:1104]
-    alert_handler_reg2hw_alert_regwen_mreg_t [59:0] alert_regwen; // [1103:1044]
-    alert_handler_reg2hw_alert_en_shadowed_mreg_t [59:0] alert_en_shadowed; // [1043:984]
-    alert_handler_reg2hw_alert_class_shadowed_mreg_t [59:0] alert_class_shadowed; // [983:864]
-    alert_handler_reg2hw_alert_cause_mreg_t [59:0] alert_cause; // [863:804]
+    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1126:1123]
+    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1122:1119]
+    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1118:1111]
+    alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1110:1095]
+    alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1094:1094]
+    alert_handler_reg2hw_alert_regwen_mreg_t [57:0] alert_regwen; // [1093:1036]
+    alert_handler_reg2hw_alert_en_shadowed_mreg_t [57:0] alert_en_shadowed; // [1035:978]
+    alert_handler_reg2hw_alert_class_shadowed_mreg_t [57:0] alert_class_shadowed; // [977:862]
+    alert_handler_reg2hw_alert_cause_mreg_t [57:0] alert_cause; // [861:804]
     alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797]
     alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0]
         loc_alert_class_shadowed; // [796:783]
@@ -699,8 +699,8 @@
 
   // HW -> register type
   typedef struct packed {
-    alert_handler_hw2reg_intr_state_reg_t intr_state; // [353:346]
-    alert_handler_hw2reg_alert_cause_mreg_t [59:0] alert_cause; // [345:226]
+    alert_handler_hw2reg_intr_state_reg_t intr_state; // [349:342]
+    alert_handler_hw2reg_alert_cause_mreg_t [57:0] alert_cause; // [341:226]
     alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212]
     alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
     alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -785,272 +785,264 @@
   parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_55_OFFSET = 11'h f4;
   parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_56_OFFSET = 11'h f8;
   parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_59_OFFSET = 11'h 104;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 108;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 10c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 110;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 114;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 118;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 11c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 120;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 124;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 128;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 12c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 130;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 134;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 138;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 13c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 140;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 144;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 148;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 14c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 150;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 154;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 158;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 15c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 160;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 164;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 168;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 16c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 170;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 174;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 178;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 17c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 180;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 184;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 188;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 18c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 190;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 194;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 198;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 19c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 1f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 1f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 1f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 1fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 200;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 204;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 208;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 20c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 210;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 214;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 218;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 21c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 220;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 224;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 228;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 22c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 230;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 234;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 238;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 23c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 240;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 244;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 248;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 24c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 250;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 254;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 258;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 25c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 260;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 264;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 268;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 26c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 270;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 274;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 278;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 27c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 280;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 284;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 288;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 28c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 290;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 294;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 298;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 29c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 2e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 2e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 2e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 2ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 2f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 2f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 2f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 2fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 300;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 304;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 308;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 30c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 310;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 314;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 318;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 31c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 320;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 324;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 328;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 32c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 330;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 334;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 338;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 33c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 340;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 344;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 348;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 34c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 350;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 354;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 358;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 35c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 360;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 364;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 368;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 36c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 370;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 374;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 378;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 37c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 380;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 384;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 388;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 38c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 390;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 394;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 398;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 39c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 3d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 3d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 3d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 3dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 3e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 3e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 3e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 3ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 3f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 3f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 3f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 3fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 400;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 404;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 408;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 40c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 410;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 414;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 418;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 41c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 420;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 424;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 428;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 42c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 430;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 434;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 438;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 43c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 440;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 444;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 448;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 44c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 450;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 454;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 458;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 45c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 460;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 464;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 468;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 46c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 470;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 474;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 478;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 47c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 480;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 484;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 488;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 48c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 490;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 494;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 498;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 49c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 4e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 4ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 4f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 4f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 4f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 4fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 500;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 504;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 508;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 50c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 510;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 514;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 518;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 51c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 520;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 524;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 100;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 104;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 108;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 10c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 110;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 114;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 118;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 11c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 120;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 124;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 128;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 12c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 130;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 134;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 138;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 13c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 140;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 144;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 148;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 14c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 150;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 154;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 158;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 15c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 160;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 164;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 168;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 16c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 170;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 174;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 178;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 17c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 180;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 184;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 188;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 18c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 190;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 194;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 198;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 19c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 1e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 1ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 1f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 1f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 1f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 1fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 200;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 204;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 208;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 20c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 210;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 214;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 218;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 21c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 220;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 224;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 228;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 22c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 230;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 234;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 238;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 23c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 240;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 244;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 248;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 24c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 250;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 254;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 258;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 25c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 260;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 264;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 268;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 26c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 270;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 274;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 278;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 27c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 280;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 284;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 288;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 28c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 290;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 294;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 298;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 29c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 2d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 2d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 2d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 2dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 2e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 2e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 2e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 2ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 2f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 2f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 2f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 2fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 300;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 304;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 308;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 30c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 310;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 314;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 318;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 31c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 320;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 324;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 328;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 32c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 330;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 334;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 338;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 33c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 340;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 344;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 348;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 34c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 350;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 354;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 358;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 35c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 360;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 364;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 368;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 36c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 370;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 374;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 378;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 37c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 380;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 384;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 388;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 38c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 390;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 394;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 398;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 39c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 3b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 3bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 3c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 3c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 3c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 3cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 3d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 3d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 3d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 3dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 3e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 3e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 3e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 3ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 3f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 3f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 3f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 3fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 400;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 404;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 408;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 40c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 410;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 414;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 418;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 41c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 420;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 424;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 428;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 42c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 430;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 434;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 438;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 43c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 440;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 444;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 448;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 44c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 450;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 454;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 458;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 45c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 460;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 464;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 468;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 46c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 470;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 474;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 478;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 47c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 480;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 484;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 488;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 48c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 490;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 494;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 498;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 49c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 4c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 4cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 4d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 4d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 4d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 4dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 4e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 500;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 504;
 
   // Reset values for hwext registers and their fields
   parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -1137,8 +1129,6 @@
     ALERT_HANDLER_ALERT_REGWEN_55,
     ALERT_HANDLER_ALERT_REGWEN_56,
     ALERT_HANDLER_ALERT_REGWEN_57,
-    ALERT_HANDLER_ALERT_REGWEN_58,
-    ALERT_HANDLER_ALERT_REGWEN_59,
     ALERT_HANDLER_ALERT_EN_SHADOWED_0,
     ALERT_HANDLER_ALERT_EN_SHADOWED_1,
     ALERT_HANDLER_ALERT_EN_SHADOWED_2,
@@ -1197,8 +1187,6 @@
     ALERT_HANDLER_ALERT_EN_SHADOWED_55,
     ALERT_HANDLER_ALERT_EN_SHADOWED_56,
     ALERT_HANDLER_ALERT_EN_SHADOWED_57,
-    ALERT_HANDLER_ALERT_EN_SHADOWED_58,
-    ALERT_HANDLER_ALERT_EN_SHADOWED_59,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_0,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_1,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_2,
@@ -1257,8 +1245,6 @@
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_55,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_56,
     ALERT_HANDLER_ALERT_CLASS_SHADOWED_57,
-    ALERT_HANDLER_ALERT_CLASS_SHADOWED_58,
-    ALERT_HANDLER_ALERT_CLASS_SHADOWED_59,
     ALERT_HANDLER_ALERT_CAUSE_0,
     ALERT_HANDLER_ALERT_CAUSE_1,
     ALERT_HANDLER_ALERT_CAUSE_2,
@@ -1317,8 +1303,6 @@
     ALERT_HANDLER_ALERT_CAUSE_55,
     ALERT_HANDLER_ALERT_CAUSE_56,
     ALERT_HANDLER_ALERT_CAUSE_57,
-    ALERT_HANDLER_ALERT_CAUSE_58,
-    ALERT_HANDLER_ALERT_CAUSE_59,
     ALERT_HANDLER_LOC_ALERT_REGWEN_0,
     ALERT_HANDLER_LOC_ALERT_REGWEN_1,
     ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1406,7 +1390,7 @@
   } alert_handler_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] ALERT_HANDLER_PERMIT [330] = '{
+  parameter logic [3:0] ALERT_HANDLER_PERMIT [322] = '{
     4'b 0001, // index[  0] ALERT_HANDLER_INTR_STATE
     4'b 0001, // index[  1] ALERT_HANDLER_INTR_ENABLE
     4'b 0001, // index[  2] ALERT_HANDLER_INTR_TEST
@@ -1471,272 +1455,264 @@
     4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_REGWEN_55
     4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_REGWEN_56
     4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57
-    4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58
-    4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_REGWEN_59
-    4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_SHADOWED_0
-    4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_SHADOWED_1
-    4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_SHADOWED_2
-    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_3
-    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_4
-    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_5
-    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_6
-    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_7
-    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_8
-    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_9
-    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_10
-    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_11
-    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_12
-    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_13
-    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_14
-    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_15
-    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_16
-    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_17
-    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_18
-    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_19
-    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_20
-    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_21
-    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_22
-    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_23
-    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_24
-    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_25
-    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_26
-    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_27
-    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_28
-    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_29
-    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_30
-    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_31
-    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_32
-    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_33
-    4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_34
-    4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_35
-    4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_36
-    4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_37
-    4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_38
-    4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_39
-    4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_40
-    4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_41
-    4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_42
-    4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_43
-    4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_44
-    4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_45
-    4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_46
-    4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_47
-    4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_48
-    4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_49
-    4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_50
-    4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_51
-    4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_52
-    4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_53
-    4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_54
-    4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_55
-    4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_56
-    4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_57
-    4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_58
-    4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_59
-    4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
-    4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
-    4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
-    4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
-    4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
-    4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
-    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
-    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
-    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
-    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
-    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
-    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
-    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
-    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
-    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
-    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
-    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
-    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
-    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
-    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
-    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
-    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
-    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
-    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
-    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
-    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
-    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
-    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
-    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
-    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
-    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
-    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
-    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
-    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
-    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
-    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
-    4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
-    4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
-    4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
-    4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
-    4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
-    4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
-    4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
-    4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
-    4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
-    4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
-    4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
-    4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
-    4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
-    4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
-    4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
-    4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
-    4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
-    4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
-    4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
-    4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
-    4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
-    4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
-    4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
-    4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59
-    4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_0
-    4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_1
-    4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_2
-    4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_3
-    4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_4
-    4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_5
-    4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_6
-    4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_7
-    4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_8
-    4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_9
-    4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_10
-    4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_11
-    4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_12
-    4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_13
-    4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_14
-    4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_15
-    4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_16
-    4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_17
-    4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_18
-    4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_19
-    4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_20
-    4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_21
-    4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_22
-    4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_23
-    4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_24
-    4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_25
-    4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_26
-    4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_27
-    4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_28
-    4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_29
-    4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_30
-    4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_31
-    4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_32
-    4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_33
-    4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_34
-    4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_35
-    4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_36
-    4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_37
-    4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_38
-    4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_39
-    4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_40
-    4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_41
-    4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_42
-    4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_43
-    4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_44
-    4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_45
-    4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_46
-    4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_47
-    4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_48
-    4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_49
-    4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_50
-    4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_51
-    4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_52
-    4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_53
-    4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_54
-    4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_55
-    4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_56
-    4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_57
-    4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_58
-    4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_59
-    4'b 0001, // index[246] ALERT_HANDLER_LOC_ALERT_REGWEN_0
-    4'b 0001, // index[247] ALERT_HANDLER_LOC_ALERT_REGWEN_1
-    4'b 0001, // index[248] ALERT_HANDLER_LOC_ALERT_REGWEN_2
-    4'b 0001, // index[249] ALERT_HANDLER_LOC_ALERT_REGWEN_3
-    4'b 0001, // index[250] ALERT_HANDLER_LOC_ALERT_REGWEN_4
-    4'b 0001, // index[251] ALERT_HANDLER_LOC_ALERT_REGWEN_5
-    4'b 0001, // index[252] ALERT_HANDLER_LOC_ALERT_REGWEN_6
-    4'b 0001, // index[253] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
-    4'b 0001, // index[254] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
-    4'b 0001, // index[255] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
-    4'b 0001, // index[256] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
-    4'b 0001, // index[257] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
-    4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
-    4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
-    4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
-    4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
-    4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
-    4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
-    4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
-    4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
-    4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
-    4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_CAUSE_0
-    4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_CAUSE_1
-    4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_CAUSE_2
-    4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_CAUSE_3
-    4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_CAUSE_4
-    4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_CAUSE_5
-    4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_CAUSE_6
-    4'b 0001, // index[274] ALERT_HANDLER_CLASSA_REGWEN
-    4'b 0011, // index[275] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
-    4'b 0001, // index[276] ALERT_HANDLER_CLASSA_CLR_REGWEN
-    4'b 0001, // index[277] ALERT_HANDLER_CLASSA_CLR_SHADOWED
-    4'b 0011, // index[278] ALERT_HANDLER_CLASSA_ACCUM_CNT
-    4'b 0011, // index[279] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[280] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[281] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[282] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[283] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[284] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[285] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[286] ALERT_HANDLER_CLASSA_ESC_CNT
-    4'b 0001, // index[287] ALERT_HANDLER_CLASSA_STATE
-    4'b 0001, // index[288] ALERT_HANDLER_CLASSB_REGWEN
-    4'b 0011, // index[289] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
-    4'b 0001, // index[290] ALERT_HANDLER_CLASSB_CLR_REGWEN
-    4'b 0001, // index[291] ALERT_HANDLER_CLASSB_CLR_SHADOWED
-    4'b 0011, // index[292] ALERT_HANDLER_CLASSB_ACCUM_CNT
-    4'b 0011, // index[293] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[294] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[295] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[296] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[297] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[298] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[299] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[300] ALERT_HANDLER_CLASSB_ESC_CNT
-    4'b 0001, // index[301] ALERT_HANDLER_CLASSB_STATE
-    4'b 0001, // index[302] ALERT_HANDLER_CLASSC_REGWEN
-    4'b 0011, // index[303] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
-    4'b 0001, // index[304] ALERT_HANDLER_CLASSC_CLR_REGWEN
-    4'b 0001, // index[305] ALERT_HANDLER_CLASSC_CLR_SHADOWED
-    4'b 0011, // index[306] ALERT_HANDLER_CLASSC_ACCUM_CNT
-    4'b 0011, // index[307] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[308] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[309] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[310] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[311] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[312] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[313] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[314] ALERT_HANDLER_CLASSC_ESC_CNT
-    4'b 0001, // index[315] ALERT_HANDLER_CLASSC_STATE
-    4'b 0001, // index[316] ALERT_HANDLER_CLASSD_REGWEN
-    4'b 0011, // index[317] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
-    4'b 0001, // index[318] ALERT_HANDLER_CLASSD_CLR_REGWEN
-    4'b 0001, // index[319] ALERT_HANDLER_CLASSD_CLR_SHADOWED
-    4'b 0011, // index[320] ALERT_HANDLER_CLASSD_ACCUM_CNT
-    4'b 0011, // index[321] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
-    4'b 1111, // index[322] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
-    4'b 0001, // index[323] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
-    4'b 1111, // index[324] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
-    4'b 1111, // index[325] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
-    4'b 1111, // index[326] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
-    4'b 1111, // index[327] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
-    4'b 1111, // index[328] ALERT_HANDLER_CLASSD_ESC_CNT
-    4'b 0001  // index[329] ALERT_HANDLER_CLASSD_STATE
+    4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_SHADOWED_0
+    4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_SHADOWED_1
+    4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_SHADOWED_2
+    4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_SHADOWED_3
+    4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_SHADOWED_4
+    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_5
+    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_6
+    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_7
+    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_8
+    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_9
+    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_10
+    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_11
+    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_12
+    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_13
+    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_14
+    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_15
+    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_16
+    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_17
+    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_18
+    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_19
+    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_20
+    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_21
+    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_22
+    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_23
+    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_24
+    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_25
+    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_26
+    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_27
+    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_28
+    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_29
+    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_30
+    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_31
+    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_32
+    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_33
+    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_34
+    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_35
+    4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_36
+    4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_37
+    4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_38
+    4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_39
+    4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_40
+    4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_41
+    4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_42
+    4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_43
+    4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_44
+    4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_45
+    4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_46
+    4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_47
+    4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_48
+    4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_49
+    4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_50
+    4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_51
+    4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_52
+    4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_53
+    4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_54
+    4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_55
+    4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_56
+    4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_57
+    4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
+    4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
+    4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
+    4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
+    4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
+    4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
+    4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
+    4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
+    4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
+    4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
+    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
+    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
+    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
+    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
+    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
+    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
+    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
+    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
+    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
+    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
+    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
+    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
+    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
+    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
+    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
+    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
+    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
+    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
+    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
+    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
+    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
+    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
+    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
+    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
+    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
+    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
+    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
+    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
+    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
+    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
+    4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
+    4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
+    4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
+    4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
+    4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
+    4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
+    4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
+    4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
+    4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
+    4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
+    4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
+    4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
+    4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
+    4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
+    4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
+    4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
+    4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
+    4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
+    4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_0
+    4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_1
+    4'b 0001, // index[182] ALERT_HANDLER_ALERT_CAUSE_2
+    4'b 0001, // index[183] ALERT_HANDLER_ALERT_CAUSE_3
+    4'b 0001, // index[184] ALERT_HANDLER_ALERT_CAUSE_4
+    4'b 0001, // index[185] ALERT_HANDLER_ALERT_CAUSE_5
+    4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_6
+    4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_7
+    4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_8
+    4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_9
+    4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_10
+    4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_11
+    4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_12
+    4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_13
+    4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_14
+    4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_15
+    4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_16
+    4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_17
+    4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_18
+    4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_19
+    4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_20
+    4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_21
+    4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_22
+    4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_23
+    4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_24
+    4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_25
+    4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_26
+    4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_27
+    4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_28
+    4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_29
+    4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_30
+    4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_31
+    4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_32
+    4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_33
+    4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_34
+    4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_35
+    4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_36
+    4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_37
+    4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_38
+    4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_39
+    4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_40
+    4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_41
+    4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_42
+    4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_43
+    4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_44
+    4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_45
+    4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_46
+    4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_47
+    4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_48
+    4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_49
+    4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_50
+    4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_51
+    4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_52
+    4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_53
+    4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_54
+    4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_55
+    4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_56
+    4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_57
+    4'b 0001, // index[238] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+    4'b 0001, // index[239] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+    4'b 0001, // index[240] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+    4'b 0001, // index[241] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+    4'b 0001, // index[242] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+    4'b 0001, // index[243] ALERT_HANDLER_LOC_ALERT_REGWEN_5
+    4'b 0001, // index[244] ALERT_HANDLER_LOC_ALERT_REGWEN_6
+    4'b 0001, // index[245] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
+    4'b 0001, // index[246] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
+    4'b 0001, // index[247] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
+    4'b 0001, // index[248] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
+    4'b 0001, // index[249] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
+    4'b 0001, // index[250] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
+    4'b 0001, // index[251] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
+    4'b 0001, // index[252] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
+    4'b 0001, // index[253] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
+    4'b 0001, // index[254] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
+    4'b 0001, // index[255] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
+    4'b 0001, // index[256] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
+    4'b 0001, // index[257] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
+    4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
+    4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+    4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+    4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+    4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+    4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+    4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_CAUSE_5
+    4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_CAUSE_6
+    4'b 0001, // index[266] ALERT_HANDLER_CLASSA_REGWEN
+    4'b 0011, // index[267] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
+    4'b 0001, // index[268] ALERT_HANDLER_CLASSA_CLR_REGWEN
+    4'b 0001, // index[269] ALERT_HANDLER_CLASSA_CLR_SHADOWED
+    4'b 0011, // index[270] ALERT_HANDLER_CLASSA_ACCUM_CNT
+    4'b 0011, // index[271] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[272] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[273] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[274] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[275] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[276] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[277] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[278] ALERT_HANDLER_CLASSA_ESC_CNT
+    4'b 0001, // index[279] ALERT_HANDLER_CLASSA_STATE
+    4'b 0001, // index[280] ALERT_HANDLER_CLASSB_REGWEN
+    4'b 0011, // index[281] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
+    4'b 0001, // index[282] ALERT_HANDLER_CLASSB_CLR_REGWEN
+    4'b 0001, // index[283] ALERT_HANDLER_CLASSB_CLR_SHADOWED
+    4'b 0011, // index[284] ALERT_HANDLER_CLASSB_ACCUM_CNT
+    4'b 0011, // index[285] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[286] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[287] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[288] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[289] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[290] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[291] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[292] ALERT_HANDLER_CLASSB_ESC_CNT
+    4'b 0001, // index[293] ALERT_HANDLER_CLASSB_STATE
+    4'b 0001, // index[294] ALERT_HANDLER_CLASSC_REGWEN
+    4'b 0011, // index[295] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
+    4'b 0001, // index[296] ALERT_HANDLER_CLASSC_CLR_REGWEN
+    4'b 0001, // index[297] ALERT_HANDLER_CLASSC_CLR_SHADOWED
+    4'b 0011, // index[298] ALERT_HANDLER_CLASSC_ACCUM_CNT
+    4'b 0011, // index[299] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[300] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[301] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[302] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[303] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[304] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[305] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[306] ALERT_HANDLER_CLASSC_ESC_CNT
+    4'b 0001, // index[307] ALERT_HANDLER_CLASSC_STATE
+    4'b 0001, // index[308] ALERT_HANDLER_CLASSD_REGWEN
+    4'b 0011, // index[309] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
+    4'b 0001, // index[310] ALERT_HANDLER_CLASSD_CLR_REGWEN
+    4'b 0001, // index[311] ALERT_HANDLER_CLASSD_CLR_SHADOWED
+    4'b 0011, // index[312] ALERT_HANDLER_CLASSD_ACCUM_CNT
+    4'b 0011, // index[313] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
+    4'b 1111, // index[314] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
+    4'b 0001, // index[315] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
+    4'b 1111, // index[316] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
+    4'b 1111, // index[317] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
+    4'b 1111, // index[318] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
+    4'b 1111, // index[319] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
+    4'b 1111, // index[320] ALERT_HANDLER_CLASSD_ESC_CNT
+    4'b 0001  // index[321] ALERT_HANDLER_CLASSD_STATE
   };
 
 endpackage

diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index b4bd3f7..c973f17 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv

@@ -317,12 +317,6 @@
   logic alert_regwen_57_we;
   logic alert_regwen_57_qs;
   logic alert_regwen_57_wd;
-  logic alert_regwen_58_we;
-  logic alert_regwen_58_qs;
-  logic alert_regwen_58_wd;
-  logic alert_regwen_59_we;
-  logic alert_regwen_59_qs;
-  logic alert_regwen_59_wd;
   logic alert_en_shadowed_0_re;
   logic alert_en_shadowed_0_we;
   logic alert_en_shadowed_0_qs;
@@ -555,14 +549,6 @@
   logic alert_en_shadowed_57_we;
   logic alert_en_shadowed_57_qs;
   logic alert_en_shadowed_57_wd;
-  logic alert_en_shadowed_58_re;
-  logic alert_en_shadowed_58_we;
-  logic alert_en_shadowed_58_qs;
-  logic alert_en_shadowed_58_wd;
-  logic alert_en_shadowed_59_re;
-  logic alert_en_shadowed_59_we;
-  logic alert_en_shadowed_59_qs;
-  logic alert_en_shadowed_59_wd;
   logic alert_class_shadowed_0_re;
   logic alert_class_shadowed_0_we;
   logic [1:0] alert_class_shadowed_0_qs;
@@ -795,14 +781,6 @@
   logic alert_class_shadowed_57_we;
   logic [1:0] alert_class_shadowed_57_qs;
   logic [1:0] alert_class_shadowed_57_wd;
-  logic alert_class_shadowed_58_re;
-  logic alert_class_shadowed_58_we;
-  logic [1:0] alert_class_shadowed_58_qs;
-  logic [1:0] alert_class_shadowed_58_wd;
-  logic alert_class_shadowed_59_re;
-  logic alert_class_shadowed_59_we;
-  logic [1:0] alert_class_shadowed_59_qs;
-  logic [1:0] alert_class_shadowed_59_wd;
   logic alert_cause_0_we;
   logic alert_cause_0_qs;
   logic alert_cause_0_wd;
@@ -977,12 +955,6 @@
   logic alert_cause_57_we;
   logic alert_cause_57_qs;
   logic alert_cause_57_wd;
-  logic alert_cause_58_we;
-  logic alert_cause_58_qs;
-  logic alert_cause_58_wd;
-  logic alert_cause_59_we;
-  logic alert_cause_59_qs;
-  logic alert_cause_59_wd;
   logic loc_alert_regwen_0_we;
   logic loc_alert_regwen_0_qs;
   logic loc_alert_regwen_0_wd;
@@ -3265,60 +3237,6 @@
   );
 
 
-  // Subregister 58 of Multireg alert_regwen
-  // R[alert_regwen_58]: V(False)
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
-    .RESVAL  (1'h1)
-  ) u_alert_regwen_58 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (alert_regwen_58_we),
-    .wd     (alert_regwen_58_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_regwen[58].q),
-
-    // to register interface (read)
-    .qs     (alert_regwen_58_qs)
-  );
-
-
-  // Subregister 59 of Multireg alert_regwen
-  // R[alert_regwen_59]: V(False)
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
-    .RESVAL  (1'h1)
-  ) u_alert_regwen_59 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (alert_regwen_59_we),
-    .wd     (alert_regwen_59_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_regwen[59].q),
-
-    // to register interface (read)
-    .qs     (alert_regwen_59_qs)
-  );
-
-
   // Subregister 0 of Multireg alert_en_shadowed
   // R[alert_en_shadowed_0]: V(False)
   prim_subreg_shadow #(
@@ -5233,72 +5151,6 @@
   );
 
 
-  // Subregister 58 of Multireg alert_en_shadowed
-  // R[alert_en_shadowed_58]: V(False)
-  prim_subreg_shadow #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_alert_en_shadowed_58 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-    .rst_shadowed_ni (rst_shadowed_ni),
-
-    // from register interface
-    .re     (alert_en_shadowed_58_re),
-    .we     (alert_en_shadowed_58_we & alert_regwen_58_qs),
-    .wd     (alert_en_shadowed_58_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_en_shadowed[58].q),
-
-    // to register interface (read)
-    .qs     (alert_en_shadowed_58_qs),
-
-    // Shadow register error conditions
-    .err_update  (reg2hw.alert_en_shadowed[58].err_update),
-    .err_storage (reg2hw.alert_en_shadowed[58].err_storage)
-  );
-
-
-  // Subregister 59 of Multireg alert_en_shadowed
-  // R[alert_en_shadowed_59]: V(False)
-  prim_subreg_shadow #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_alert_en_shadowed_59 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-    .rst_shadowed_ni (rst_shadowed_ni),
-
-    // from register interface
-    .re     (alert_en_shadowed_59_re),
-    .we     (alert_en_shadowed_59_we & alert_regwen_59_qs),
-    .wd     (alert_en_shadowed_59_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_en_shadowed[59].q),
-
-    // to register interface (read)
-    .qs     (alert_en_shadowed_59_qs),
-
-    // Shadow register error conditions
-    .err_update  (reg2hw.alert_en_shadowed[59].err_update),
-    .err_storage (reg2hw.alert_en_shadowed[59].err_storage)
-  );
-
-
   // Subregister 0 of Multireg alert_class_shadowed
   // R[alert_class_shadowed_0]: V(False)
   prim_subreg_shadow #(
@@ -7213,72 +7065,6 @@
   );
 
 
-  // Subregister 58 of Multireg alert_class_shadowed
-  // R[alert_class_shadowed_58]: V(False)
-  prim_subreg_shadow #(
-    .DW      (2),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (2'h0)
-  ) u_alert_class_shadowed_58 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-    .rst_shadowed_ni (rst_shadowed_ni),
-
-    // from register interface
-    .re     (alert_class_shadowed_58_re),
-    .we     (alert_class_shadowed_58_we & alert_regwen_58_qs),
-    .wd     (alert_class_shadowed_58_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_class_shadowed[58].q),
-
-    // to register interface (read)
-    .qs     (alert_class_shadowed_58_qs),
-
-    // Shadow register error conditions
-    .err_update  (reg2hw.alert_class_shadowed[58].err_update),
-    .err_storage (reg2hw.alert_class_shadowed[58].err_storage)
-  );
-
-
-  // Subregister 59 of Multireg alert_class_shadowed
-  // R[alert_class_shadowed_59]: V(False)
-  prim_subreg_shadow #(
-    .DW      (2),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (2'h0)
-  ) u_alert_class_shadowed_59 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-    .rst_shadowed_ni (rst_shadowed_ni),
-
-    // from register interface
-    .re     (alert_class_shadowed_59_re),
-    .we     (alert_class_shadowed_59_we & alert_regwen_59_qs),
-    .wd     (alert_class_shadowed_59_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_class_shadowed[59].q),
-
-    // to register interface (read)
-    .qs     (alert_class_shadowed_59_qs),
-
-    // Shadow register error conditions
-    .err_update  (reg2hw.alert_class_shadowed[59].err_update),
-    .err_storage (reg2hw.alert_class_shadowed[59].err_storage)
-  );
-
-
   // Subregister 0 of Multireg alert_cause
   // R[alert_cause_0]: V(False)
   prim_subreg #(
@@ -8845,60 +8631,6 @@
   );
 
 
-  // Subregister 58 of Multireg alert_cause
-  // R[alert_cause_58]: V(False)
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
-    .RESVAL  (1'h0)
-  ) u_alert_cause_58 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (alert_cause_58_we),
-    .wd     (alert_cause_58_wd),
-
-    // from internal hardware
-    .de     (hw2reg.alert_cause[58].de),
-    .d      (hw2reg.alert_cause[58].d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_cause[58].q),
-
-    // to register interface (read)
-    .qs     (alert_cause_58_qs)
-  );
-
-
-  // Subregister 59 of Multireg alert_cause
-  // R[alert_cause_59]: V(False)
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
-    .RESVAL  (1'h0)
-  ) u_alert_cause_59 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (alert_cause_59_we),
-    .wd     (alert_cause_59_wd),
-
-    // from internal hardware
-    .de     (hw2reg.alert_cause[59].de),
-    .d      (hw2reg.alert_cause[59].d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.alert_cause[59].q),
-
-    // to register interface (read)
-    .qs     (alert_cause_59_qs)
-  );
-
-
   // Subregister 0 of Multireg loc_alert_regwen
   // R[loc_alert_regwen_0]: V(False)
   prim_subreg #(
@@ -12400,7 +12132,7 @@
 
 
 
-  logic [329:0] addr_hit;
+  logic [321:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -12467,272 +12199,264 @@
     addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_55_OFFSET);
     addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_56_OFFSET);
     addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET);
-    addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET);
-    addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_59_OFFSET);
-    addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
-    addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
-    addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
-    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
-    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
-    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
-    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
-    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
-    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
-    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
-    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
-    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
-    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
-    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
-    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
-    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
-    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
-    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
-    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
-    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
-    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
-    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
-    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
-    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
-    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
-    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
-    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
-    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
-    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
-    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
-    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
-    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
-    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
-    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
-    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
-    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
-    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
-    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
-    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
-    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
-    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
-    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
-    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
-    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
-    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
-    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
-    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
-    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
-    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
-    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
-    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
-    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
-    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
-    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
-    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
-    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
-    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
-    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
-    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
-    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
-    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
-    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
-    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
-    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
-    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
-    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
-    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
-    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
-    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
-    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
-    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
-    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
-    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
-    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
-    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
-    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
-    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
-    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
-    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
-    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
-    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
-    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
-    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
-    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
-    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
-    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
-    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
-    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
-    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
-    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
-    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
-    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
-    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
-    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
-    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
-    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
-    addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
-    addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
-    addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
-    addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
-    addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
-    addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
-    addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
-    addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
-    addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
-    addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
-    addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
-    addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
-    addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
-    addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
-    addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
-    addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
-    addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
-    addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
-    addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
-    addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
-    addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
-    addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
-    addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
-    addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
-    addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
-    addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
-    addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
-    addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
-    addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
-    addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
-    addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
-    addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
-    addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
-    addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
-    addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
-    addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
-    addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
-    addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
-    addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
-    addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
-    addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
-    addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
-    addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
-    addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
-    addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
-    addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
-    addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
-    addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
-    addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
-    addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
-    addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
-    addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
-    addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
-    addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
-    addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
-    addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
-    addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
-    addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
-    addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
-    addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
-    addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
-    addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
-    addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
-    addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
-    addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
-    addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
-    addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
-    addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
-    addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
-    addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
-    addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
-    addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
-    addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
-    addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
-    addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
-    addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
-    addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
-    addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
-    addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
-    addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
-    addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
-    addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
-    addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
-    addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
-    addr_hit[246] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
-    addr_hit[247] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
-    addr_hit[248] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
-    addr_hit[249] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
-    addr_hit[250] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
-    addr_hit[251] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
-    addr_hit[252] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
-    addr_hit[253] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
-    addr_hit[254] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
-    addr_hit[255] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
-    addr_hit[256] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
-    addr_hit[257] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
-    addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
-    addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
-    addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
-    addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
-    addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
-    addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
-    addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
-    addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
-    addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
-    addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
-    addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
-    addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
-    addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
-    addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
-    addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
-    addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
-    addr_hit[274] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
-    addr_hit[275] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
-    addr_hit[276] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
-    addr_hit[277] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
-    addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
-    addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[282] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[283] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[284] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[285] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
-    addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
-    addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
-    addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
-    addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
-    addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
-    addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
-    addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
-    addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
-    addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
-    addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
-    addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
-    addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
-    addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
-    addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
-    addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
-    addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
-    addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
-    addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
-    addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
-    addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
-    addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
-    addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
-    addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
-    addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
-    addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
-    addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
-    addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
-    addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
-    addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+    addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
+    addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
+    addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
+    addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
+    addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
+    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
+    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
+    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
+    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
+    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
+    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
+    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
+    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
+    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
+    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
+    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
+    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
+    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
+    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
+    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
+    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
+    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
+    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
+    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
+    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
+    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
+    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
+    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
+    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
+    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
+    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
+    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
+    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
+    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
+    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
+    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
+    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
+    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
+    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
+    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
+    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
+    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
+    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
+    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
+    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
+    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
+    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
+    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
+    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
+    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
+    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
+    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
+    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
+    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
+    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
+    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
+    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
+    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
+    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
+    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
+    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
+    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
+    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
+    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
+    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
+    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
+    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
+    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
+    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
+    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
+    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
+    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
+    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
+    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
+    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
+    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
+    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
+    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
+    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
+    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
+    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
+    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
+    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
+    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
+    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
+    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
+    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
+    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
+    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
+    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
+    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
+    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
+    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
+    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
+    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
+    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
+    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
+    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
+    addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
+    addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
+    addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
+    addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
+    addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
+    addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
+    addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
+    addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
+    addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
+    addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
+    addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
+    addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
+    addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
+    addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
+    addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
+    addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
+    addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
+    addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
+    addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+    addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+    addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+    addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+    addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+    addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+    addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+    addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+    addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+    addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+    addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+    addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+    addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+    addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+    addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+    addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+    addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+    addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+    addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+    addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+    addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+    addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+    addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+    addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+    addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+    addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+    addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+    addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+    addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+    addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+    addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+    addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+    addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+    addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+    addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+    addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+    addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+    addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+    addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+    addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+    addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+    addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+    addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+    addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+    addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+    addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+    addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+    addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+    addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
+    addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
+    addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
+    addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
+    addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
+    addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
+    addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
+    addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
+    addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
+    addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
+    addr_hit[238] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+    addr_hit[239] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+    addr_hit[240] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+    addr_hit[241] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+    addr_hit[242] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+    addr_hit[243] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
+    addr_hit[244] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
+    addr_hit[245] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
+    addr_hit[246] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
+    addr_hit[247] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
+    addr_hit[248] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
+    addr_hit[249] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
+    addr_hit[250] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
+    addr_hit[251] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
+    addr_hit[252] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
+    addr_hit[253] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
+    addr_hit[254] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
+    addr_hit[255] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
+    addr_hit[256] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
+    addr_hit[257] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
+    addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
+    addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+    addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+    addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+    addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+    addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+    addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
+    addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
+    addr_hit[266] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+    addr_hit[267] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
+    addr_hit[268] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+    addr_hit[269] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
+    addr_hit[270] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+    addr_hit[271] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[272] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[273] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[274] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[275] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[276] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[277] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+    addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+    addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+    addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
+    addr_hit[282] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+    addr_hit[283] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
+    addr_hit[284] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+    addr_hit[285] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+    addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+    addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+    addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
+    addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+    addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
+    addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+    addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+    addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+    addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+    addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
+    addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+    addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
+    addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+    addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
+    addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
+    addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+    addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
+    addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
+    addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
+    addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
+    addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+    addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -13061,15 +12785,7 @@
                (addr_hit[318] & (|(ALERT_HANDLER_PERMIT[318] & ~reg_be))) |
                (addr_hit[319] & (|(ALERT_HANDLER_PERMIT[319] & ~reg_be))) |
                (addr_hit[320] & (|(ALERT_HANDLER_PERMIT[320] & ~reg_be))) |
-               (addr_hit[321] & (|(ALERT_HANDLER_PERMIT[321] & ~reg_be))) |
-               (addr_hit[322] & (|(ALERT_HANDLER_PERMIT[322] & ~reg_be))) |
-               (addr_hit[323] & (|(ALERT_HANDLER_PERMIT[323] & ~reg_be))) |
-               (addr_hit[324] & (|(ALERT_HANDLER_PERMIT[324] & ~reg_be))) |
-               (addr_hit[325] & (|(ALERT_HANDLER_PERMIT[325] & ~reg_be))) |
-               (addr_hit[326] & (|(ALERT_HANDLER_PERMIT[326] & ~reg_be))) |
-               (addr_hit[327] & (|(ALERT_HANDLER_PERMIT[327] & ~reg_be))) |
-               (addr_hit[328] & (|(ALERT_HANDLER_PERMIT[328] & ~reg_be))) |
-               (addr_hit[329] & (|(ALERT_HANDLER_PERMIT[329] & ~reg_be)))));
+               (addr_hit[321] & (|(ALERT_HANDLER_PERMIT[321] & ~reg_be)))));
   end
   assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
 
@@ -13283,775 +12999,747 @@
   assign alert_regwen_57_we = addr_hit[63] & reg_we & !reg_error;
 
   assign alert_regwen_57_wd = reg_wdata[0];
-  assign alert_regwen_58_we = addr_hit[64] & reg_we & !reg_error;
-
-  assign alert_regwen_58_wd = reg_wdata[0];
-  assign alert_regwen_59_we = addr_hit[65] & reg_we & !reg_error;
-
-  assign alert_regwen_59_wd = reg_wdata[0];
-  assign alert_en_shadowed_0_re = addr_hit[66] & reg_re & !reg_error;
-  assign alert_en_shadowed_0_we = addr_hit[66] & reg_we & !reg_error;
+  assign alert_en_shadowed_0_re = addr_hit[64] & reg_re & !reg_error;
+  assign alert_en_shadowed_0_we = addr_hit[64] & reg_we & !reg_error;
 
   assign alert_en_shadowed_0_wd = reg_wdata[0];
-  assign alert_en_shadowed_1_re = addr_hit[67] & reg_re & !reg_error;
-  assign alert_en_shadowed_1_we = addr_hit[67] & reg_we & !reg_error;
+  assign alert_en_shadowed_1_re = addr_hit[65] & reg_re & !reg_error;
+  assign alert_en_shadowed_1_we = addr_hit[65] & reg_we & !reg_error;
 
   assign alert_en_shadowed_1_wd = reg_wdata[0];
-  assign alert_en_shadowed_2_re = addr_hit[68] & reg_re & !reg_error;
-  assign alert_en_shadowed_2_we = addr_hit[68] & reg_we & !reg_error;
+  assign alert_en_shadowed_2_re = addr_hit[66] & reg_re & !reg_error;
+  assign alert_en_shadowed_2_we = addr_hit[66] & reg_we & !reg_error;
 
   assign alert_en_shadowed_2_wd = reg_wdata[0];
-  assign alert_en_shadowed_3_re = addr_hit[69] & reg_re & !reg_error;
-  assign alert_en_shadowed_3_we = addr_hit[69] & reg_we & !reg_error;
+  assign alert_en_shadowed_3_re = addr_hit[67] & reg_re & !reg_error;
+  assign alert_en_shadowed_3_we = addr_hit[67] & reg_we & !reg_error;
 
   assign alert_en_shadowed_3_wd = reg_wdata[0];
-  assign alert_en_shadowed_4_re = addr_hit[70] & reg_re & !reg_error;
-  assign alert_en_shadowed_4_we = addr_hit[70] & reg_we & !reg_error;
+  assign alert_en_shadowed_4_re = addr_hit[68] & reg_re & !reg_error;
+  assign alert_en_shadowed_4_we = addr_hit[68] & reg_we & !reg_error;
 
   assign alert_en_shadowed_4_wd = reg_wdata[0];
-  assign alert_en_shadowed_5_re = addr_hit[71] & reg_re & !reg_error;
-  assign alert_en_shadowed_5_we = addr_hit[71] & reg_we & !reg_error;
+  assign alert_en_shadowed_5_re = addr_hit[69] & reg_re & !reg_error;
+  assign alert_en_shadowed_5_we = addr_hit[69] & reg_we & !reg_error;
 
   assign alert_en_shadowed_5_wd = reg_wdata[0];
-  assign alert_en_shadowed_6_re = addr_hit[72] & reg_re & !reg_error;
-  assign alert_en_shadowed_6_we = addr_hit[72] & reg_we & !reg_error;
+  assign alert_en_shadowed_6_re = addr_hit[70] & reg_re & !reg_error;
+  assign alert_en_shadowed_6_we = addr_hit[70] & reg_we & !reg_error;
 
   assign alert_en_shadowed_6_wd = reg_wdata[0];
-  assign alert_en_shadowed_7_re = addr_hit[73] & reg_re & !reg_error;
-  assign alert_en_shadowed_7_we = addr_hit[73] & reg_we & !reg_error;
+  assign alert_en_shadowed_7_re = addr_hit[71] & reg_re & !reg_error;
+  assign alert_en_shadowed_7_we = addr_hit[71] & reg_we & !reg_error;
 
   assign alert_en_shadowed_7_wd = reg_wdata[0];
-  assign alert_en_shadowed_8_re = addr_hit[74] & reg_re & !reg_error;
-  assign alert_en_shadowed_8_we = addr_hit[74] & reg_we & !reg_error;
+  assign alert_en_shadowed_8_re = addr_hit[72] & reg_re & !reg_error;
+  assign alert_en_shadowed_8_we = addr_hit[72] & reg_we & !reg_error;
 
   assign alert_en_shadowed_8_wd = reg_wdata[0];
-  assign alert_en_shadowed_9_re = addr_hit[75] & reg_re & !reg_error;
-  assign alert_en_shadowed_9_we = addr_hit[75] & reg_we & !reg_error;
+  assign alert_en_shadowed_9_re = addr_hit[73] & reg_re & !reg_error;
+  assign alert_en_shadowed_9_we = addr_hit[73] & reg_we & !reg_error;
 
   assign alert_en_shadowed_9_wd = reg_wdata[0];
-  assign alert_en_shadowed_10_re = addr_hit[76] & reg_re & !reg_error;
-  assign alert_en_shadowed_10_we = addr_hit[76] & reg_we & !reg_error;
+  assign alert_en_shadowed_10_re = addr_hit[74] & reg_re & !reg_error;
+  assign alert_en_shadowed_10_we = addr_hit[74] & reg_we & !reg_error;
 
   assign alert_en_shadowed_10_wd = reg_wdata[0];
-  assign alert_en_shadowed_11_re = addr_hit[77] & reg_re & !reg_error;
-  assign alert_en_shadowed_11_we = addr_hit[77] & reg_we & !reg_error;
+  assign alert_en_shadowed_11_re = addr_hit[75] & reg_re & !reg_error;
+  assign alert_en_shadowed_11_we = addr_hit[75] & reg_we & !reg_error;
 
   assign alert_en_shadowed_11_wd = reg_wdata[0];
-  assign alert_en_shadowed_12_re = addr_hit[78] & reg_re & !reg_error;
-  assign alert_en_shadowed_12_we = addr_hit[78] & reg_we & !reg_error;
+  assign alert_en_shadowed_12_re = addr_hit[76] & reg_re & !reg_error;
+  assign alert_en_shadowed_12_we = addr_hit[76] & reg_we & !reg_error;
 
   assign alert_en_shadowed_12_wd = reg_wdata[0];
-  assign alert_en_shadowed_13_re = addr_hit[79] & reg_re & !reg_error;
-  assign alert_en_shadowed_13_we = addr_hit[79] & reg_we & !reg_error;
+  assign alert_en_shadowed_13_re = addr_hit[77] & reg_re & !reg_error;
+  assign alert_en_shadowed_13_we = addr_hit[77] & reg_we & !reg_error;
 
   assign alert_en_shadowed_13_wd = reg_wdata[0];
-  assign alert_en_shadowed_14_re = addr_hit[80] & reg_re & !reg_error;
-  assign alert_en_shadowed_14_we = addr_hit[80] & reg_we & !reg_error;
+  assign alert_en_shadowed_14_re = addr_hit[78] & reg_re & !reg_error;
+  assign alert_en_shadowed_14_we = addr_hit[78] & reg_we & !reg_error;
 
   assign alert_en_shadowed_14_wd = reg_wdata[0];
-  assign alert_en_shadowed_15_re = addr_hit[81] & reg_re & !reg_error;
-  assign alert_en_shadowed_15_we = addr_hit[81] & reg_we & !reg_error;
+  assign alert_en_shadowed_15_re = addr_hit[79] & reg_re & !reg_error;
+  assign alert_en_shadowed_15_we = addr_hit[79] & reg_we & !reg_error;
 
   assign alert_en_shadowed_15_wd = reg_wdata[0];
-  assign alert_en_shadowed_16_re = addr_hit[82] & reg_re & !reg_error;
-  assign alert_en_shadowed_16_we = addr_hit[82] & reg_we & !reg_error;
+  assign alert_en_shadowed_16_re = addr_hit[80] & reg_re & !reg_error;
+  assign alert_en_shadowed_16_we = addr_hit[80] & reg_we & !reg_error;
 
   assign alert_en_shadowed_16_wd = reg_wdata[0];
-  assign alert_en_shadowed_17_re = addr_hit[83] & reg_re & !reg_error;
-  assign alert_en_shadowed_17_we = addr_hit[83] & reg_we & !reg_error;
+  assign alert_en_shadowed_17_re = addr_hit[81] & reg_re & !reg_error;
+  assign alert_en_shadowed_17_we = addr_hit[81] & reg_we & !reg_error;
 
   assign alert_en_shadowed_17_wd = reg_wdata[0];
-  assign alert_en_shadowed_18_re = addr_hit[84] & reg_re & !reg_error;
-  assign alert_en_shadowed_18_we = addr_hit[84] & reg_we & !reg_error;
+  assign alert_en_shadowed_18_re = addr_hit[82] & reg_re & !reg_error;
+  assign alert_en_shadowed_18_we = addr_hit[82] & reg_we & !reg_error;
 
   assign alert_en_shadowed_18_wd = reg_wdata[0];
-  assign alert_en_shadowed_19_re = addr_hit[85] & reg_re & !reg_error;
-  assign alert_en_shadowed_19_we = addr_hit[85] & reg_we & !reg_error;
+  assign alert_en_shadowed_19_re = addr_hit[83] & reg_re & !reg_error;
+  assign alert_en_shadowed_19_we = addr_hit[83] & reg_we & !reg_error;
 
   assign alert_en_shadowed_19_wd = reg_wdata[0];
-  assign alert_en_shadowed_20_re = addr_hit[86] & reg_re & !reg_error;
-  assign alert_en_shadowed_20_we = addr_hit[86] & reg_we & !reg_error;
+  assign alert_en_shadowed_20_re = addr_hit[84] & reg_re & !reg_error;
+  assign alert_en_shadowed_20_we = addr_hit[84] & reg_we & !reg_error;
 
   assign alert_en_shadowed_20_wd = reg_wdata[0];
-  assign alert_en_shadowed_21_re = addr_hit[87] & reg_re & !reg_error;
-  assign alert_en_shadowed_21_we = addr_hit[87] & reg_we & !reg_error;
+  assign alert_en_shadowed_21_re = addr_hit[85] & reg_re & !reg_error;
+  assign alert_en_shadowed_21_we = addr_hit[85] & reg_we & !reg_error;
 
   assign alert_en_shadowed_21_wd = reg_wdata[0];
-  assign alert_en_shadowed_22_re = addr_hit[88] & reg_re & !reg_error;
-  assign alert_en_shadowed_22_we = addr_hit[88] & reg_we & !reg_error;
+  assign alert_en_shadowed_22_re = addr_hit[86] & reg_re & !reg_error;
+  assign alert_en_shadowed_22_we = addr_hit[86] & reg_we & !reg_error;
 
   assign alert_en_shadowed_22_wd = reg_wdata[0];
-  assign alert_en_shadowed_23_re = addr_hit[89] & reg_re & !reg_error;
-  assign alert_en_shadowed_23_we = addr_hit[89] & reg_we & !reg_error;
+  assign alert_en_shadowed_23_re = addr_hit[87] & reg_re & !reg_error;
+  assign alert_en_shadowed_23_we = addr_hit[87] & reg_we & !reg_error;
 
   assign alert_en_shadowed_23_wd = reg_wdata[0];
-  assign alert_en_shadowed_24_re = addr_hit[90] & reg_re & !reg_error;
-  assign alert_en_shadowed_24_we = addr_hit[90] & reg_we & !reg_error;
+  assign alert_en_shadowed_24_re = addr_hit[88] & reg_re & !reg_error;
+  assign alert_en_shadowed_24_we = addr_hit[88] & reg_we & !reg_error;
 
   assign alert_en_shadowed_24_wd = reg_wdata[0];
-  assign alert_en_shadowed_25_re = addr_hit[91] & reg_re & !reg_error;
-  assign alert_en_shadowed_25_we = addr_hit[91] & reg_we & !reg_error;
+  assign alert_en_shadowed_25_re = addr_hit[89] & reg_re & !reg_error;
+  assign alert_en_shadowed_25_we = addr_hit[89] & reg_we & !reg_error;
 
   assign alert_en_shadowed_25_wd = reg_wdata[0];
-  assign alert_en_shadowed_26_re = addr_hit[92] & reg_re & !reg_error;
-  assign alert_en_shadowed_26_we = addr_hit[92] & reg_we & !reg_error;
+  assign alert_en_shadowed_26_re = addr_hit[90] & reg_re & !reg_error;
+  assign alert_en_shadowed_26_we = addr_hit[90] & reg_we & !reg_error;
 
   assign alert_en_shadowed_26_wd = reg_wdata[0];
-  assign alert_en_shadowed_27_re = addr_hit[93] & reg_re & !reg_error;
-  assign alert_en_shadowed_27_we = addr_hit[93] & reg_we & !reg_error;
+  assign alert_en_shadowed_27_re = addr_hit[91] & reg_re & !reg_error;
+  assign alert_en_shadowed_27_we = addr_hit[91] & reg_we & !reg_error;
 
   assign alert_en_shadowed_27_wd = reg_wdata[0];
-  assign alert_en_shadowed_28_re = addr_hit[94] & reg_re & !reg_error;
-  assign alert_en_shadowed_28_we = addr_hit[94] & reg_we & !reg_error;
+  assign alert_en_shadowed_28_re = addr_hit[92] & reg_re & !reg_error;
+  assign alert_en_shadowed_28_we = addr_hit[92] & reg_we & !reg_error;
 
   assign alert_en_shadowed_28_wd = reg_wdata[0];
-  assign alert_en_shadowed_29_re = addr_hit[95] & reg_re & !reg_error;
-  assign alert_en_shadowed_29_we = addr_hit[95] & reg_we & !reg_error;
+  assign alert_en_shadowed_29_re = addr_hit[93] & reg_re & !reg_error;
+  assign alert_en_shadowed_29_we = addr_hit[93] & reg_we & !reg_error;
 
   assign alert_en_shadowed_29_wd = reg_wdata[0];
-  assign alert_en_shadowed_30_re = addr_hit[96] & reg_re & !reg_error;
-  assign alert_en_shadowed_30_we = addr_hit[96] & reg_we & !reg_error;
+  assign alert_en_shadowed_30_re = addr_hit[94] & reg_re & !reg_error;
+  assign alert_en_shadowed_30_we = addr_hit[94] & reg_we & !reg_error;
 
   assign alert_en_shadowed_30_wd = reg_wdata[0];
-  assign alert_en_shadowed_31_re = addr_hit[97] & reg_re & !reg_error;
-  assign alert_en_shadowed_31_we = addr_hit[97] & reg_we & !reg_error;
+  assign alert_en_shadowed_31_re = addr_hit[95] & reg_re & !reg_error;
+  assign alert_en_shadowed_31_we = addr_hit[95] & reg_we & !reg_error;
 
   assign alert_en_shadowed_31_wd = reg_wdata[0];
-  assign alert_en_shadowed_32_re = addr_hit[98] & reg_re & !reg_error;
-  assign alert_en_shadowed_32_we = addr_hit[98] & reg_we & !reg_error;
+  assign alert_en_shadowed_32_re = addr_hit[96] & reg_re & !reg_error;
+  assign alert_en_shadowed_32_we = addr_hit[96] & reg_we & !reg_error;
 
   assign alert_en_shadowed_32_wd = reg_wdata[0];
-  assign alert_en_shadowed_33_re = addr_hit[99] & reg_re & !reg_error;
-  assign alert_en_shadowed_33_we = addr_hit[99] & reg_we & !reg_error;
+  assign alert_en_shadowed_33_re = addr_hit[97] & reg_re & !reg_error;
+  assign alert_en_shadowed_33_we = addr_hit[97] & reg_we & !reg_error;
 
   assign alert_en_shadowed_33_wd = reg_wdata[0];
-  assign alert_en_shadowed_34_re = addr_hit[100] & reg_re & !reg_error;
-  assign alert_en_shadowed_34_we = addr_hit[100] & reg_we & !reg_error;
+  assign alert_en_shadowed_34_re = addr_hit[98] & reg_re & !reg_error;
+  assign alert_en_shadowed_34_we = addr_hit[98] & reg_we & !reg_error;
 
   assign alert_en_shadowed_34_wd = reg_wdata[0];
-  assign alert_en_shadowed_35_re = addr_hit[101] & reg_re & !reg_error;
-  assign alert_en_shadowed_35_we = addr_hit[101] & reg_we & !reg_error;
+  assign alert_en_shadowed_35_re = addr_hit[99] & reg_re & !reg_error;
+  assign alert_en_shadowed_35_we = addr_hit[99] & reg_we & !reg_error;
 
   assign alert_en_shadowed_35_wd = reg_wdata[0];
-  assign alert_en_shadowed_36_re = addr_hit[102] & reg_re & !reg_error;
-  assign alert_en_shadowed_36_we = addr_hit[102] & reg_we & !reg_error;
+  assign alert_en_shadowed_36_re = addr_hit[100] & reg_re & !reg_error;
+  assign alert_en_shadowed_36_we = addr_hit[100] & reg_we & !reg_error;
 
   assign alert_en_shadowed_36_wd = reg_wdata[0];
-  assign alert_en_shadowed_37_re = addr_hit[103] & reg_re & !reg_error;
-  assign alert_en_shadowed_37_we = addr_hit[103] & reg_we & !reg_error;
+  assign alert_en_shadowed_37_re = addr_hit[101] & reg_re & !reg_error;
+  assign alert_en_shadowed_37_we = addr_hit[101] & reg_we & !reg_error;
 
   assign alert_en_shadowed_37_wd = reg_wdata[0];
-  assign alert_en_shadowed_38_re = addr_hit[104] & reg_re & !reg_error;
-  assign alert_en_shadowed_38_we = addr_hit[104] & reg_we & !reg_error;
+  assign alert_en_shadowed_38_re = addr_hit[102] & reg_re & !reg_error;
+  assign alert_en_shadowed_38_we = addr_hit[102] & reg_we & !reg_error;
 
   assign alert_en_shadowed_38_wd = reg_wdata[0];
-  assign alert_en_shadowed_39_re = addr_hit[105] & reg_re & !reg_error;
-  assign alert_en_shadowed_39_we = addr_hit[105] & reg_we & !reg_error;
+  assign alert_en_shadowed_39_re = addr_hit[103] & reg_re & !reg_error;
+  assign alert_en_shadowed_39_we = addr_hit[103] & reg_we & !reg_error;
 
   assign alert_en_shadowed_39_wd = reg_wdata[0];
-  assign alert_en_shadowed_40_re = addr_hit[106] & reg_re & !reg_error;
-  assign alert_en_shadowed_40_we = addr_hit[106] & reg_we & !reg_error;
+  assign alert_en_shadowed_40_re = addr_hit[104] & reg_re & !reg_error;
+  assign alert_en_shadowed_40_we = addr_hit[104] & reg_we & !reg_error;
 
   assign alert_en_shadowed_40_wd = reg_wdata[0];
-  assign alert_en_shadowed_41_re = addr_hit[107] & reg_re & !reg_error;
-  assign alert_en_shadowed_41_we = addr_hit[107] & reg_we & !reg_error;
+  assign alert_en_shadowed_41_re = addr_hit[105] & reg_re & !reg_error;
+  assign alert_en_shadowed_41_we = addr_hit[105] & reg_we & !reg_error;
 
   assign alert_en_shadowed_41_wd = reg_wdata[0];
-  assign alert_en_shadowed_42_re = addr_hit[108] & reg_re & !reg_error;
-  assign alert_en_shadowed_42_we = addr_hit[108] & reg_we & !reg_error;
+  assign alert_en_shadowed_42_re = addr_hit[106] & reg_re & !reg_error;
+  assign alert_en_shadowed_42_we = addr_hit[106] & reg_we & !reg_error;
 
   assign alert_en_shadowed_42_wd = reg_wdata[0];
-  assign alert_en_shadowed_43_re = addr_hit[109] & reg_re & !reg_error;
-  assign alert_en_shadowed_43_we = addr_hit[109] & reg_we & !reg_error;
+  assign alert_en_shadowed_43_re = addr_hit[107] & reg_re & !reg_error;
+  assign alert_en_shadowed_43_we = addr_hit[107] & reg_we & !reg_error;
 
   assign alert_en_shadowed_43_wd = reg_wdata[0];
-  assign alert_en_shadowed_44_re = addr_hit[110] & reg_re & !reg_error;
-  assign alert_en_shadowed_44_we = addr_hit[110] & reg_we & !reg_error;
+  assign alert_en_shadowed_44_re = addr_hit[108] & reg_re & !reg_error;
+  assign alert_en_shadowed_44_we = addr_hit[108] & reg_we & !reg_error;
 
   assign alert_en_shadowed_44_wd = reg_wdata[0];
-  assign alert_en_shadowed_45_re = addr_hit[111] & reg_re & !reg_error;
-  assign alert_en_shadowed_45_we = addr_hit[111] & reg_we & !reg_error;
+  assign alert_en_shadowed_45_re = addr_hit[109] & reg_re & !reg_error;
+  assign alert_en_shadowed_45_we = addr_hit[109] & reg_we & !reg_error;
 
   assign alert_en_shadowed_45_wd = reg_wdata[0];
-  assign alert_en_shadowed_46_re = addr_hit[112] & reg_re & !reg_error;
-  assign alert_en_shadowed_46_we = addr_hit[112] & reg_we & !reg_error;
+  assign alert_en_shadowed_46_re = addr_hit[110] & reg_re & !reg_error;
+  assign alert_en_shadowed_46_we = addr_hit[110] & reg_we & !reg_error;
 
   assign alert_en_shadowed_46_wd = reg_wdata[0];
-  assign alert_en_shadowed_47_re = addr_hit[113] & reg_re & !reg_error;
-  assign alert_en_shadowed_47_we = addr_hit[113] & reg_we & !reg_error;
+  assign alert_en_shadowed_47_re = addr_hit[111] & reg_re & !reg_error;
+  assign alert_en_shadowed_47_we = addr_hit[111] & reg_we & !reg_error;
 
   assign alert_en_shadowed_47_wd = reg_wdata[0];
-  assign alert_en_shadowed_48_re = addr_hit[114] & reg_re & !reg_error;
-  assign alert_en_shadowed_48_we = addr_hit[114] & reg_we & !reg_error;
+  assign alert_en_shadowed_48_re = addr_hit[112] & reg_re & !reg_error;
+  assign alert_en_shadowed_48_we = addr_hit[112] & reg_we & !reg_error;
 
   assign alert_en_shadowed_48_wd = reg_wdata[0];
-  assign alert_en_shadowed_49_re = addr_hit[115] & reg_re & !reg_error;
-  assign alert_en_shadowed_49_we = addr_hit[115] & reg_we & !reg_error;
+  assign alert_en_shadowed_49_re = addr_hit[113] & reg_re & !reg_error;
+  assign alert_en_shadowed_49_we = addr_hit[113] & reg_we & !reg_error;
 
   assign alert_en_shadowed_49_wd = reg_wdata[0];
-  assign alert_en_shadowed_50_re = addr_hit[116] & reg_re & !reg_error;
-  assign alert_en_shadowed_50_we = addr_hit[116] & reg_we & !reg_error;
+  assign alert_en_shadowed_50_re = addr_hit[114] & reg_re & !reg_error;
+  assign alert_en_shadowed_50_we = addr_hit[114] & reg_we & !reg_error;
 
   assign alert_en_shadowed_50_wd = reg_wdata[0];
-  assign alert_en_shadowed_51_re = addr_hit[117] & reg_re & !reg_error;
-  assign alert_en_shadowed_51_we = addr_hit[117] & reg_we & !reg_error;
+  assign alert_en_shadowed_51_re = addr_hit[115] & reg_re & !reg_error;
+  assign alert_en_shadowed_51_we = addr_hit[115] & reg_we & !reg_error;
 
   assign alert_en_shadowed_51_wd = reg_wdata[0];
-  assign alert_en_shadowed_52_re = addr_hit[118] & reg_re & !reg_error;
-  assign alert_en_shadowed_52_we = addr_hit[118] & reg_we & !reg_error;
+  assign alert_en_shadowed_52_re = addr_hit[116] & reg_re & !reg_error;
+  assign alert_en_shadowed_52_we = addr_hit[116] & reg_we & !reg_error;
 
   assign alert_en_shadowed_52_wd = reg_wdata[0];
-  assign alert_en_shadowed_53_re = addr_hit[119] & reg_re & !reg_error;
-  assign alert_en_shadowed_53_we = addr_hit[119] & reg_we & !reg_error;
+  assign alert_en_shadowed_53_re = addr_hit[117] & reg_re & !reg_error;
+  assign alert_en_shadowed_53_we = addr_hit[117] & reg_we & !reg_error;
 
   assign alert_en_shadowed_53_wd = reg_wdata[0];
-  assign alert_en_shadowed_54_re = addr_hit[120] & reg_re & !reg_error;
-  assign alert_en_shadowed_54_we = addr_hit[120] & reg_we & !reg_error;
+  assign alert_en_shadowed_54_re = addr_hit[118] & reg_re & !reg_error;
+  assign alert_en_shadowed_54_we = addr_hit[118] & reg_we & !reg_error;
 
   assign alert_en_shadowed_54_wd = reg_wdata[0];
-  assign alert_en_shadowed_55_re = addr_hit[121] & reg_re & !reg_error;
-  assign alert_en_shadowed_55_we = addr_hit[121] & reg_we & !reg_error;
+  assign alert_en_shadowed_55_re = addr_hit[119] & reg_re & !reg_error;
+  assign alert_en_shadowed_55_we = addr_hit[119] & reg_we & !reg_error;
 
   assign alert_en_shadowed_55_wd = reg_wdata[0];
-  assign alert_en_shadowed_56_re = addr_hit[122] & reg_re & !reg_error;
-  assign alert_en_shadowed_56_we = addr_hit[122] & reg_we & !reg_error;
+  assign alert_en_shadowed_56_re = addr_hit[120] & reg_re & !reg_error;
+  assign alert_en_shadowed_56_we = addr_hit[120] & reg_we & !reg_error;
 
   assign alert_en_shadowed_56_wd = reg_wdata[0];
-  assign alert_en_shadowed_57_re = addr_hit[123] & reg_re & !reg_error;
-  assign alert_en_shadowed_57_we = addr_hit[123] & reg_we & !reg_error;
+  assign alert_en_shadowed_57_re = addr_hit[121] & reg_re & !reg_error;
+  assign alert_en_shadowed_57_we = addr_hit[121] & reg_we & !reg_error;
 
   assign alert_en_shadowed_57_wd = reg_wdata[0];
-  assign alert_en_shadowed_58_re = addr_hit[124] & reg_re & !reg_error;
-  assign alert_en_shadowed_58_we = addr_hit[124] & reg_we & !reg_error;
-
-  assign alert_en_shadowed_58_wd = reg_wdata[0];
-  assign alert_en_shadowed_59_re = addr_hit[125] & reg_re & !reg_error;
-  assign alert_en_shadowed_59_we = addr_hit[125] & reg_we & !reg_error;
-
-  assign alert_en_shadowed_59_wd = reg_wdata[0];
-  assign alert_class_shadowed_0_re = addr_hit[126] & reg_re & !reg_error;
-  assign alert_class_shadowed_0_we = addr_hit[126] & reg_we & !reg_error;
+  assign alert_class_shadowed_0_re = addr_hit[122] & reg_re & !reg_error;
+  assign alert_class_shadowed_0_we = addr_hit[122] & reg_we & !reg_error;
 
   assign alert_class_shadowed_0_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_1_re = addr_hit[127] & reg_re & !reg_error;
-  assign alert_class_shadowed_1_we = addr_hit[127] & reg_we & !reg_error;
+  assign alert_class_shadowed_1_re = addr_hit[123] & reg_re & !reg_error;
+  assign alert_class_shadowed_1_we = addr_hit[123] & reg_we & !reg_error;
 
   assign alert_class_shadowed_1_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_2_re = addr_hit[128] & reg_re & !reg_error;
-  assign alert_class_shadowed_2_we = addr_hit[128] & reg_we & !reg_error;
+  assign alert_class_shadowed_2_re = addr_hit[124] & reg_re & !reg_error;
+  assign alert_class_shadowed_2_we = addr_hit[124] & reg_we & !reg_error;
 
   assign alert_class_shadowed_2_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_3_re = addr_hit[129] & reg_re & !reg_error;
-  assign alert_class_shadowed_3_we = addr_hit[129] & reg_we & !reg_error;
+  assign alert_class_shadowed_3_re = addr_hit[125] & reg_re & !reg_error;
+  assign alert_class_shadowed_3_we = addr_hit[125] & reg_we & !reg_error;
 
   assign alert_class_shadowed_3_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_4_re = addr_hit[130] & reg_re & !reg_error;
-  assign alert_class_shadowed_4_we = addr_hit[130] & reg_we & !reg_error;
+  assign alert_class_shadowed_4_re = addr_hit[126] & reg_re & !reg_error;
+  assign alert_class_shadowed_4_we = addr_hit[126] & reg_we & !reg_error;
 
   assign alert_class_shadowed_4_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_5_re = addr_hit[131] & reg_re & !reg_error;
-  assign alert_class_shadowed_5_we = addr_hit[131] & reg_we & !reg_error;
+  assign alert_class_shadowed_5_re = addr_hit[127] & reg_re & !reg_error;
+  assign alert_class_shadowed_5_we = addr_hit[127] & reg_we & !reg_error;
 
   assign alert_class_shadowed_5_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_6_re = addr_hit[132] & reg_re & !reg_error;
-  assign alert_class_shadowed_6_we = addr_hit[132] & reg_we & !reg_error;
+  assign alert_class_shadowed_6_re = addr_hit[128] & reg_re & !reg_error;
+  assign alert_class_shadowed_6_we = addr_hit[128] & reg_we & !reg_error;
 
   assign alert_class_shadowed_6_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_7_re = addr_hit[133] & reg_re & !reg_error;
-  assign alert_class_shadowed_7_we = addr_hit[133] & reg_we & !reg_error;
+  assign alert_class_shadowed_7_re = addr_hit[129] & reg_re & !reg_error;
+  assign alert_class_shadowed_7_we = addr_hit[129] & reg_we & !reg_error;
 
   assign alert_class_shadowed_7_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_8_re = addr_hit[134] & reg_re & !reg_error;
-  assign alert_class_shadowed_8_we = addr_hit[134] & reg_we & !reg_error;
+  assign alert_class_shadowed_8_re = addr_hit[130] & reg_re & !reg_error;
+  assign alert_class_shadowed_8_we = addr_hit[130] & reg_we & !reg_error;
 
   assign alert_class_shadowed_8_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_9_re = addr_hit[135] & reg_re & !reg_error;
-  assign alert_class_shadowed_9_we = addr_hit[135] & reg_we & !reg_error;
+  assign alert_class_shadowed_9_re = addr_hit[131] & reg_re & !reg_error;
+  assign alert_class_shadowed_9_we = addr_hit[131] & reg_we & !reg_error;
 
   assign alert_class_shadowed_9_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_10_re = addr_hit[136] & reg_re & !reg_error;
-  assign alert_class_shadowed_10_we = addr_hit[136] & reg_we & !reg_error;
+  assign alert_class_shadowed_10_re = addr_hit[132] & reg_re & !reg_error;
+  assign alert_class_shadowed_10_we = addr_hit[132] & reg_we & !reg_error;
 
   assign alert_class_shadowed_10_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_11_re = addr_hit[137] & reg_re & !reg_error;
-  assign alert_class_shadowed_11_we = addr_hit[137] & reg_we & !reg_error;
+  assign alert_class_shadowed_11_re = addr_hit[133] & reg_re & !reg_error;
+  assign alert_class_shadowed_11_we = addr_hit[133] & reg_we & !reg_error;
 
   assign alert_class_shadowed_11_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_12_re = addr_hit[138] & reg_re & !reg_error;
-  assign alert_class_shadowed_12_we = addr_hit[138] & reg_we & !reg_error;
+  assign alert_class_shadowed_12_re = addr_hit[134] & reg_re & !reg_error;
+  assign alert_class_shadowed_12_we = addr_hit[134] & reg_we & !reg_error;
 
   assign alert_class_shadowed_12_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_13_re = addr_hit[139] & reg_re & !reg_error;
-  assign alert_class_shadowed_13_we = addr_hit[139] & reg_we & !reg_error;
+  assign alert_class_shadowed_13_re = addr_hit[135] & reg_re & !reg_error;
+  assign alert_class_shadowed_13_we = addr_hit[135] & reg_we & !reg_error;
 
   assign alert_class_shadowed_13_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_14_re = addr_hit[140] & reg_re & !reg_error;
-  assign alert_class_shadowed_14_we = addr_hit[140] & reg_we & !reg_error;
+  assign alert_class_shadowed_14_re = addr_hit[136] & reg_re & !reg_error;
+  assign alert_class_shadowed_14_we = addr_hit[136] & reg_we & !reg_error;
 
   assign alert_class_shadowed_14_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_15_re = addr_hit[141] & reg_re & !reg_error;
-  assign alert_class_shadowed_15_we = addr_hit[141] & reg_we & !reg_error;
+  assign alert_class_shadowed_15_re = addr_hit[137] & reg_re & !reg_error;
+  assign alert_class_shadowed_15_we = addr_hit[137] & reg_we & !reg_error;
 
   assign alert_class_shadowed_15_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_16_re = addr_hit[142] & reg_re & !reg_error;
-  assign alert_class_shadowed_16_we = addr_hit[142] & reg_we & !reg_error;
+  assign alert_class_shadowed_16_re = addr_hit[138] & reg_re & !reg_error;
+  assign alert_class_shadowed_16_we = addr_hit[138] & reg_we & !reg_error;
 
   assign alert_class_shadowed_16_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_17_re = addr_hit[143] & reg_re & !reg_error;
-  assign alert_class_shadowed_17_we = addr_hit[143] & reg_we & !reg_error;
+  assign alert_class_shadowed_17_re = addr_hit[139] & reg_re & !reg_error;
+  assign alert_class_shadowed_17_we = addr_hit[139] & reg_we & !reg_error;
 
   assign alert_class_shadowed_17_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_18_re = addr_hit[144] & reg_re & !reg_error;
-  assign alert_class_shadowed_18_we = addr_hit[144] & reg_we & !reg_error;
+  assign alert_class_shadowed_18_re = addr_hit[140] & reg_re & !reg_error;
+  assign alert_class_shadowed_18_we = addr_hit[140] & reg_we & !reg_error;
 
   assign alert_class_shadowed_18_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_19_re = addr_hit[145] & reg_re & !reg_error;
-  assign alert_class_shadowed_19_we = addr_hit[145] & reg_we & !reg_error;
+  assign alert_class_shadowed_19_re = addr_hit[141] & reg_re & !reg_error;
+  assign alert_class_shadowed_19_we = addr_hit[141] & reg_we & !reg_error;
 
   assign alert_class_shadowed_19_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_20_re = addr_hit[146] & reg_re & !reg_error;
-  assign alert_class_shadowed_20_we = addr_hit[146] & reg_we & !reg_error;
+  assign alert_class_shadowed_20_re = addr_hit[142] & reg_re & !reg_error;
+  assign alert_class_shadowed_20_we = addr_hit[142] & reg_we & !reg_error;
 
   assign alert_class_shadowed_20_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_21_re = addr_hit[147] & reg_re & !reg_error;
-  assign alert_class_shadowed_21_we = addr_hit[147] & reg_we & !reg_error;
+  assign alert_class_shadowed_21_re = addr_hit[143] & reg_re & !reg_error;
+  assign alert_class_shadowed_21_we = addr_hit[143] & reg_we & !reg_error;
 
   assign alert_class_shadowed_21_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_22_re = addr_hit[148] & reg_re & !reg_error;
-  assign alert_class_shadowed_22_we = addr_hit[148] & reg_we & !reg_error;
+  assign alert_class_shadowed_22_re = addr_hit[144] & reg_re & !reg_error;
+  assign alert_class_shadowed_22_we = addr_hit[144] & reg_we & !reg_error;
 
   assign alert_class_shadowed_22_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_23_re = addr_hit[149] & reg_re & !reg_error;
-  assign alert_class_shadowed_23_we = addr_hit[149] & reg_we & !reg_error;
+  assign alert_class_shadowed_23_re = addr_hit[145] & reg_re & !reg_error;
+  assign alert_class_shadowed_23_we = addr_hit[145] & reg_we & !reg_error;
 
   assign alert_class_shadowed_23_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_24_re = addr_hit[150] & reg_re & !reg_error;
-  assign alert_class_shadowed_24_we = addr_hit[150] & reg_we & !reg_error;
+  assign alert_class_shadowed_24_re = addr_hit[146] & reg_re & !reg_error;
+  assign alert_class_shadowed_24_we = addr_hit[146] & reg_we & !reg_error;
 
   assign alert_class_shadowed_24_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_25_re = addr_hit[151] & reg_re & !reg_error;
-  assign alert_class_shadowed_25_we = addr_hit[151] & reg_we & !reg_error;
+  assign alert_class_shadowed_25_re = addr_hit[147] & reg_re & !reg_error;
+  assign alert_class_shadowed_25_we = addr_hit[147] & reg_we & !reg_error;
 
   assign alert_class_shadowed_25_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_26_re = addr_hit[152] & reg_re & !reg_error;
-  assign alert_class_shadowed_26_we = addr_hit[152] & reg_we & !reg_error;
+  assign alert_class_shadowed_26_re = addr_hit[148] & reg_re & !reg_error;
+  assign alert_class_shadowed_26_we = addr_hit[148] & reg_we & !reg_error;
 
   assign alert_class_shadowed_26_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_27_re = addr_hit[153] & reg_re & !reg_error;
-  assign alert_class_shadowed_27_we = addr_hit[153] & reg_we & !reg_error;
+  assign alert_class_shadowed_27_re = addr_hit[149] & reg_re & !reg_error;
+  assign alert_class_shadowed_27_we = addr_hit[149] & reg_we & !reg_error;
 
   assign alert_class_shadowed_27_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_28_re = addr_hit[154] & reg_re & !reg_error;
-  assign alert_class_shadowed_28_we = addr_hit[154] & reg_we & !reg_error;
+  assign alert_class_shadowed_28_re = addr_hit[150] & reg_re & !reg_error;
+  assign alert_class_shadowed_28_we = addr_hit[150] & reg_we & !reg_error;
 
   assign alert_class_shadowed_28_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_29_re = addr_hit[155] & reg_re & !reg_error;
-  assign alert_class_shadowed_29_we = addr_hit[155] & reg_we & !reg_error;
+  assign alert_class_shadowed_29_re = addr_hit[151] & reg_re & !reg_error;
+  assign alert_class_shadowed_29_we = addr_hit[151] & reg_we & !reg_error;
 
   assign alert_class_shadowed_29_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_30_re = addr_hit[156] & reg_re & !reg_error;
-  assign alert_class_shadowed_30_we = addr_hit[156] & reg_we & !reg_error;
+  assign alert_class_shadowed_30_re = addr_hit[152] & reg_re & !reg_error;
+  assign alert_class_shadowed_30_we = addr_hit[152] & reg_we & !reg_error;
 
   assign alert_class_shadowed_30_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_31_re = addr_hit[157] & reg_re & !reg_error;
-  assign alert_class_shadowed_31_we = addr_hit[157] & reg_we & !reg_error;
+  assign alert_class_shadowed_31_re = addr_hit[153] & reg_re & !reg_error;
+  assign alert_class_shadowed_31_we = addr_hit[153] & reg_we & !reg_error;
 
   assign alert_class_shadowed_31_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_32_re = addr_hit[158] & reg_re & !reg_error;
-  assign alert_class_shadowed_32_we = addr_hit[158] & reg_we & !reg_error;
+  assign alert_class_shadowed_32_re = addr_hit[154] & reg_re & !reg_error;
+  assign alert_class_shadowed_32_we = addr_hit[154] & reg_we & !reg_error;
 
   assign alert_class_shadowed_32_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_33_re = addr_hit[159] & reg_re & !reg_error;
-  assign alert_class_shadowed_33_we = addr_hit[159] & reg_we & !reg_error;
+  assign alert_class_shadowed_33_re = addr_hit[155] & reg_re & !reg_error;
+  assign alert_class_shadowed_33_we = addr_hit[155] & reg_we & !reg_error;
 
   assign alert_class_shadowed_33_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_34_re = addr_hit[160] & reg_re & !reg_error;
-  assign alert_class_shadowed_34_we = addr_hit[160] & reg_we & !reg_error;
+  assign alert_class_shadowed_34_re = addr_hit[156] & reg_re & !reg_error;
+  assign alert_class_shadowed_34_we = addr_hit[156] & reg_we & !reg_error;
 
   assign alert_class_shadowed_34_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_35_re = addr_hit[161] & reg_re & !reg_error;
-  assign alert_class_shadowed_35_we = addr_hit[161] & reg_we & !reg_error;
+  assign alert_class_shadowed_35_re = addr_hit[157] & reg_re & !reg_error;
+  assign alert_class_shadowed_35_we = addr_hit[157] & reg_we & !reg_error;
 
   assign alert_class_shadowed_35_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_36_re = addr_hit[162] & reg_re & !reg_error;
-  assign alert_class_shadowed_36_we = addr_hit[162] & reg_we & !reg_error;
+  assign alert_class_shadowed_36_re = addr_hit[158] & reg_re & !reg_error;
+  assign alert_class_shadowed_36_we = addr_hit[158] & reg_we & !reg_error;
 
   assign alert_class_shadowed_36_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_37_re = addr_hit[163] & reg_re & !reg_error;
-  assign alert_class_shadowed_37_we = addr_hit[163] & reg_we & !reg_error;
+  assign alert_class_shadowed_37_re = addr_hit[159] & reg_re & !reg_error;
+  assign alert_class_shadowed_37_we = addr_hit[159] & reg_we & !reg_error;
 
   assign alert_class_shadowed_37_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_38_re = addr_hit[164] & reg_re & !reg_error;
-  assign alert_class_shadowed_38_we = addr_hit[164] & reg_we & !reg_error;
+  assign alert_class_shadowed_38_re = addr_hit[160] & reg_re & !reg_error;
+  assign alert_class_shadowed_38_we = addr_hit[160] & reg_we & !reg_error;
 
   assign alert_class_shadowed_38_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_39_re = addr_hit[165] & reg_re & !reg_error;
-  assign alert_class_shadowed_39_we = addr_hit[165] & reg_we & !reg_error;
+  assign alert_class_shadowed_39_re = addr_hit[161] & reg_re & !reg_error;
+  assign alert_class_shadowed_39_we = addr_hit[161] & reg_we & !reg_error;
 
   assign alert_class_shadowed_39_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_40_re = addr_hit[166] & reg_re & !reg_error;
-  assign alert_class_shadowed_40_we = addr_hit[166] & reg_we & !reg_error;
+  assign alert_class_shadowed_40_re = addr_hit[162] & reg_re & !reg_error;
+  assign alert_class_shadowed_40_we = addr_hit[162] & reg_we & !reg_error;
 
   assign alert_class_shadowed_40_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_41_re = addr_hit[167] & reg_re & !reg_error;
-  assign alert_class_shadowed_41_we = addr_hit[167] & reg_we & !reg_error;
+  assign alert_class_shadowed_41_re = addr_hit[163] & reg_re & !reg_error;
+  assign alert_class_shadowed_41_we = addr_hit[163] & reg_we & !reg_error;
 
   assign alert_class_shadowed_41_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_42_re = addr_hit[168] & reg_re & !reg_error;
-  assign alert_class_shadowed_42_we = addr_hit[168] & reg_we & !reg_error;
+  assign alert_class_shadowed_42_re = addr_hit[164] & reg_re & !reg_error;
+  assign alert_class_shadowed_42_we = addr_hit[164] & reg_we & !reg_error;
 
   assign alert_class_shadowed_42_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_43_re = addr_hit[169] & reg_re & !reg_error;
-  assign alert_class_shadowed_43_we = addr_hit[169] & reg_we & !reg_error;
+  assign alert_class_shadowed_43_re = addr_hit[165] & reg_re & !reg_error;
+  assign alert_class_shadowed_43_we = addr_hit[165] & reg_we & !reg_error;
 
   assign alert_class_shadowed_43_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_44_re = addr_hit[170] & reg_re & !reg_error;
-  assign alert_class_shadowed_44_we = addr_hit[170] & reg_we & !reg_error;
+  assign alert_class_shadowed_44_re = addr_hit[166] & reg_re & !reg_error;
+  assign alert_class_shadowed_44_we = addr_hit[166] & reg_we & !reg_error;
 
   assign alert_class_shadowed_44_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_45_re = addr_hit[171] & reg_re & !reg_error;
-  assign alert_class_shadowed_45_we = addr_hit[171] & reg_we & !reg_error;
+  assign alert_class_shadowed_45_re = addr_hit[167] & reg_re & !reg_error;
+  assign alert_class_shadowed_45_we = addr_hit[167] & reg_we & !reg_error;
 
   assign alert_class_shadowed_45_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_46_re = addr_hit[172] & reg_re & !reg_error;
-  assign alert_class_shadowed_46_we = addr_hit[172] & reg_we & !reg_error;
+  assign alert_class_shadowed_46_re = addr_hit[168] & reg_re & !reg_error;
+  assign alert_class_shadowed_46_we = addr_hit[168] & reg_we & !reg_error;
 
   assign alert_class_shadowed_46_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_47_re = addr_hit[173] & reg_re & !reg_error;
-  assign alert_class_shadowed_47_we = addr_hit[173] & reg_we & !reg_error;
+  assign alert_class_shadowed_47_re = addr_hit[169] & reg_re & !reg_error;
+  assign alert_class_shadowed_47_we = addr_hit[169] & reg_we & !reg_error;
 
   assign alert_class_shadowed_47_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_48_re = addr_hit[174] & reg_re & !reg_error;
-  assign alert_class_shadowed_48_we = addr_hit[174] & reg_we & !reg_error;
+  assign alert_class_shadowed_48_re = addr_hit[170] & reg_re & !reg_error;
+  assign alert_class_shadowed_48_we = addr_hit[170] & reg_we & !reg_error;
 
   assign alert_class_shadowed_48_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_49_re = addr_hit[175] & reg_re & !reg_error;
-  assign alert_class_shadowed_49_we = addr_hit[175] & reg_we & !reg_error;
+  assign alert_class_shadowed_49_re = addr_hit[171] & reg_re & !reg_error;
+  assign alert_class_shadowed_49_we = addr_hit[171] & reg_we & !reg_error;
 
   assign alert_class_shadowed_49_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_50_re = addr_hit[176] & reg_re & !reg_error;
-  assign alert_class_shadowed_50_we = addr_hit[176] & reg_we & !reg_error;
+  assign alert_class_shadowed_50_re = addr_hit[172] & reg_re & !reg_error;
+  assign alert_class_shadowed_50_we = addr_hit[172] & reg_we & !reg_error;
 
   assign alert_class_shadowed_50_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_51_re = addr_hit[177] & reg_re & !reg_error;
-  assign alert_class_shadowed_51_we = addr_hit[177] & reg_we & !reg_error;
+  assign alert_class_shadowed_51_re = addr_hit[173] & reg_re & !reg_error;
+  assign alert_class_shadowed_51_we = addr_hit[173] & reg_we & !reg_error;
 
   assign alert_class_shadowed_51_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_52_re = addr_hit[178] & reg_re & !reg_error;
-  assign alert_class_shadowed_52_we = addr_hit[178] & reg_we & !reg_error;
+  assign alert_class_shadowed_52_re = addr_hit[174] & reg_re & !reg_error;
+  assign alert_class_shadowed_52_we = addr_hit[174] & reg_we & !reg_error;
 
   assign alert_class_shadowed_52_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_53_re = addr_hit[179] & reg_re & !reg_error;
-  assign alert_class_shadowed_53_we = addr_hit[179] & reg_we & !reg_error;
+  assign alert_class_shadowed_53_re = addr_hit[175] & reg_re & !reg_error;
+  assign alert_class_shadowed_53_we = addr_hit[175] & reg_we & !reg_error;
 
   assign alert_class_shadowed_53_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_54_re = addr_hit[180] & reg_re & !reg_error;
-  assign alert_class_shadowed_54_we = addr_hit[180] & reg_we & !reg_error;
+  assign alert_class_shadowed_54_re = addr_hit[176] & reg_re & !reg_error;
+  assign alert_class_shadowed_54_we = addr_hit[176] & reg_we & !reg_error;
 
   assign alert_class_shadowed_54_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_55_re = addr_hit[181] & reg_re & !reg_error;
-  assign alert_class_shadowed_55_we = addr_hit[181] & reg_we & !reg_error;
+  assign alert_class_shadowed_55_re = addr_hit[177] & reg_re & !reg_error;
+  assign alert_class_shadowed_55_we = addr_hit[177] & reg_we & !reg_error;
 
   assign alert_class_shadowed_55_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_56_re = addr_hit[182] & reg_re & !reg_error;
-  assign alert_class_shadowed_56_we = addr_hit[182] & reg_we & !reg_error;
+  assign alert_class_shadowed_56_re = addr_hit[178] & reg_re & !reg_error;
+  assign alert_class_shadowed_56_we = addr_hit[178] & reg_we & !reg_error;
 
   assign alert_class_shadowed_56_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_57_re = addr_hit[183] & reg_re & !reg_error;
-  assign alert_class_shadowed_57_we = addr_hit[183] & reg_we & !reg_error;
+  assign alert_class_shadowed_57_re = addr_hit[179] & reg_re & !reg_error;
+  assign alert_class_shadowed_57_we = addr_hit[179] & reg_we & !reg_error;
 
   assign alert_class_shadowed_57_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_58_re = addr_hit[184] & reg_re & !reg_error;
-  assign alert_class_shadowed_58_we = addr_hit[184] & reg_we & !reg_error;
-
-  assign alert_class_shadowed_58_wd = reg_wdata[1:0];
-  assign alert_class_shadowed_59_re = addr_hit[185] & reg_re & !reg_error;
-  assign alert_class_shadowed_59_we = addr_hit[185] & reg_we & !reg_error;
-
-  assign alert_class_shadowed_59_wd = reg_wdata[1:0];
-  assign alert_cause_0_we = addr_hit[186] & reg_we & !reg_error;
+  assign alert_cause_0_we = addr_hit[180] & reg_we & !reg_error;
 
   assign alert_cause_0_wd = reg_wdata[0];
-  assign alert_cause_1_we = addr_hit[187] & reg_we & !reg_error;
+  assign alert_cause_1_we = addr_hit[181] & reg_we & !reg_error;
 
   assign alert_cause_1_wd = reg_wdata[0];
-  assign alert_cause_2_we = addr_hit[188] & reg_we & !reg_error;
+  assign alert_cause_2_we = addr_hit[182] & reg_we & !reg_error;
 
   assign alert_cause_2_wd = reg_wdata[0];
-  assign alert_cause_3_we = addr_hit[189] & reg_we & !reg_error;
+  assign alert_cause_3_we = addr_hit[183] & reg_we & !reg_error;
 
   assign alert_cause_3_wd = reg_wdata[0];
-  assign alert_cause_4_we = addr_hit[190] & reg_we & !reg_error;
+  assign alert_cause_4_we = addr_hit[184] & reg_we & !reg_error;
 
   assign alert_cause_4_wd = reg_wdata[0];
-  assign alert_cause_5_we = addr_hit[191] & reg_we & !reg_error;
+  assign alert_cause_5_we = addr_hit[185] & reg_we & !reg_error;
 
   assign alert_cause_5_wd = reg_wdata[0];
-  assign alert_cause_6_we = addr_hit[192] & reg_we & !reg_error;
+  assign alert_cause_6_we = addr_hit[186] & reg_we & !reg_error;
 
   assign alert_cause_6_wd = reg_wdata[0];
-  assign alert_cause_7_we = addr_hit[193] & reg_we & !reg_error;
+  assign alert_cause_7_we = addr_hit[187] & reg_we & !reg_error;
 
   assign alert_cause_7_wd = reg_wdata[0];
-  assign alert_cause_8_we = addr_hit[194] & reg_we & !reg_error;
+  assign alert_cause_8_we = addr_hit[188] & reg_we & !reg_error;
 
   assign alert_cause_8_wd = reg_wdata[0];
-  assign alert_cause_9_we = addr_hit[195] & reg_we & !reg_error;
+  assign alert_cause_9_we = addr_hit[189] & reg_we & !reg_error;
 
   assign alert_cause_9_wd = reg_wdata[0];
-  assign alert_cause_10_we = addr_hit[196] & reg_we & !reg_error;
+  assign alert_cause_10_we = addr_hit[190] & reg_we & !reg_error;
 
   assign alert_cause_10_wd = reg_wdata[0];
-  assign alert_cause_11_we = addr_hit[197] & reg_we & !reg_error;
+  assign alert_cause_11_we = addr_hit[191] & reg_we & !reg_error;
 
   assign alert_cause_11_wd = reg_wdata[0];
-  assign alert_cause_12_we = addr_hit[198] & reg_we & !reg_error;
+  assign alert_cause_12_we = addr_hit[192] & reg_we & !reg_error;
 
   assign alert_cause_12_wd = reg_wdata[0];
-  assign alert_cause_13_we = addr_hit[199] & reg_we & !reg_error;
+  assign alert_cause_13_we = addr_hit[193] & reg_we & !reg_error;
 
   assign alert_cause_13_wd = reg_wdata[0];
-  assign alert_cause_14_we = addr_hit[200] & reg_we & !reg_error;
+  assign alert_cause_14_we = addr_hit[194] & reg_we & !reg_error;
 
   assign alert_cause_14_wd = reg_wdata[0];
-  assign alert_cause_15_we = addr_hit[201] & reg_we & !reg_error;
+  assign alert_cause_15_we = addr_hit[195] & reg_we & !reg_error;
 
   assign alert_cause_15_wd = reg_wdata[0];
-  assign alert_cause_16_we = addr_hit[202] & reg_we & !reg_error;
+  assign alert_cause_16_we = addr_hit[196] & reg_we & !reg_error;
 
   assign alert_cause_16_wd = reg_wdata[0];
-  assign alert_cause_17_we = addr_hit[203] & reg_we & !reg_error;
+  assign alert_cause_17_we = addr_hit[197] & reg_we & !reg_error;
 
   assign alert_cause_17_wd = reg_wdata[0];
-  assign alert_cause_18_we = addr_hit[204] & reg_we & !reg_error;
+  assign alert_cause_18_we = addr_hit[198] & reg_we & !reg_error;
 
   assign alert_cause_18_wd = reg_wdata[0];
-  assign alert_cause_19_we = addr_hit[205] & reg_we & !reg_error;
+  assign alert_cause_19_we = addr_hit[199] & reg_we & !reg_error;
 
   assign alert_cause_19_wd = reg_wdata[0];
-  assign alert_cause_20_we = addr_hit[206] & reg_we & !reg_error;
+  assign alert_cause_20_we = addr_hit[200] & reg_we & !reg_error;
 
   assign alert_cause_20_wd = reg_wdata[0];
-  assign alert_cause_21_we = addr_hit[207] & reg_we & !reg_error;
+  assign alert_cause_21_we = addr_hit[201] & reg_we & !reg_error;
 
   assign alert_cause_21_wd = reg_wdata[0];
-  assign alert_cause_22_we = addr_hit[208] & reg_we & !reg_error;
+  assign alert_cause_22_we = addr_hit[202] & reg_we & !reg_error;
 
   assign alert_cause_22_wd = reg_wdata[0];
-  assign alert_cause_23_we = addr_hit[209] & reg_we & !reg_error;
+  assign alert_cause_23_we = addr_hit[203] & reg_we & !reg_error;
 
   assign alert_cause_23_wd = reg_wdata[0];
-  assign alert_cause_24_we = addr_hit[210] & reg_we & !reg_error;
+  assign alert_cause_24_we = addr_hit[204] & reg_we & !reg_error;
 
   assign alert_cause_24_wd = reg_wdata[0];
-  assign alert_cause_25_we = addr_hit[211] & reg_we & !reg_error;
+  assign alert_cause_25_we = addr_hit[205] & reg_we & !reg_error;
 
   assign alert_cause_25_wd = reg_wdata[0];
-  assign alert_cause_26_we = addr_hit[212] & reg_we & !reg_error;
+  assign alert_cause_26_we = addr_hit[206] & reg_we & !reg_error;
 
   assign alert_cause_26_wd = reg_wdata[0];
-  assign alert_cause_27_we = addr_hit[213] & reg_we & !reg_error;
+  assign alert_cause_27_we = addr_hit[207] & reg_we & !reg_error;
 
   assign alert_cause_27_wd = reg_wdata[0];
-  assign alert_cause_28_we = addr_hit[214] & reg_we & !reg_error;
+  assign alert_cause_28_we = addr_hit[208] & reg_we & !reg_error;
 
   assign alert_cause_28_wd = reg_wdata[0];
-  assign alert_cause_29_we = addr_hit[215] & reg_we & !reg_error;
+  assign alert_cause_29_we = addr_hit[209] & reg_we & !reg_error;
 
   assign alert_cause_29_wd = reg_wdata[0];
-  assign alert_cause_30_we = addr_hit[216] & reg_we & !reg_error;
+  assign alert_cause_30_we = addr_hit[210] & reg_we & !reg_error;
 
   assign alert_cause_30_wd = reg_wdata[0];
-  assign alert_cause_31_we = addr_hit[217] & reg_we & !reg_error;
+  assign alert_cause_31_we = addr_hit[211] & reg_we & !reg_error;
 
   assign alert_cause_31_wd = reg_wdata[0];
-  assign alert_cause_32_we = addr_hit[218] & reg_we & !reg_error;
+  assign alert_cause_32_we = addr_hit[212] & reg_we & !reg_error;
 
   assign alert_cause_32_wd = reg_wdata[0];
-  assign alert_cause_33_we = addr_hit[219] & reg_we & !reg_error;
+  assign alert_cause_33_we = addr_hit[213] & reg_we & !reg_error;
 
   assign alert_cause_33_wd = reg_wdata[0];
-  assign alert_cause_34_we = addr_hit[220] & reg_we & !reg_error;
+  assign alert_cause_34_we = addr_hit[214] & reg_we & !reg_error;
 
   assign alert_cause_34_wd = reg_wdata[0];
-  assign alert_cause_35_we = addr_hit[221] & reg_we & !reg_error;
+  assign alert_cause_35_we = addr_hit[215] & reg_we & !reg_error;
 
   assign alert_cause_35_wd = reg_wdata[0];
-  assign alert_cause_36_we = addr_hit[222] & reg_we & !reg_error;
+  assign alert_cause_36_we = addr_hit[216] & reg_we & !reg_error;
 
   assign alert_cause_36_wd = reg_wdata[0];
-  assign alert_cause_37_we = addr_hit[223] & reg_we & !reg_error;
+  assign alert_cause_37_we = addr_hit[217] & reg_we & !reg_error;
 
   assign alert_cause_37_wd = reg_wdata[0];
-  assign alert_cause_38_we = addr_hit[224] & reg_we & !reg_error;
+  assign alert_cause_38_we = addr_hit[218] & reg_we & !reg_error;
 
   assign alert_cause_38_wd = reg_wdata[0];
-  assign alert_cause_39_we = addr_hit[225] & reg_we & !reg_error;
+  assign alert_cause_39_we = addr_hit[219] & reg_we & !reg_error;
 
   assign alert_cause_39_wd = reg_wdata[0];
-  assign alert_cause_40_we = addr_hit[226] & reg_we & !reg_error;
+  assign alert_cause_40_we = addr_hit[220] & reg_we & !reg_error;
 
   assign alert_cause_40_wd = reg_wdata[0];
-  assign alert_cause_41_we = addr_hit[227] & reg_we & !reg_error;
+  assign alert_cause_41_we = addr_hit[221] & reg_we & !reg_error;
 
   assign alert_cause_41_wd = reg_wdata[0];
-  assign alert_cause_42_we = addr_hit[228] & reg_we & !reg_error;
+  assign alert_cause_42_we = addr_hit[222] & reg_we & !reg_error;
 
   assign alert_cause_42_wd = reg_wdata[0];
-  assign alert_cause_43_we = addr_hit[229] & reg_we & !reg_error;
+  assign alert_cause_43_we = addr_hit[223] & reg_we & !reg_error;
 
   assign alert_cause_43_wd = reg_wdata[0];
-  assign alert_cause_44_we = addr_hit[230] & reg_we & !reg_error;
+  assign alert_cause_44_we = addr_hit[224] & reg_we & !reg_error;
 
   assign alert_cause_44_wd = reg_wdata[0];
-  assign alert_cause_45_we = addr_hit[231] & reg_we & !reg_error;
+  assign alert_cause_45_we = addr_hit[225] & reg_we & !reg_error;
 
   assign alert_cause_45_wd = reg_wdata[0];
-  assign alert_cause_46_we = addr_hit[232] & reg_we & !reg_error;
+  assign alert_cause_46_we = addr_hit[226] & reg_we & !reg_error;
 
   assign alert_cause_46_wd = reg_wdata[0];
-  assign alert_cause_47_we = addr_hit[233] & reg_we & !reg_error;
+  assign alert_cause_47_we = addr_hit[227] & reg_we & !reg_error;
 
   assign alert_cause_47_wd = reg_wdata[0];
-  assign alert_cause_48_we = addr_hit[234] & reg_we & !reg_error;
+  assign alert_cause_48_we = addr_hit[228] & reg_we & !reg_error;
 
   assign alert_cause_48_wd = reg_wdata[0];
-  assign alert_cause_49_we = addr_hit[235] & reg_we & !reg_error;
+  assign alert_cause_49_we = addr_hit[229] & reg_we & !reg_error;
 
   assign alert_cause_49_wd = reg_wdata[0];
-  assign alert_cause_50_we = addr_hit[236] & reg_we & !reg_error;
+  assign alert_cause_50_we = addr_hit[230] & reg_we & !reg_error;
 
   assign alert_cause_50_wd = reg_wdata[0];
-  assign alert_cause_51_we = addr_hit[237] & reg_we & !reg_error;
+  assign alert_cause_51_we = addr_hit[231] & reg_we & !reg_error;
 
   assign alert_cause_51_wd = reg_wdata[0];
-  assign alert_cause_52_we = addr_hit[238] & reg_we & !reg_error;
+  assign alert_cause_52_we = addr_hit[232] & reg_we & !reg_error;
 
   assign alert_cause_52_wd = reg_wdata[0];
-  assign alert_cause_53_we = addr_hit[239] & reg_we & !reg_error;
+  assign alert_cause_53_we = addr_hit[233] & reg_we & !reg_error;
 
   assign alert_cause_53_wd = reg_wdata[0];
-  assign alert_cause_54_we = addr_hit[240] & reg_we & !reg_error;
+  assign alert_cause_54_we = addr_hit[234] & reg_we & !reg_error;
 
   assign alert_cause_54_wd = reg_wdata[0];
-  assign alert_cause_55_we = addr_hit[241] & reg_we & !reg_error;
+  assign alert_cause_55_we = addr_hit[235] & reg_we & !reg_error;
 
   assign alert_cause_55_wd = reg_wdata[0];
-  assign alert_cause_56_we = addr_hit[242] & reg_we & !reg_error;
+  assign alert_cause_56_we = addr_hit[236] & reg_we & !reg_error;
 
   assign alert_cause_56_wd = reg_wdata[0];
-  assign alert_cause_57_we = addr_hit[243] & reg_we & !reg_error;
+  assign alert_cause_57_we = addr_hit[237] & reg_we & !reg_error;
 
   assign alert_cause_57_wd = reg_wdata[0];
-  assign alert_cause_58_we = addr_hit[244] & reg_we & !reg_error;
-
-  assign alert_cause_58_wd = reg_wdata[0];
-  assign alert_cause_59_we = addr_hit[245] & reg_we & !reg_error;
-
-  assign alert_cause_59_wd = reg_wdata[0];
-  assign loc_alert_regwen_0_we = addr_hit[246] & reg_we & !reg_error;
+  assign loc_alert_regwen_0_we = addr_hit[238] & reg_we & !reg_error;
 
   assign loc_alert_regwen_0_wd = reg_wdata[0];
-  assign loc_alert_regwen_1_we = addr_hit[247] & reg_we & !reg_error;
+  assign loc_alert_regwen_1_we = addr_hit[239] & reg_we & !reg_error;
 
   assign loc_alert_regwen_1_wd = reg_wdata[0];
-  assign loc_alert_regwen_2_we = addr_hit[248] & reg_we & !reg_error;
+  assign loc_alert_regwen_2_we = addr_hit[240] & reg_we & !reg_error;
 
   assign loc_alert_regwen_2_wd = reg_wdata[0];
-  assign loc_alert_regwen_3_we = addr_hit[249] & reg_we & !reg_error;
+  assign loc_alert_regwen_3_we = addr_hit[241] & reg_we & !reg_error;
 
   assign loc_alert_regwen_3_wd = reg_wdata[0];
-  assign loc_alert_regwen_4_we = addr_hit[250] & reg_we & !reg_error;
+  assign loc_alert_regwen_4_we = addr_hit[242] & reg_we & !reg_error;
 
   assign loc_alert_regwen_4_wd = reg_wdata[0];
-  assign loc_alert_regwen_5_we = addr_hit[251] & reg_we & !reg_error;
+  assign loc_alert_regwen_5_we = addr_hit[243] & reg_we & !reg_error;
 
   assign loc_alert_regwen_5_wd = reg_wdata[0];
-  assign loc_alert_regwen_6_we = addr_hit[252] & reg_we & !reg_error;
+  assign loc_alert_regwen_6_we = addr_hit[244] & reg_we & !reg_error;
 
   assign loc_alert_regwen_6_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_0_re = addr_hit[253] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_0_we = addr_hit[253] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_0_re = addr_hit[245] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_0_we = addr_hit[245] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_0_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_1_re = addr_hit[254] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_1_we = addr_hit[254] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_1_re = addr_hit[246] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_1_we = addr_hit[246] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_1_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_2_re = addr_hit[255] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_2_we = addr_hit[255] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_2_re = addr_hit[247] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_2_we = addr_hit[247] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_2_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_3_re = addr_hit[256] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_3_we = addr_hit[256] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_3_re = addr_hit[248] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_3_we = addr_hit[248] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_3_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_4_re = addr_hit[257] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_4_we = addr_hit[257] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_4_re = addr_hit[249] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_4_we = addr_hit[249] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_4_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_5_re = addr_hit[258] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_5_we = addr_hit[258] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_5_re = addr_hit[250] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_5_we = addr_hit[250] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_5_wd = reg_wdata[0];
-  assign loc_alert_en_shadowed_6_re = addr_hit[259] & reg_re & !reg_error;
-  assign loc_alert_en_shadowed_6_we = addr_hit[259] & reg_we & !reg_error;
+  assign loc_alert_en_shadowed_6_re = addr_hit[251] & reg_re & !reg_error;
+  assign loc_alert_en_shadowed_6_we = addr_hit[251] & reg_we & !reg_error;
 
   assign loc_alert_en_shadowed_6_wd = reg_wdata[0];
-  assign loc_alert_class_shadowed_0_re = addr_hit[260] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_0_we = addr_hit[260] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_0_re = addr_hit[252] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_0_we = addr_hit[252] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_1_re = addr_hit[261] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_1_we = addr_hit[261] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_1_re = addr_hit[253] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_1_we = addr_hit[253] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_2_re = addr_hit[262] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_2_we = addr_hit[262] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_2_re = addr_hit[254] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_2_we = addr_hit[254] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_3_re = addr_hit[263] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_3_we = addr_hit[263] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_3_re = addr_hit[255] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_3_we = addr_hit[255] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_4_re = addr_hit[264] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_4_we = addr_hit[264] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_4_re = addr_hit[256] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_4_we = addr_hit[256] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_5_re = addr_hit[265] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_5_we = addr_hit[265] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_5_re = addr_hit[257] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_5_we = addr_hit[257] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0];
-  assign loc_alert_class_shadowed_6_re = addr_hit[266] & reg_re & !reg_error;
-  assign loc_alert_class_shadowed_6_we = addr_hit[266] & reg_we & !reg_error;
+  assign loc_alert_class_shadowed_6_re = addr_hit[258] & reg_re & !reg_error;
+  assign loc_alert_class_shadowed_6_we = addr_hit[258] & reg_we & !reg_error;
 
   assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0];
-  assign loc_alert_cause_0_we = addr_hit[267] & reg_we & !reg_error;
+  assign loc_alert_cause_0_we = addr_hit[259] & reg_we & !reg_error;
 
   assign loc_alert_cause_0_wd = reg_wdata[0];
-  assign loc_alert_cause_1_we = addr_hit[268] & reg_we & !reg_error;
+  assign loc_alert_cause_1_we = addr_hit[260] & reg_we & !reg_error;
 
   assign loc_alert_cause_1_wd = reg_wdata[0];
-  assign loc_alert_cause_2_we = addr_hit[269] & reg_we & !reg_error;
+  assign loc_alert_cause_2_we = addr_hit[261] & reg_we & !reg_error;
 
   assign loc_alert_cause_2_wd = reg_wdata[0];
-  assign loc_alert_cause_3_we = addr_hit[270] & reg_we & !reg_error;
+  assign loc_alert_cause_3_we = addr_hit[262] & reg_we & !reg_error;
 
   assign loc_alert_cause_3_wd = reg_wdata[0];
-  assign loc_alert_cause_4_we = addr_hit[271] & reg_we & !reg_error;
+  assign loc_alert_cause_4_we = addr_hit[263] & reg_we & !reg_error;
 
   assign loc_alert_cause_4_wd = reg_wdata[0];
-  assign loc_alert_cause_5_we = addr_hit[272] & reg_we & !reg_error;
+  assign loc_alert_cause_5_we = addr_hit[264] & reg_we & !reg_error;
 
   assign loc_alert_cause_5_wd = reg_wdata[0];
-  assign loc_alert_cause_6_we = addr_hit[273] & reg_we & !reg_error;
+  assign loc_alert_cause_6_we = addr_hit[265] & reg_we & !reg_error;
 
   assign loc_alert_cause_6_wd = reg_wdata[0];
-  assign classa_regwen_we = addr_hit[274] & reg_we & !reg_error;
+  assign classa_regwen_we = addr_hit[266] & reg_we & !reg_error;
 
   assign classa_regwen_wd = reg_wdata[0];
-  assign classa_ctrl_shadowed_re = addr_hit[275] & reg_re & !reg_error;
-  assign classa_ctrl_shadowed_we = addr_hit[275] & reg_we & !reg_error;
+  assign classa_ctrl_shadowed_re = addr_hit[267] & reg_re & !reg_error;
+  assign classa_ctrl_shadowed_we = addr_hit[267] & reg_we & !reg_error;
 
   assign classa_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -14072,49 +13760,49 @@
   assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classa_clr_regwen_we = addr_hit[276] & reg_we & !reg_error;
+  assign classa_clr_regwen_we = addr_hit[268] & reg_we & !reg_error;
 
   assign classa_clr_regwen_wd = reg_wdata[0];
-  assign classa_clr_shadowed_re = addr_hit[277] & reg_re & !reg_error;
-  assign classa_clr_shadowed_we = addr_hit[277] & reg_we & !reg_error;
+  assign classa_clr_shadowed_re = addr_hit[269] & reg_re & !reg_error;
+  assign classa_clr_shadowed_we = addr_hit[269] & reg_we & !reg_error;
 
   assign classa_clr_shadowed_wd = reg_wdata[0];
-  assign classa_accum_cnt_re = addr_hit[278] & reg_re & !reg_error;
-  assign classa_accum_thresh_shadowed_re = addr_hit[279] & reg_re & !reg_error;
-  assign classa_accum_thresh_shadowed_we = addr_hit[279] & reg_we & !reg_error;
+  assign classa_accum_cnt_re = addr_hit[270] & reg_re & !reg_error;
+  assign classa_accum_thresh_shadowed_re = addr_hit[271] & reg_re & !reg_error;
+  assign classa_accum_thresh_shadowed_we = addr_hit[271] & reg_we & !reg_error;
 
   assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classa_timeout_cyc_shadowed_re = addr_hit[280] & reg_re & !reg_error;
-  assign classa_timeout_cyc_shadowed_we = addr_hit[280] & reg_we & !reg_error;
+  assign classa_timeout_cyc_shadowed_re = addr_hit[272] & reg_re & !reg_error;
+  assign classa_timeout_cyc_shadowed_we = addr_hit[272] & reg_we & !reg_error;
 
   assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_crashdump_trigger_shadowed_re = addr_hit[281] & reg_re & !reg_error;
-  assign classa_crashdump_trigger_shadowed_we = addr_hit[281] & reg_we & !reg_error;
+  assign classa_crashdump_trigger_shadowed_re = addr_hit[273] & reg_re & !reg_error;
+  assign classa_crashdump_trigger_shadowed_we = addr_hit[273] & reg_we & !reg_error;
 
   assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classa_phase0_cyc_shadowed_re = addr_hit[282] & reg_re & !reg_error;
-  assign classa_phase0_cyc_shadowed_we = addr_hit[282] & reg_we & !reg_error;
+  assign classa_phase0_cyc_shadowed_re = addr_hit[274] & reg_re & !reg_error;
+  assign classa_phase0_cyc_shadowed_we = addr_hit[274] & reg_we & !reg_error;
 
   assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_phase1_cyc_shadowed_re = addr_hit[283] & reg_re & !reg_error;
-  assign classa_phase1_cyc_shadowed_we = addr_hit[283] & reg_we & !reg_error;
+  assign classa_phase1_cyc_shadowed_re = addr_hit[275] & reg_re & !reg_error;
+  assign classa_phase1_cyc_shadowed_we = addr_hit[275] & reg_we & !reg_error;
 
   assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_phase2_cyc_shadowed_re = addr_hit[284] & reg_re & !reg_error;
-  assign classa_phase2_cyc_shadowed_we = addr_hit[284] & reg_we & !reg_error;
+  assign classa_phase2_cyc_shadowed_re = addr_hit[276] & reg_re & !reg_error;
+  assign classa_phase2_cyc_shadowed_we = addr_hit[276] & reg_we & !reg_error;
 
   assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_phase3_cyc_shadowed_re = addr_hit[285] & reg_re & !reg_error;
-  assign classa_phase3_cyc_shadowed_we = addr_hit[285] & reg_we & !reg_error;
+  assign classa_phase3_cyc_shadowed_re = addr_hit[277] & reg_re & !reg_error;
+  assign classa_phase3_cyc_shadowed_we = addr_hit[277] & reg_we & !reg_error;
 
   assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classa_esc_cnt_re = addr_hit[286] & reg_re & !reg_error;
-  assign classa_state_re = addr_hit[287] & reg_re & !reg_error;
-  assign classb_regwen_we = addr_hit[288] & reg_we & !reg_error;
+  assign classa_esc_cnt_re = addr_hit[278] & reg_re & !reg_error;
+  assign classa_state_re = addr_hit[279] & reg_re & !reg_error;
+  assign classb_regwen_we = addr_hit[280] & reg_we & !reg_error;
 
   assign classb_regwen_wd = reg_wdata[0];
-  assign classb_ctrl_shadowed_re = addr_hit[289] & reg_re & !reg_error;
-  assign classb_ctrl_shadowed_we = addr_hit[289] & reg_we & !reg_error;
+  assign classb_ctrl_shadowed_re = addr_hit[281] & reg_re & !reg_error;
+  assign classb_ctrl_shadowed_we = addr_hit[281] & reg_we & !reg_error;
 
   assign classb_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -14135,49 +13823,49 @@
   assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classb_clr_regwen_we = addr_hit[290] & reg_we & !reg_error;
+  assign classb_clr_regwen_we = addr_hit[282] & reg_we & !reg_error;
 
   assign classb_clr_regwen_wd = reg_wdata[0];
-  assign classb_clr_shadowed_re = addr_hit[291] & reg_re & !reg_error;
-  assign classb_clr_shadowed_we = addr_hit[291] & reg_we & !reg_error;
+  assign classb_clr_shadowed_re = addr_hit[283] & reg_re & !reg_error;
+  assign classb_clr_shadowed_we = addr_hit[283] & reg_we & !reg_error;
 
   assign classb_clr_shadowed_wd = reg_wdata[0];
-  assign classb_accum_cnt_re = addr_hit[292] & reg_re & !reg_error;
-  assign classb_accum_thresh_shadowed_re = addr_hit[293] & reg_re & !reg_error;
-  assign classb_accum_thresh_shadowed_we = addr_hit[293] & reg_we & !reg_error;
+  assign classb_accum_cnt_re = addr_hit[284] & reg_re & !reg_error;
+  assign classb_accum_thresh_shadowed_re = addr_hit[285] & reg_re & !reg_error;
+  assign classb_accum_thresh_shadowed_we = addr_hit[285] & reg_we & !reg_error;
 
   assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classb_timeout_cyc_shadowed_re = addr_hit[294] & reg_re & !reg_error;
-  assign classb_timeout_cyc_shadowed_we = addr_hit[294] & reg_we & !reg_error;
+  assign classb_timeout_cyc_shadowed_re = addr_hit[286] & reg_re & !reg_error;
+  assign classb_timeout_cyc_shadowed_we = addr_hit[286] & reg_we & !reg_error;
 
   assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_crashdump_trigger_shadowed_re = addr_hit[295] & reg_re & !reg_error;
-  assign classb_crashdump_trigger_shadowed_we = addr_hit[295] & reg_we & !reg_error;
+  assign classb_crashdump_trigger_shadowed_re = addr_hit[287] & reg_re & !reg_error;
+  assign classb_crashdump_trigger_shadowed_we = addr_hit[287] & reg_we & !reg_error;
 
   assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classb_phase0_cyc_shadowed_re = addr_hit[296] & reg_re & !reg_error;
-  assign classb_phase0_cyc_shadowed_we = addr_hit[296] & reg_we & !reg_error;
+  assign classb_phase0_cyc_shadowed_re = addr_hit[288] & reg_re & !reg_error;
+  assign classb_phase0_cyc_shadowed_we = addr_hit[288] & reg_we & !reg_error;
 
   assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_phase1_cyc_shadowed_re = addr_hit[297] & reg_re & !reg_error;
-  assign classb_phase1_cyc_shadowed_we = addr_hit[297] & reg_we & !reg_error;
+  assign classb_phase1_cyc_shadowed_re = addr_hit[289] & reg_re & !reg_error;
+  assign classb_phase1_cyc_shadowed_we = addr_hit[289] & reg_we & !reg_error;
 
   assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_phase2_cyc_shadowed_re = addr_hit[298] & reg_re & !reg_error;
-  assign classb_phase2_cyc_shadowed_we = addr_hit[298] & reg_we & !reg_error;
+  assign classb_phase2_cyc_shadowed_re = addr_hit[290] & reg_re & !reg_error;
+  assign classb_phase2_cyc_shadowed_we = addr_hit[290] & reg_we & !reg_error;
 
   assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_phase3_cyc_shadowed_re = addr_hit[299] & reg_re & !reg_error;
-  assign classb_phase3_cyc_shadowed_we = addr_hit[299] & reg_we & !reg_error;
+  assign classb_phase3_cyc_shadowed_re = addr_hit[291] & reg_re & !reg_error;
+  assign classb_phase3_cyc_shadowed_we = addr_hit[291] & reg_we & !reg_error;
 
   assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classb_esc_cnt_re = addr_hit[300] & reg_re & !reg_error;
-  assign classb_state_re = addr_hit[301] & reg_re & !reg_error;
-  assign classc_regwen_we = addr_hit[302] & reg_we & !reg_error;
+  assign classb_esc_cnt_re = addr_hit[292] & reg_re & !reg_error;
+  assign classb_state_re = addr_hit[293] & reg_re & !reg_error;
+  assign classc_regwen_we = addr_hit[294] & reg_we & !reg_error;
 
   assign classc_regwen_wd = reg_wdata[0];
-  assign classc_ctrl_shadowed_re = addr_hit[303] & reg_re & !reg_error;
-  assign classc_ctrl_shadowed_we = addr_hit[303] & reg_we & !reg_error;
+  assign classc_ctrl_shadowed_re = addr_hit[295] & reg_re & !reg_error;
+  assign classc_ctrl_shadowed_we = addr_hit[295] & reg_we & !reg_error;
 
   assign classc_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -14198,49 +13886,49 @@
   assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classc_clr_regwen_we = addr_hit[304] & reg_we & !reg_error;
+  assign classc_clr_regwen_we = addr_hit[296] & reg_we & !reg_error;
 
   assign classc_clr_regwen_wd = reg_wdata[0];
-  assign classc_clr_shadowed_re = addr_hit[305] & reg_re & !reg_error;
-  assign classc_clr_shadowed_we = addr_hit[305] & reg_we & !reg_error;
+  assign classc_clr_shadowed_re = addr_hit[297] & reg_re & !reg_error;
+  assign classc_clr_shadowed_we = addr_hit[297] & reg_we & !reg_error;
 
   assign classc_clr_shadowed_wd = reg_wdata[0];
-  assign classc_accum_cnt_re = addr_hit[306] & reg_re & !reg_error;
-  assign classc_accum_thresh_shadowed_re = addr_hit[307] & reg_re & !reg_error;
-  assign classc_accum_thresh_shadowed_we = addr_hit[307] & reg_we & !reg_error;
+  assign classc_accum_cnt_re = addr_hit[298] & reg_re & !reg_error;
+  assign classc_accum_thresh_shadowed_re = addr_hit[299] & reg_re & !reg_error;
+  assign classc_accum_thresh_shadowed_we = addr_hit[299] & reg_we & !reg_error;
 
   assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classc_timeout_cyc_shadowed_re = addr_hit[308] & reg_re & !reg_error;
-  assign classc_timeout_cyc_shadowed_we = addr_hit[308] & reg_we & !reg_error;
+  assign classc_timeout_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error;
+  assign classc_timeout_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error;
 
   assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_crashdump_trigger_shadowed_re = addr_hit[309] & reg_re & !reg_error;
-  assign classc_crashdump_trigger_shadowed_we = addr_hit[309] & reg_we & !reg_error;
+  assign classc_crashdump_trigger_shadowed_re = addr_hit[301] & reg_re & !reg_error;
+  assign classc_crashdump_trigger_shadowed_we = addr_hit[301] & reg_we & !reg_error;
 
   assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classc_phase0_cyc_shadowed_re = addr_hit[310] & reg_re & !reg_error;
-  assign classc_phase0_cyc_shadowed_we = addr_hit[310] & reg_we & !reg_error;
+  assign classc_phase0_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error;
+  assign classc_phase0_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error;
 
   assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_phase1_cyc_shadowed_re = addr_hit[311] & reg_re & !reg_error;
-  assign classc_phase1_cyc_shadowed_we = addr_hit[311] & reg_we & !reg_error;
+  assign classc_phase1_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error;
+  assign classc_phase1_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error;
 
   assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_phase2_cyc_shadowed_re = addr_hit[312] & reg_re & !reg_error;
-  assign classc_phase2_cyc_shadowed_we = addr_hit[312] & reg_we & !reg_error;
+  assign classc_phase2_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error;
+  assign classc_phase2_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error;
 
   assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_phase3_cyc_shadowed_re = addr_hit[313] & reg_re & !reg_error;
-  assign classc_phase3_cyc_shadowed_we = addr_hit[313] & reg_we & !reg_error;
+  assign classc_phase3_cyc_shadowed_re = addr_hit[305] & reg_re & !reg_error;
+  assign classc_phase3_cyc_shadowed_we = addr_hit[305] & reg_we & !reg_error;
 
   assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classc_esc_cnt_re = addr_hit[314] & reg_re & !reg_error;
-  assign classc_state_re = addr_hit[315] & reg_re & !reg_error;
-  assign classd_regwen_we = addr_hit[316] & reg_we & !reg_error;
+  assign classc_esc_cnt_re = addr_hit[306] & reg_re & !reg_error;
+  assign classc_state_re = addr_hit[307] & reg_re & !reg_error;
+  assign classd_regwen_we = addr_hit[308] & reg_we & !reg_error;
 
   assign classd_regwen_wd = reg_wdata[0];
-  assign classd_ctrl_shadowed_re = addr_hit[317] & reg_re & !reg_error;
-  assign classd_ctrl_shadowed_we = addr_hit[317] & reg_we & !reg_error;
+  assign classd_ctrl_shadowed_re = addr_hit[309] & reg_re & !reg_error;
+  assign classd_ctrl_shadowed_we = addr_hit[309] & reg_we & !reg_error;
 
   assign classd_ctrl_shadowed_en_wd = reg_wdata[0];
 
@@ -14261,44 +13949,44 @@
   assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
 
   assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
-  assign classd_clr_regwen_we = addr_hit[318] & reg_we & !reg_error;
+  assign classd_clr_regwen_we = addr_hit[310] & reg_we & !reg_error;
 
   assign classd_clr_regwen_wd = reg_wdata[0];
-  assign classd_clr_shadowed_re = addr_hit[319] & reg_re & !reg_error;
-  assign classd_clr_shadowed_we = addr_hit[319] & reg_we & !reg_error;
+  assign classd_clr_shadowed_re = addr_hit[311] & reg_re & !reg_error;
+  assign classd_clr_shadowed_we = addr_hit[311] & reg_we & !reg_error;
 
   assign classd_clr_shadowed_wd = reg_wdata[0];
-  assign classd_accum_cnt_re = addr_hit[320] & reg_re & !reg_error;
-  assign classd_accum_thresh_shadowed_re = addr_hit[321] & reg_re & !reg_error;
-  assign classd_accum_thresh_shadowed_we = addr_hit[321] & reg_we & !reg_error;
+  assign classd_accum_cnt_re = addr_hit[312] & reg_re & !reg_error;
+  assign classd_accum_thresh_shadowed_re = addr_hit[313] & reg_re & !reg_error;
+  assign classd_accum_thresh_shadowed_we = addr_hit[313] & reg_we & !reg_error;
 
   assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0];
-  assign classd_timeout_cyc_shadowed_re = addr_hit[322] & reg_re & !reg_error;
-  assign classd_timeout_cyc_shadowed_we = addr_hit[322] & reg_we & !reg_error;
+  assign classd_timeout_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error;
+  assign classd_timeout_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error;
 
   assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_crashdump_trigger_shadowed_re = addr_hit[323] & reg_re & !reg_error;
-  assign classd_crashdump_trigger_shadowed_we = addr_hit[323] & reg_we & !reg_error;
+  assign classd_crashdump_trigger_shadowed_re = addr_hit[315] & reg_re & !reg_error;
+  assign classd_crashdump_trigger_shadowed_we = addr_hit[315] & reg_we & !reg_error;
 
   assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
-  assign classd_phase0_cyc_shadowed_re = addr_hit[324] & reg_re & !reg_error;
-  assign classd_phase0_cyc_shadowed_we = addr_hit[324] & reg_we & !reg_error;
+  assign classd_phase0_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error;
+  assign classd_phase0_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error;
 
   assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_phase1_cyc_shadowed_re = addr_hit[325] & reg_re & !reg_error;
-  assign classd_phase1_cyc_shadowed_we = addr_hit[325] & reg_we & !reg_error;
+  assign classd_phase1_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error;
+  assign classd_phase1_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error;
 
   assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_phase2_cyc_shadowed_re = addr_hit[326] & reg_re & !reg_error;
-  assign classd_phase2_cyc_shadowed_we = addr_hit[326] & reg_we & !reg_error;
+  assign classd_phase2_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error;
+  assign classd_phase2_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error;
 
   assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_phase3_cyc_shadowed_re = addr_hit[327] & reg_re & !reg_error;
-  assign classd_phase3_cyc_shadowed_we = addr_hit[327] & reg_we & !reg_error;
+  assign classd_phase3_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error;
+  assign classd_phase3_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error;
 
   assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0];
-  assign classd_esc_cnt_re = addr_hit[328] & reg_re & !reg_error;
-  assign classd_state_re = addr_hit[329] & reg_re & !reg_error;
+  assign classd_esc_cnt_re = addr_hit[320] & reg_re & !reg_error;
+  assign classd_state_re = addr_hit[321] & reg_re & !reg_error;
 
   // Read data return
   always_comb begin
@@ -14570,850 +14258,818 @@
       end
 
       addr_hit[64]: begin
-        reg_rdata_next[0] = alert_regwen_58_qs;
-      end
-
-      addr_hit[65]: begin
-        reg_rdata_next[0] = alert_regwen_59_qs;
-      end
-
-      addr_hit[66]: begin
         reg_rdata_next[0] = alert_en_shadowed_0_qs;
       end
 
-      addr_hit[67]: begin
+      addr_hit[65]: begin
         reg_rdata_next[0] = alert_en_shadowed_1_qs;
       end
 
-      addr_hit[68]: begin
+      addr_hit[66]: begin
         reg_rdata_next[0] = alert_en_shadowed_2_qs;
       end
 
-      addr_hit[69]: begin
+      addr_hit[67]: begin
         reg_rdata_next[0] = alert_en_shadowed_3_qs;
       end
 
-      addr_hit[70]: begin
+      addr_hit[68]: begin
         reg_rdata_next[0] = alert_en_shadowed_4_qs;
       end
 
-      addr_hit[71]: begin
+      addr_hit[69]: begin
         reg_rdata_next[0] = alert_en_shadowed_5_qs;
       end
 
-      addr_hit[72]: begin
+      addr_hit[70]: begin
         reg_rdata_next[0] = alert_en_shadowed_6_qs;
       end
 
-      addr_hit[73]: begin
+      addr_hit[71]: begin
         reg_rdata_next[0] = alert_en_shadowed_7_qs;
       end
 
-      addr_hit[74]: begin
+      addr_hit[72]: begin
         reg_rdata_next[0] = alert_en_shadowed_8_qs;
       end
 
-      addr_hit[75]: begin
+      addr_hit[73]: begin
         reg_rdata_next[0] = alert_en_shadowed_9_qs;
       end
 
-      addr_hit[76]: begin
+      addr_hit[74]: begin
         reg_rdata_next[0] = alert_en_shadowed_10_qs;
       end
 
-      addr_hit[77]: begin
+      addr_hit[75]: begin
         reg_rdata_next[0] = alert_en_shadowed_11_qs;
       end
 
-      addr_hit[78]: begin
+      addr_hit[76]: begin
         reg_rdata_next[0] = alert_en_shadowed_12_qs;
       end
 
-      addr_hit[79]: begin
+      addr_hit[77]: begin
         reg_rdata_next[0] = alert_en_shadowed_13_qs;
       end
 
-      addr_hit[80]: begin
+      addr_hit[78]: begin
         reg_rdata_next[0] = alert_en_shadowed_14_qs;
       end
 
-      addr_hit[81]: begin
+      addr_hit[79]: begin
         reg_rdata_next[0] = alert_en_shadowed_15_qs;
       end
 
-      addr_hit[82]: begin
+      addr_hit[80]: begin
         reg_rdata_next[0] = alert_en_shadowed_16_qs;
       end
 
-      addr_hit[83]: begin
+      addr_hit[81]: begin
         reg_rdata_next[0] = alert_en_shadowed_17_qs;
       end
 
-      addr_hit[84]: begin
+      addr_hit[82]: begin
         reg_rdata_next[0] = alert_en_shadowed_18_qs;
       end
 
-      addr_hit[85]: begin
+      addr_hit[83]: begin
         reg_rdata_next[0] = alert_en_shadowed_19_qs;
       end
 
-      addr_hit[86]: begin
+      addr_hit[84]: begin
         reg_rdata_next[0] = alert_en_shadowed_20_qs;
       end
 
-      addr_hit[87]: begin
+      addr_hit[85]: begin
         reg_rdata_next[0] = alert_en_shadowed_21_qs;
       end
 
-      addr_hit[88]: begin
+      addr_hit[86]: begin
         reg_rdata_next[0] = alert_en_shadowed_22_qs;
       end
 
-      addr_hit[89]: begin
+      addr_hit[87]: begin
         reg_rdata_next[0] = alert_en_shadowed_23_qs;
       end
 
-      addr_hit[90]: begin
+      addr_hit[88]: begin
         reg_rdata_next[0] = alert_en_shadowed_24_qs;
       end
 
-      addr_hit[91]: begin
+      addr_hit[89]: begin
         reg_rdata_next[0] = alert_en_shadowed_25_qs;
       end
 
-      addr_hit[92]: begin
+      addr_hit[90]: begin
         reg_rdata_next[0] = alert_en_shadowed_26_qs;
       end
 
-      addr_hit[93]: begin
+      addr_hit[91]: begin
         reg_rdata_next[0] = alert_en_shadowed_27_qs;
       end
 
-      addr_hit[94]: begin
+      addr_hit[92]: begin
         reg_rdata_next[0] = alert_en_shadowed_28_qs;
       end
 
-      addr_hit[95]: begin
+      addr_hit[93]: begin
         reg_rdata_next[0] = alert_en_shadowed_29_qs;
       end
 
-      addr_hit[96]: begin
+      addr_hit[94]: begin
         reg_rdata_next[0] = alert_en_shadowed_30_qs;
       end
 
-      addr_hit[97]: begin
+      addr_hit[95]: begin
         reg_rdata_next[0] = alert_en_shadowed_31_qs;
       end
 
-      addr_hit[98]: begin
+      addr_hit[96]: begin
         reg_rdata_next[0] = alert_en_shadowed_32_qs;
       end
 
-      addr_hit[99]: begin
+      addr_hit[97]: begin
         reg_rdata_next[0] = alert_en_shadowed_33_qs;
       end
 
-      addr_hit[100]: begin
+      addr_hit[98]: begin
         reg_rdata_next[0] = alert_en_shadowed_34_qs;
       end
 
-      addr_hit[101]: begin
+      addr_hit[99]: begin
         reg_rdata_next[0] = alert_en_shadowed_35_qs;
       end
 
-      addr_hit[102]: begin
+      addr_hit[100]: begin
         reg_rdata_next[0] = alert_en_shadowed_36_qs;
       end
 
-      addr_hit[103]: begin
+      addr_hit[101]: begin
         reg_rdata_next[0] = alert_en_shadowed_37_qs;
       end
 
-      addr_hit[104]: begin
+      addr_hit[102]: begin
         reg_rdata_next[0] = alert_en_shadowed_38_qs;
       end
 
-      addr_hit[105]: begin
+      addr_hit[103]: begin
         reg_rdata_next[0] = alert_en_shadowed_39_qs;
       end
 
-      addr_hit[106]: begin
+      addr_hit[104]: begin
         reg_rdata_next[0] = alert_en_shadowed_40_qs;
       end
 
-      addr_hit[107]: begin
+      addr_hit[105]: begin
         reg_rdata_next[0] = alert_en_shadowed_41_qs;
       end
 
-      addr_hit[108]: begin
+      addr_hit[106]: begin
         reg_rdata_next[0] = alert_en_shadowed_42_qs;
       end
 
-      addr_hit[109]: begin
+      addr_hit[107]: begin
         reg_rdata_next[0] = alert_en_shadowed_43_qs;
       end
 
-      addr_hit[110]: begin
+      addr_hit[108]: begin
         reg_rdata_next[0] = alert_en_shadowed_44_qs;
       end
 
-      addr_hit[111]: begin
+      addr_hit[109]: begin
         reg_rdata_next[0] = alert_en_shadowed_45_qs;
       end
 
-      addr_hit[112]: begin
+      addr_hit[110]: begin
         reg_rdata_next[0] = alert_en_shadowed_46_qs;
       end
 
-      addr_hit[113]: begin
+      addr_hit[111]: begin
         reg_rdata_next[0] = alert_en_shadowed_47_qs;
       end
 
-      addr_hit[114]: begin
+      addr_hit[112]: begin
         reg_rdata_next[0] = alert_en_shadowed_48_qs;
       end
 
-      addr_hit[115]: begin
+      addr_hit[113]: begin
         reg_rdata_next[0] = alert_en_shadowed_49_qs;
       end
 
-      addr_hit[116]: begin
+      addr_hit[114]: begin
         reg_rdata_next[0] = alert_en_shadowed_50_qs;
       end
 
-      addr_hit[117]: begin
+      addr_hit[115]: begin
         reg_rdata_next[0] = alert_en_shadowed_51_qs;
       end
 
-      addr_hit[118]: begin
+      addr_hit[116]: begin
         reg_rdata_next[0] = alert_en_shadowed_52_qs;
       end
 
-      addr_hit[119]: begin
+      addr_hit[117]: begin
         reg_rdata_next[0] = alert_en_shadowed_53_qs;
       end
 
-      addr_hit[120]: begin
+      addr_hit[118]: begin
         reg_rdata_next[0] = alert_en_shadowed_54_qs;
       end
 
-      addr_hit[121]: begin
+      addr_hit[119]: begin
         reg_rdata_next[0] = alert_en_shadowed_55_qs;
       end
 
-      addr_hit[122]: begin
+      addr_hit[120]: begin
         reg_rdata_next[0] = alert_en_shadowed_56_qs;
       end
 
-      addr_hit[123]: begin
+      addr_hit[121]: begin
         reg_rdata_next[0] = alert_en_shadowed_57_qs;
       end
 
-      addr_hit[124]: begin
-        reg_rdata_next[0] = alert_en_shadowed_58_qs;
-      end
-
-      addr_hit[125]: begin
-        reg_rdata_next[0] = alert_en_shadowed_59_qs;
-      end
-
-      addr_hit[126]: begin
+      addr_hit[122]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
       end
 
-      addr_hit[127]: begin
+      addr_hit[123]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
       end
 
-      addr_hit[128]: begin
+      addr_hit[124]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
       end
 
-      addr_hit[129]: begin
+      addr_hit[125]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
       end
 
-      addr_hit[130]: begin
+      addr_hit[126]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
       end
 
-      addr_hit[131]: begin
+      addr_hit[127]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
       end
 
-      addr_hit[132]: begin
+      addr_hit[128]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
       end
 
-      addr_hit[133]: begin
+      addr_hit[129]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
       end
 
-      addr_hit[134]: begin
+      addr_hit[130]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
       end
 
-      addr_hit[135]: begin
+      addr_hit[131]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
       end
 
-      addr_hit[136]: begin
+      addr_hit[132]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
       end
 
-      addr_hit[137]: begin
+      addr_hit[133]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
       end
 
-      addr_hit[138]: begin
+      addr_hit[134]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
       end
 
-      addr_hit[139]: begin
+      addr_hit[135]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
       end
 
-      addr_hit[140]: begin
+      addr_hit[136]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
       end
 
-      addr_hit[141]: begin
+      addr_hit[137]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
       end
 
-      addr_hit[142]: begin
+      addr_hit[138]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
       end
 
-      addr_hit[143]: begin
+      addr_hit[139]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
       end
 
-      addr_hit[144]: begin
+      addr_hit[140]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
       end
 
-      addr_hit[145]: begin
+      addr_hit[141]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
       end
 
-      addr_hit[146]: begin
+      addr_hit[142]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
       end
 
-      addr_hit[147]: begin
+      addr_hit[143]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
       end
 
-      addr_hit[148]: begin
+      addr_hit[144]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
       end
 
-      addr_hit[149]: begin
+      addr_hit[145]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
       end
 
-      addr_hit[150]: begin
+      addr_hit[146]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
       end
 
-      addr_hit[151]: begin
+      addr_hit[147]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
       end
 
-      addr_hit[152]: begin
+      addr_hit[148]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
       end
 
-      addr_hit[153]: begin
+      addr_hit[149]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
       end
 
-      addr_hit[154]: begin
+      addr_hit[150]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
       end
 
-      addr_hit[155]: begin
+      addr_hit[151]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
       end
 
-      addr_hit[156]: begin
+      addr_hit[152]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
       end
 
-      addr_hit[157]: begin
+      addr_hit[153]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
       end
 
-      addr_hit[158]: begin
+      addr_hit[154]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
       end
 
-      addr_hit[159]: begin
+      addr_hit[155]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
       end
 
-      addr_hit[160]: begin
+      addr_hit[156]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
       end
 
-      addr_hit[161]: begin
+      addr_hit[157]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
       end
 
-      addr_hit[162]: begin
+      addr_hit[158]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
       end
 
-      addr_hit[163]: begin
+      addr_hit[159]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
       end
 
-      addr_hit[164]: begin
+      addr_hit[160]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
       end
 
-      addr_hit[165]: begin
+      addr_hit[161]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
       end
 
-      addr_hit[166]: begin
+      addr_hit[162]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
       end
 
-      addr_hit[167]: begin
+      addr_hit[163]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
       end
 
-      addr_hit[168]: begin
+      addr_hit[164]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
       end
 
-      addr_hit[169]: begin
+      addr_hit[165]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
       end
 
-      addr_hit[170]: begin
+      addr_hit[166]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
       end
 
-      addr_hit[171]: begin
+      addr_hit[167]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
       end
 
-      addr_hit[172]: begin
+      addr_hit[168]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
       end
 
-      addr_hit[173]: begin
+      addr_hit[169]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
       end
 
-      addr_hit[174]: begin
+      addr_hit[170]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
       end
 
-      addr_hit[175]: begin
+      addr_hit[171]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
       end
 
-      addr_hit[176]: begin
+      addr_hit[172]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
       end
 
-      addr_hit[177]: begin
+      addr_hit[173]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
       end
 
-      addr_hit[178]: begin
+      addr_hit[174]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
       end
 
-      addr_hit[179]: begin
+      addr_hit[175]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
       end
 
-      addr_hit[180]: begin
+      addr_hit[176]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
       end
 
-      addr_hit[181]: begin
+      addr_hit[177]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
       end
 
-      addr_hit[182]: begin
+      addr_hit[178]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
       end
 
-      addr_hit[183]: begin
+      addr_hit[179]: begin
         reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
       end
 
-      addr_hit[184]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
-      end
-
-      addr_hit[185]: begin
-        reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
-      end
-
-      addr_hit[186]: begin
+      addr_hit[180]: begin
         reg_rdata_next[0] = alert_cause_0_qs;
       end
 
-      addr_hit[187]: begin
+      addr_hit[181]: begin
         reg_rdata_next[0] = alert_cause_1_qs;
       end
 
-      addr_hit[188]: begin
+      addr_hit[182]: begin
         reg_rdata_next[0] = alert_cause_2_qs;
       end
 
-      addr_hit[189]: begin
+      addr_hit[183]: begin
         reg_rdata_next[0] = alert_cause_3_qs;
       end
 
-      addr_hit[190]: begin
+      addr_hit[184]: begin
         reg_rdata_next[0] = alert_cause_4_qs;
       end
 
-      addr_hit[191]: begin
+      addr_hit[185]: begin
         reg_rdata_next[0] = alert_cause_5_qs;
       end
 
-      addr_hit[192]: begin
+      addr_hit[186]: begin
         reg_rdata_next[0] = alert_cause_6_qs;
       end
 
-      addr_hit[193]: begin
+      addr_hit[187]: begin
         reg_rdata_next[0] = alert_cause_7_qs;
       end
 
-      addr_hit[194]: begin
+      addr_hit[188]: begin
         reg_rdata_next[0] = alert_cause_8_qs;
       end
 
-      addr_hit[195]: begin
+      addr_hit[189]: begin
         reg_rdata_next[0] = alert_cause_9_qs;
       end
 
-      addr_hit[196]: begin
+      addr_hit[190]: begin
         reg_rdata_next[0] = alert_cause_10_qs;
       end
 
-      addr_hit[197]: begin
+      addr_hit[191]: begin
         reg_rdata_next[0] = alert_cause_11_qs;
       end
 
-      addr_hit[198]: begin
+      addr_hit[192]: begin
         reg_rdata_next[0] = alert_cause_12_qs;
       end
 
-      addr_hit[199]: begin
+      addr_hit[193]: begin
         reg_rdata_next[0] = alert_cause_13_qs;
       end
 
-      addr_hit[200]: begin
+      addr_hit[194]: begin
         reg_rdata_next[0] = alert_cause_14_qs;
       end
 
-      addr_hit[201]: begin
+      addr_hit[195]: begin
         reg_rdata_next[0] = alert_cause_15_qs;
       end
 
-      addr_hit[202]: begin
+      addr_hit[196]: begin
         reg_rdata_next[0] = alert_cause_16_qs;
       end
 
-      addr_hit[203]: begin
+      addr_hit[197]: begin
         reg_rdata_next[0] = alert_cause_17_qs;
       end
 
-      addr_hit[204]: begin
+      addr_hit[198]: begin
         reg_rdata_next[0] = alert_cause_18_qs;
       end
 
-      addr_hit[205]: begin
+      addr_hit[199]: begin
         reg_rdata_next[0] = alert_cause_19_qs;
       end
 
-      addr_hit[206]: begin
+      addr_hit[200]: begin
         reg_rdata_next[0] = alert_cause_20_qs;
       end
 
-      addr_hit[207]: begin
+      addr_hit[201]: begin
         reg_rdata_next[0] = alert_cause_21_qs;
       end
 
-      addr_hit[208]: begin
+      addr_hit[202]: begin
         reg_rdata_next[0] = alert_cause_22_qs;
       end
 
-      addr_hit[209]: begin
+      addr_hit[203]: begin
         reg_rdata_next[0] = alert_cause_23_qs;
       end
 
-      addr_hit[210]: begin
+      addr_hit[204]: begin
         reg_rdata_next[0] = alert_cause_24_qs;
       end
 
-      addr_hit[211]: begin
+      addr_hit[205]: begin
         reg_rdata_next[0] = alert_cause_25_qs;
       end
 
-      addr_hit[212]: begin
+      addr_hit[206]: begin
         reg_rdata_next[0] = alert_cause_26_qs;
       end
 
-      addr_hit[213]: begin
+      addr_hit[207]: begin
         reg_rdata_next[0] = alert_cause_27_qs;
       end
 
-      addr_hit[214]: begin
+      addr_hit[208]: begin
         reg_rdata_next[0] = alert_cause_28_qs;
       end
 
-      addr_hit[215]: begin
+      addr_hit[209]: begin
         reg_rdata_next[0] = alert_cause_29_qs;
       end
 
-      addr_hit[216]: begin
+      addr_hit[210]: begin
         reg_rdata_next[0] = alert_cause_30_qs;
       end
 
-      addr_hit[217]: begin
+      addr_hit[211]: begin
         reg_rdata_next[0] = alert_cause_31_qs;
       end
 
-      addr_hit[218]: begin
+      addr_hit[212]: begin
         reg_rdata_next[0] = alert_cause_32_qs;
       end
 
-      addr_hit[219]: begin
+      addr_hit[213]: begin
         reg_rdata_next[0] = alert_cause_33_qs;
       end
 
-      addr_hit[220]: begin
+      addr_hit[214]: begin
         reg_rdata_next[0] = alert_cause_34_qs;
       end
 
-      addr_hit[221]: begin
+      addr_hit[215]: begin
         reg_rdata_next[0] = alert_cause_35_qs;
       end
 
-      addr_hit[222]: begin
+      addr_hit[216]: begin
         reg_rdata_next[0] = alert_cause_36_qs;
       end
 
-      addr_hit[223]: begin
+      addr_hit[217]: begin
         reg_rdata_next[0] = alert_cause_37_qs;
       end
 
-      addr_hit[224]: begin
+      addr_hit[218]: begin
         reg_rdata_next[0] = alert_cause_38_qs;
       end
 
-      addr_hit[225]: begin
+      addr_hit[219]: begin
         reg_rdata_next[0] = alert_cause_39_qs;
       end
 
-      addr_hit[226]: begin
+      addr_hit[220]: begin
         reg_rdata_next[0] = alert_cause_40_qs;
       end
 
-      addr_hit[227]: begin
+      addr_hit[221]: begin
         reg_rdata_next[0] = alert_cause_41_qs;
       end
 
-      addr_hit[228]: begin
+      addr_hit[222]: begin
         reg_rdata_next[0] = alert_cause_42_qs;
       end
 
-      addr_hit[229]: begin
+      addr_hit[223]: begin
         reg_rdata_next[0] = alert_cause_43_qs;
       end
 
-      addr_hit[230]: begin
+      addr_hit[224]: begin
         reg_rdata_next[0] = alert_cause_44_qs;
       end
 
-      addr_hit[231]: begin
+      addr_hit[225]: begin
         reg_rdata_next[0] = alert_cause_45_qs;
       end
 
-      addr_hit[232]: begin
+      addr_hit[226]: begin
         reg_rdata_next[0] = alert_cause_46_qs;
       end
 
-      addr_hit[233]: begin
+      addr_hit[227]: begin
         reg_rdata_next[0] = alert_cause_47_qs;
       end
 
-      addr_hit[234]: begin
+      addr_hit[228]: begin
         reg_rdata_next[0] = alert_cause_48_qs;
       end
 
-      addr_hit[235]: begin
+      addr_hit[229]: begin
         reg_rdata_next[0] = alert_cause_49_qs;
       end
 
-      addr_hit[236]: begin
+      addr_hit[230]: begin
         reg_rdata_next[0] = alert_cause_50_qs;
       end
 
-      addr_hit[237]: begin
+      addr_hit[231]: begin
         reg_rdata_next[0] = alert_cause_51_qs;
       end
 
-      addr_hit[238]: begin
+      addr_hit[232]: begin
         reg_rdata_next[0] = alert_cause_52_qs;
       end
 
-      addr_hit[239]: begin
+      addr_hit[233]: begin
         reg_rdata_next[0] = alert_cause_53_qs;
       end
 
-      addr_hit[240]: begin
+      addr_hit[234]: begin
         reg_rdata_next[0] = alert_cause_54_qs;
       end
 
-      addr_hit[241]: begin
+      addr_hit[235]: begin
         reg_rdata_next[0] = alert_cause_55_qs;
       end
 
-      addr_hit[242]: begin
+      addr_hit[236]: begin
         reg_rdata_next[0] = alert_cause_56_qs;
       end
 
-      addr_hit[243]: begin
+      addr_hit[237]: begin
         reg_rdata_next[0] = alert_cause_57_qs;
       end
 
-      addr_hit[244]: begin
-        reg_rdata_next[0] = alert_cause_58_qs;
-      end
-
-      addr_hit[245]: begin
-        reg_rdata_next[0] = alert_cause_59_qs;
-      end
-
-      addr_hit[246]: begin
+      addr_hit[238]: begin
         reg_rdata_next[0] = loc_alert_regwen_0_qs;
       end
 
-      addr_hit[247]: begin
+      addr_hit[239]: begin
         reg_rdata_next[0] = loc_alert_regwen_1_qs;
       end
 
-      addr_hit[248]: begin
+      addr_hit[240]: begin
         reg_rdata_next[0] = loc_alert_regwen_2_qs;
       end
 
-      addr_hit[249]: begin
+      addr_hit[241]: begin
         reg_rdata_next[0] = loc_alert_regwen_3_qs;
       end
 
-      addr_hit[250]: begin
+      addr_hit[242]: begin
         reg_rdata_next[0] = loc_alert_regwen_4_qs;
       end
 
-      addr_hit[251]: begin
+      addr_hit[243]: begin
         reg_rdata_next[0] = loc_alert_regwen_5_qs;
       end
 
-      addr_hit[252]: begin
+      addr_hit[244]: begin
         reg_rdata_next[0] = loc_alert_regwen_6_qs;
       end
 
-      addr_hit[253]: begin
+      addr_hit[245]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
       end
 
-      addr_hit[254]: begin
+      addr_hit[246]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
       end
 
-      addr_hit[255]: begin
+      addr_hit[247]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
       end
 
-      addr_hit[256]: begin
+      addr_hit[248]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
       end
 
-      addr_hit[257]: begin
+      addr_hit[249]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
       end
 
-      addr_hit[258]: begin
+      addr_hit[250]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
       end
 
-      addr_hit[259]: begin
+      addr_hit[251]: begin
         reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
       end
 
-      addr_hit[260]: begin
+      addr_hit[252]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
       end
 
-      addr_hit[261]: begin
+      addr_hit[253]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
       end
 
-      addr_hit[262]: begin
+      addr_hit[254]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
       end
 
-      addr_hit[263]: begin
+      addr_hit[255]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
       end
 
-      addr_hit[264]: begin
+      addr_hit[256]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
       end
 
-      addr_hit[265]: begin
+      addr_hit[257]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
       end
 
-      addr_hit[266]: begin
+      addr_hit[258]: begin
         reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
       end
 
-      addr_hit[267]: begin
+      addr_hit[259]: begin
         reg_rdata_next[0] = loc_alert_cause_0_qs;
       end
 
-      addr_hit[268]: begin
+      addr_hit[260]: begin
         reg_rdata_next[0] = loc_alert_cause_1_qs;
       end
 
-      addr_hit[269]: begin
+      addr_hit[261]: begin
         reg_rdata_next[0] = loc_alert_cause_2_qs;
       end
 
-      addr_hit[270]: begin
+      addr_hit[262]: begin
         reg_rdata_next[0] = loc_alert_cause_3_qs;
       end
 
-      addr_hit[271]: begin
+      addr_hit[263]: begin
         reg_rdata_next[0] = loc_alert_cause_4_qs;
       end
 
-      addr_hit[272]: begin
+      addr_hit[264]: begin
         reg_rdata_next[0] = loc_alert_cause_5_qs;
       end
 
-      addr_hit[273]: begin
+      addr_hit[265]: begin
         reg_rdata_next[0] = loc_alert_cause_6_qs;
       end
 
-      addr_hit[274]: begin
+      addr_hit[266]: begin
         reg_rdata_next[0] = classa_regwen_qs;
       end
 
-      addr_hit[275]: begin
+      addr_hit[267]: begin
         reg_rdata_next[0] = classa_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs;
@@ -15426,59 +15082,59 @@
         reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[276]: begin
+      addr_hit[268]: begin
         reg_rdata_next[0] = classa_clr_regwen_qs;
       end
 
-      addr_hit[277]: begin
+      addr_hit[269]: begin
         reg_rdata_next[0] = classa_clr_shadowed_qs;
       end
 
-      addr_hit[278]: begin
+      addr_hit[270]: begin
         reg_rdata_next[15:0] = classa_accum_cnt_qs;
       end
 
-      addr_hit[279]: begin
+      addr_hit[271]: begin
         reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[280]: begin
+      addr_hit[272]: begin
         reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[281]: begin
+      addr_hit[273]: begin
         reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[282]: begin
+      addr_hit[274]: begin
         reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[283]: begin
+      addr_hit[275]: begin
         reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[284]: begin
+      addr_hit[276]: begin
         reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[285]: begin
+      addr_hit[277]: begin
         reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[286]: begin
+      addr_hit[278]: begin
         reg_rdata_next[31:0] = classa_esc_cnt_qs;
       end
 
-      addr_hit[287]: begin
+      addr_hit[279]: begin
         reg_rdata_next[2:0] = classa_state_qs;
       end
 
-      addr_hit[288]: begin
+      addr_hit[280]: begin
         reg_rdata_next[0] = classb_regwen_qs;
       end
 
-      addr_hit[289]: begin
+      addr_hit[281]: begin
         reg_rdata_next[0] = classb_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs;
@@ -15491,59 +15147,59 @@
         reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[290]: begin
+      addr_hit[282]: begin
         reg_rdata_next[0] = classb_clr_regwen_qs;
       end
 
-      addr_hit[291]: begin
+      addr_hit[283]: begin
         reg_rdata_next[0] = classb_clr_shadowed_qs;
       end
 
-      addr_hit[292]: begin
+      addr_hit[284]: begin
         reg_rdata_next[15:0] = classb_accum_cnt_qs;
       end
 
-      addr_hit[293]: begin
+      addr_hit[285]: begin
         reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[294]: begin
+      addr_hit[286]: begin
         reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[295]: begin
+      addr_hit[287]: begin
         reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[296]: begin
+      addr_hit[288]: begin
         reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[297]: begin
+      addr_hit[289]: begin
         reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[298]: begin
+      addr_hit[290]: begin
         reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[299]: begin
+      addr_hit[291]: begin
         reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[300]: begin
+      addr_hit[292]: begin
         reg_rdata_next[31:0] = classb_esc_cnt_qs;
       end
 
-      addr_hit[301]: begin
+      addr_hit[293]: begin
         reg_rdata_next[2:0] = classb_state_qs;
       end
 
-      addr_hit[302]: begin
+      addr_hit[294]: begin
         reg_rdata_next[0] = classc_regwen_qs;
       end
 
-      addr_hit[303]: begin
+      addr_hit[295]: begin
         reg_rdata_next[0] = classc_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs;
@@ -15556,59 +15212,59 @@
         reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[304]: begin
+      addr_hit[296]: begin
         reg_rdata_next[0] = classc_clr_regwen_qs;
       end
 
-      addr_hit[305]: begin
+      addr_hit[297]: begin
         reg_rdata_next[0] = classc_clr_shadowed_qs;
       end
 
-      addr_hit[306]: begin
+      addr_hit[298]: begin
         reg_rdata_next[15:0] = classc_accum_cnt_qs;
       end
 
-      addr_hit[307]: begin
+      addr_hit[299]: begin
         reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[308]: begin
+      addr_hit[300]: begin
         reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[309]: begin
+      addr_hit[301]: begin
         reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[310]: begin
+      addr_hit[302]: begin
         reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[311]: begin
+      addr_hit[303]: begin
         reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[312]: begin
+      addr_hit[304]: begin
         reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[313]: begin
+      addr_hit[305]: begin
         reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[314]: begin
+      addr_hit[306]: begin
         reg_rdata_next[31:0] = classc_esc_cnt_qs;
       end
 
-      addr_hit[315]: begin
+      addr_hit[307]: begin
         reg_rdata_next[2:0] = classc_state_qs;
       end
 
-      addr_hit[316]: begin
+      addr_hit[308]: begin
         reg_rdata_next[0] = classd_regwen_qs;
       end
 
-      addr_hit[317]: begin
+      addr_hit[309]: begin
         reg_rdata_next[0] = classd_ctrl_shadowed_en_qs;
         reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs;
         reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs;
@@ -15621,51 +15277,51 @@
         reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs;
       end
 
-      addr_hit[318]: begin
+      addr_hit[310]: begin
         reg_rdata_next[0] = classd_clr_regwen_qs;
       end
 
-      addr_hit[319]: begin
+      addr_hit[311]: begin
         reg_rdata_next[0] = classd_clr_shadowed_qs;
       end
 
-      addr_hit[320]: begin
+      addr_hit[312]: begin
         reg_rdata_next[15:0] = classd_accum_cnt_qs;
       end
 
-      addr_hit[321]: begin
+      addr_hit[313]: begin
         reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs;
       end
 
-      addr_hit[322]: begin
+      addr_hit[314]: begin
         reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs;
       end
 
-      addr_hit[323]: begin
+      addr_hit[315]: begin
         reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs;
       end
 
-      addr_hit[324]: begin
+      addr_hit[316]: begin
         reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs;
       end
 
-      addr_hit[325]: begin
+      addr_hit[317]: begin
         reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs;
       end
 
-      addr_hit[326]: begin
+      addr_hit[318]: begin
         reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs;
       end
 
-      addr_hit[327]: begin
+      addr_hit[319]: begin
         reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs;
       end
 
-      addr_hit[328]: begin
+      addr_hit[320]: begin
         reg_rdata_next[31:0] = classd_esc_cnt_qs;
       end
 
-      addr_hit[329]: begin
+      addr_hit[321]: begin
         reg_rdata_next[2:0] = classd_state_qs;
       end
 

diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index 91b3573..b2bf727 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson

@@ -34,21 +34,15 @@
     { name: "rd_full",    desc: "Read FIFO full" },
     { name: "rd_lvl",     desc: "Read FIFO filled to level" },
     { name: "op_done",    desc: "Operation complete" },
-    { name: "err",        desc: "Error encountered"},
+    { name: "corr_err",   desc: "Correctable error encountered"},
   ],
 
   alert_list: [
     { name: "recov_err",
-      desc: "flash alerts directly from prim_flash",
+      desc: "flash recoverable errors",
     },
-    { name: "recov_mp_err",
-      desc: "recoverable flash alert for permission error"
-    },
-    { name: "recov_ecc_err",
-      desc: "recoverable flash alert for ecc error"
-    },
-    { name: "fatal_intg_err",
-      desc: "Fatal integrity error"
+    { name: "fatal_err",
+      desc: "flash fatal errors"
     },
   ],
 
@@ -1390,159 +1384,172 @@
         ]
       },
 
-      { name: "ERR_CODE_INTR_EN",
-        desc: '''
-          Interrupt enable mask for error code.
-          Only enabled bits will generate interrupts.
-          Bits that are not enabled will still be reflected in the !!ERR_CODE register, but will not trigger
-          an interrupt
-        '''
-        swaccess: "rw",
-        hwaccess: "hro",
-        fields: [
-          { bits: "0",
-            name: "flash_err_en",
-            desc: "interrupt mask for flash error"
-          },
-          { bits: "1",
-            name: "flash_alert_en",
-            desc: "interrupt mask for flash alert"
-          },
-          { bits: "2",
-            name: "oob_err",
-            desc: "interrupt mask for software address out of bounds error"
-          },
-          { bits: "3",
-            name: "mp_err",
-            desc: "interrupt mask for memory properties error"
-          },
-          { bits: "4",
-            name: "ecc_single_err",
-            desc: "interrupt mask for single bit ecc error"
-          },
-          { bits: "5",
-            name: "ecc_multi_err",
-            desc: "interrupt mask for multiple bits ecc error"
-          },
-        ]
-      },
-
       { name: "ERR_CODE",
         desc: '''
           Flash error code register.
           This register tabulates detailed error status of the flash.
           This is separate from !!OP_STATUS, which is used to indicate the current state of the software initiated
           flash operation.
+
+          Note, all errors in this register are considered recoverable errors, ie, errors that could have been
+          generated by software.
         '''
         swaccess: "rw1c",
-        hwaccess: "hrw",
+        hwaccess: "hwo",
         fields: [
           { bits: "0",
-            name: "flash_err",
-            desc: '''
-              The flash memory itself has an error, please check the vendor specs for details of the error.
-            '''
-          },
-          { bits: "1",
-            name: "flash_alert",
-            desc: '''
-              The flash memory itself has triggered an alert, please check the vendor specs for details of the error.
-            '''
-          },
-          { bits: "2",
             name: "oob_err",
             desc: '''
               The supplied address !!ADDR is invalid and out of bounds.
+              This is a synchronous error.
             '''
           },
-          { bits: "3",
+          { bits: "1",
             name: "mp_err",
             desc: '''
               Flash access has encountered an access permission error.
               Please see !!ERR_ADDR for exact address.
+              This is a synchronous error.
+            '''
+          },
+          { bits: "2",
+            name: "rd_err",
+            desc: '''
+              Flash read has an uncorrectable data error.
+              Please see !!ERR_ADDR for exact address.
+              This is a synchronous error.
+            '''
+          },
+          { bits: "3",
+            name: "prog_win_err",
+            desc: '''
+              Flash program has a window resolution error.  Ie, the start of program
+              and end of program are in different windows.  Please check !!ADDR.
+              This is a synchronous error.
             '''
           },
           { bits: "4",
-            name: "ecc_single_err",
+            name: "prog_type_err",
             desc: '''
-              Flash access has encountered a single bit ECC error.
-              Please see !!ECC_SINGLE_ERR_ADDR for exact address.
+              Flash program selected unavailable type, see !!PROG_TYPE_EN.
+              This is a synchronous error.
             '''
           },
           { bits: "5",
-            name: "ecc_multi_err",
+            name: "flash_phy_err",
             desc: '''
-              Flash access has encountered a multi bit ECC error.
-              Please see !!ECC_MULTI_ERR_ADDR for exact address.
+              The flash access encountered a native flash error.
+              Please check the vendor specs for details of the error.
+              This is a synchronous error.
+            '''
+          },
+        ]
+      },
+
+      { name: "FAULT_STATUS",
+        desc: '''
+          Flash fault status register.
+          This register tabulates detailed fault status of the flash.
+
+          These are errors that are impossible to have been caused by software or unrecoverable
+          in nature.
+        '''
+        swaccess: "ro",
+        hwaccess: "hrw",
+        fields: [
+          { bits: "0",
+            name: "oob_err",
+            desc: '''
+              The flash hardware interface supplied an out of bound value.
+            '''
+          },
+          { bits: "1",
+            name: "mp_err",
+            desc: '''
+              The flash hardware interface encountered a memory permission error.
+            '''
+          },
+          { bits: "2",
+            name: "rd_err",
+            desc: '''
+              The flash hardware interface encountered a read data error.
+            '''
+          },
+          { bits: "3",
+            name: "prog_win_err",
+            desc: '''
+              The flash hardware interface encountered a program resolution error.
+            '''
+          },
+          { bits: "4",
+            name: "prog_type_err",
+            desc: '''
+              The flash hardware interface encountered a program type error.
+            '''
+          },
+          { bits: "5",
+            name: "flash_phy_err",
+            desc: '''
+              The flash hardware interface encountered a native flash error.
+            '''
+          },
+          { bits: "6",
+            name: "reg_intg_err",
+            desc: '''
+              The flash controller encountered a register integrity error.
+            '''
+          },
+          { bits: "7",
+            name: "phy_intg_err",
+            desc: '''
+              The flash memory encountered a register integrity error.
             '''
           },
         ]
       },
 
       { name: "ERR_ADDR",
-        desc: "Access permission error address",
+        desc: "Synchronous error address",
         swaccess: "ro",
         hwaccess: "hwo",
         fields: [
-          { bits: "8:0",
-            resval: 0,
-          },
-        ]
-      },
-
-      { name: "ECC_SINGLE_ERR_CNT",
-        desc: "Total number of single bit ECC error count",
-        swaccess: "rw1c",
-        hwaccess: "hrw",
-        fields: [
-          { bits: "7:0",
-            desc: "This count will not wrap when saturated",
+          { bits: "31:0",
             resval: 0,
           },
         ]
       },
 
       { multireg: {
-          cname: "ECC_SINGLE_ERR"
+          cname: "ECC_SINGLE_ERR",
+          name: "ECC_SINGLE_ERR_CNT",
+          desc: "Total number of single bit ECC error count",
+          count: "RegNumBanks",
+          swaccess: "rw",
+          hwaccess: "hrw",
+          fields: [
+            { bits: "7:0",
+              desc: "This count will not wrap when saturated",
+              resval: 0,
+            },
+          ]
+        }
+      },
+
+      { multireg: {
+          cname: "ECC_SINGLE_ERR",
           name: "ECC_SINGLE_ERR_ADDR",
-          desc: "Latest single bit error address (correctable)",
+          desc: "Latest address of ECC single err",
           count: "RegNumBanks",
           swaccess: "ro",
           hwaccess: "hwo",
           fields: [
             { bits: "19:0",
+              desc: "Latest single error address for this bank",
               resval: 0,
             },
           ]
         }
-      },
-
-      { name: "ECC_MULTI_ERR_CNT",
-        desc: "Total number of multi bit ECC error count",
-        swaccess: "rw1c",
-        hwaccess: "hrw",
-        fields: [
-          { bits: "7:0",
-            desc: "This count will not wrap when saturated",
-            resval: 0,
-          },
-        ]
-      },
-
-      { multireg: {
-          cname: "ECC_MULTI_ERR"
-          name: "ECC_MULTI_ERR_ADDR",
-          desc: "Latest multi bit error address (uncorrectable)",
-          count: "RegNumBanks",
-          swaccess: "ro",
-          hwaccess: "hwo",
-          fields: [
-            { bits: "19:0",
-              resval: 0,
-            },
-          ]
-        }
-      },
+      }
 
       { name: "PHY_ERR_CFG_REGWEN",
         swaccess: "rw0c",

diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index c90b487..bbcd48a 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv

@@ -64,7 +64,7 @@
   output logic cio_tdo_o,
 
   // Interrupts
-  output logic intr_err_o,        // ERR_CODE is non-zero
+  output logic intr_corr_err_o,   // Correctable errors encountered
   output logic intr_prog_empty_o, // Program fifo is empty
   output logic intr_prog_lvl_o,   // Program fifo is empty
   output logic intr_rd_full_o,    // Read fifo is full
@@ -150,18 +150,16 @@
   flash_erase_e erase_flash_type;
   logic erase_op_valid;
 
-  // combined indication that an operation has started
-  logic op_valid;
-
   // Done / Error signaling from ctrl modules
   logic prog_done, rd_done, erase_done;
-  logic prog_err, rd_err, erase_err;
+  flash_ctrl_err_t prog_err, rd_err, erase_err;
+  logic [BusAddrW-1:0] prog_err_addr, rd_err_addr, erase_err_addr;
 
   // Flash Memory Properties Connections
   logic [BusAddrW-1:0] flash_addr;
   logic flash_req;
   logic flash_rd_done, flash_prog_done, flash_erase_done;
-  logic flash_mp_error;
+  logic flash_mp_err;
   logic [BusWidth-1:0] flash_prog_data;
   logic flash_prog_last;
   flash_prog_e flash_prog_type;
@@ -171,7 +169,6 @@
   logic rd_op;
   logic prog_op;
   logic erase_op;
-  logic [AllPagesW-1:0] err_addr;
   flash_lcmgr_phase_e phase;
 
   // Flash control arbitration connections to hardware interface
@@ -183,7 +180,7 @@
   logic hw_req;
   logic [top_pkg::TL_AW-1:0] hw_addr;
   logic hw_done;
-  logic hw_err;
+  flash_ctrl_err_t hw_err;
   logic hw_rvalid;
   logic hw_rready;
   logic hw_wvalid;
@@ -197,7 +194,7 @@
 
   // Flash control arbitration connections to software interface
   logic sw_ctrl_done;
-  logic sw_ctrl_err;
+  flash_ctrl_err_t sw_ctrl_err;
 
   // Flash control muxed connections
   flash_ctrl_reg2hw_control_reg_t muxed_ctrl;
@@ -205,6 +202,7 @@
   logic op_start;
   logic [11:0] op_num_words;
   logic [BusAddrW-1:0] op_addr;
+  logic [BusAddrW-1:0] ctrl_err_addr;
   // SW or HW supplied address is out of bounds
   logic op_addr_oob;
   flash_op_e op_type;
@@ -311,6 +309,9 @@
     .clk_i,
     .rst_ni,
 
+    // error output shared by both interfaces
+    .ctrl_err_addr_o(ctrl_err_addr),
+
     // software interface to rd_ctrl / erase_ctrl
     .sw_ctrl_i(reg2hw.control),
     .sw_addr_i(reg2hw.addr.q),
@@ -352,10 +353,13 @@
     .muxed_addr_o(muxed_addr),
     .prog_ack_i(prog_done),
     .prog_err_i(prog_err),
+    .prog_err_addr_i(prog_err_addr),
     .rd_ack_i(rd_done),
     .rd_err_i(rd_err),
+    .rd_err_addr_i(rd_err_addr),
     .erase_ack_i(erase_done),
     .erase_err_i(erase_err),
+    .erase_err_addr_i(erase_err_addr),
 
     // muxed interface to rd_fifo
     .rd_fifo_rvalid_i(rd_fifo_rvalid),
@@ -394,7 +398,6 @@
   assign prog_op       = op_type == FlashOpProgram;
   assign erase_op      = op_type == FlashOpErase;
   assign sw_sel        = if_sel == SwSel;
-  assign op_valid      = prog_op_valid | rd_op_valid | erase_op_valid;
 
   // software privilege to creator seed
   assign creator_seed_priv = lc_creator_seed_sw_rw_en == lc_ctrl_pkg::On;
@@ -530,6 +533,7 @@
     .op_addr_oob_i  (op_addr_oob),
     .op_type_i      (op_prog_type),
     .type_avail_i   (prog_type_en),
+    .op_err_addr_o  (prog_err_addr),
 
     // FIFO Interface
     .data_i         (prog_fifo_rdata),
@@ -544,7 +548,9 @@
     .flash_last_o   (flash_prog_last),
     .flash_type_o   (flash_prog_type),
     .flash_done_i   (flash_prog_done),
-    .flash_error_i  (flash_mp_error)
+    // TODO, pending feedback
+    .flash_phy_err_i(flash_phy_rsp.flash_err),
+    .flash_mp_err_i (flash_mp_err)
   );
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -608,6 +614,7 @@
     .op_num_words_i (op_num_words),
     .op_done_o      (rd_done),
     .op_err_o       (rd_err),
+    .op_err_addr_o  (rd_err_addr),
     .op_addr_i      (op_addr),
     .op_addr_oob_i  (op_addr_oob),
 
@@ -622,7 +629,9 @@
     .flash_ovfl_o   (rd_flash_ovfl),
     .flash_data_i   (flash_rd_data),
     .flash_done_i   (flash_rd_done),
-    .flash_error_i  (flash_mp_error | flash_rd_err)
+    .flash_mp_err_i (flash_mp_err),
+    .flash_rd_err_i (flash_rd_err),
+    .flash_phy_err_i(flash_phy_rsp.flash_err)
   );
 
   // Erase handler does not consume fifo
@@ -635,13 +644,15 @@
     .op_err_o       (erase_err),
     .op_addr_i      (op_addr),
     .op_addr_oob_i  (op_addr_oob),
+    .op_err_addr_o  (erase_err_addr),
 
     // Flash Macro Interface
     .flash_req_o    (erase_flash_req),
     .flash_addr_o   (erase_flash_addr),
     .flash_op_o     (erase_flash_type),
     .flash_done_i   (flash_erase_done),
-    .flash_error_i  (flash_mp_error)
+    .flash_mp_err_i (flash_mp_err),
+    .flash_phy_err_i(flash_phy_rsp.flash_err)
   );
 
   // Final muxing to flash macro module
@@ -762,8 +773,7 @@
     .rd_done_o(flash_rd_done),
     .prog_done_o(flash_prog_done),
     .erase_done_o(flash_erase_done),
-    .error_o(flash_mp_error),
-    .err_addr_o(err_addr),
+    .error_o(flash_mp_err),
 
     // flash phy interface
     .req_o(flash_phy_req.req),
@@ -787,7 +797,7 @@
   assign hw2reg.op_status.done.d     = 1'b1;
   assign hw2reg.op_status.done.de    = sw_ctrl_done;
   assign hw2reg.op_status.err.d      = 1'b1;
-  assign hw2reg.op_status.err.de     = sw_ctrl_err;
+  assign hw2reg.op_status.err.de     = |sw_ctrl_err;
   assign hw2reg.status.rd_full.d     = rd_fifo_full;
   assign hw2reg.status.rd_full.de    = sw_sel;
   assign hw2reg.status.rd_empty.d    = ~rd_fifo_rvalid;
@@ -862,31 +872,24 @@
   logic [NumAlerts-1:0] alert_srcs;
   logic [NumAlerts-1:0] alert_tests;
 
+  // TODO Add shadow update
+  // An excessive number of recoverable errors may also indicate an attack
   logic recov_err;
-  assign recov_err = flash_phy_rsp.flash_alert_p | ~flash_phy_rsp.flash_alert_n;
+  assign recov_err = sw_ctrl_done & |sw_ctrl_err;
 
-  logic recov_mp_err;
-  assign recov_mp_err = flash_mp_error;
+  logic fatal_err;
+  assign fatal_err = |reg2hw.fault_status;
 
-  logic recov_ecc_err;
-  assign recov_ecc_err = |flash_phy_rsp.ecc_single_err | |flash_phy_rsp.ecc_multi_err;
 
-  logic fatal_intg_err;
-  assign fatal_intg_err = flash_phy_rsp.intg_err | intg_err;
-
-  assign alert_srcs = { fatal_intg_err,
-                        recov_ecc_err,
-                        recov_mp_err,
+  assign alert_srcs = { fatal_err,
                         recov_err
                       };
 
-  assign alert_tests = { reg2hw.alert_test.fatal_intg_err.q & reg2hw.alert_test.fatal_intg_err.qe,
-                         reg2hw.alert_test.recov_ecc_err.q & reg2hw.alert_test.recov_ecc_err.qe,
-                         reg2hw.alert_test.recov_mp_err.q  & reg2hw.alert_test.recov_mp_err.qe,
-                         reg2hw.alert_test.recov_err.q     & reg2hw.alert_test.recov_err.qe
+  assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+                         reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
                        };
 
-  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0, 1'b0, 1'b0};
+  localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0};
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
     prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
@@ -907,7 +910,7 @@
   // Flash Disable
   //////////////////////////////////////
   assign flash_disable = reg2hw.flash_disable.q ? lc_ctrl_pkg::On :
-                         fatal_intg_err         ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
+                         fatal_err              ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
 
   lc_ctrl_pkg::lc_tx_t lc_escalate_en;
   prim_lc_sync #(
@@ -925,133 +928,184 @@
   // Errors and Interrupts
   //////////////////////////////////////
 
-  assign hw2reg.err_code.oob_err.d = 1'b1;
-  assign hw2reg.err_code.mp_err.d = 1'b1;
-  assign hw2reg.err_code.ecc_single_err.d = 1'b1;
-  assign hw2reg.err_code.ecc_multi_err.d = 1'b1;
-  assign hw2reg.err_code.flash_err.d = 1'b1;
-  assign hw2reg.err_code.flash_alert.d = 1'b1;
-  assign hw2reg.err_code.oob_err.de = op_valid & op_addr_oob;
-  assign hw2reg.err_code.mp_err.de = flash_mp_error;
-  assign hw2reg.err_code.ecc_single_err.de = |flash_phy_rsp.ecc_single_err;
-  assign hw2reg.err_code.ecc_multi_err.de = |flash_phy_rsp.ecc_multi_err;
-  assign hw2reg.err_code.flash_err.de = flash_phy_rsp.flash_err;
-  assign hw2reg.err_code.flash_alert.de = flash_phy_rsp.flash_alert_p |
-                                          ~flash_phy_rsp.flash_alert_n;
-  assign hw2reg.err_addr.d = err_addr;
-  assign hw2reg.err_addr.de = flash_mp_error;
+  // all software interface errors are treated as synchronous errors
+  assign hw2reg.err_code.oob_err.d        = 1'b1;
+  assign hw2reg.err_code.mp_err.d         = 1'b1;
+  assign hw2reg.err_code.rd_err.d         = 1'b1;
+  assign hw2reg.err_code.prog_win_err.d   = 1'b1;
+  assign hw2reg.err_code.prog_type_err.d  = 1'b1;
+  assign hw2reg.err_code.flash_phy_err.d  = 1'b1;
+  assign hw2reg.err_code.oob_err.de       = sw_ctrl_err.oob_err;
+  assign hw2reg.err_code.mp_err.de        = sw_ctrl_err.mp_err;
+  assign hw2reg.err_code.rd_err.de        = sw_ctrl_err.rd_err;
+  assign hw2reg.err_code.prog_win_err.de  = sw_ctrl_err.prog_win_err;
+  assign hw2reg.err_code.prog_type_err.de = sw_ctrl_err.prog_type_err;
+  assign hw2reg.err_code.flash_phy_err.de = sw_ctrl_err.phy_err;
+  assign hw2reg.err_addr.d                = {reg2hw.addr.q[31:BusAddrW],ctrl_err_addr};
+  assign hw2reg.err_addr.de               = sw_ctrl_err.mp_err |
+                                            sw_ctrl_err.rd_err |
+                                            sw_ctrl_err.phy_err;
 
-  for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_single_err_cons
-    assign hw2reg.ecc_single_err_addr[bank].d  = {flash_phy_rsp.ecc_addr[bank],
-      {BusByteWidth{1'b0}}};
-    assign hw2reg.ecc_single_err_addr[bank].de = flash_phy_rsp.ecc_single_err[bank];
+  // all hardware interface errors are considered faults
+  assign hw2reg.fault_status.oob_err.d        = 1'b1;
+  assign hw2reg.fault_status.mp_err.d         = 1'b1;
+  assign hw2reg.fault_status.rd_err.d         = 1'b1;
+  assign hw2reg.fault_status.prog_win_err.d   = 1'b1;
+  assign hw2reg.fault_status.prog_type_err.d  = 1'b1;
+  assign hw2reg.fault_status.flash_phy_err.d  = 1'b1;
+  assign hw2reg.fault_status.reg_intg_err.d   = 1'b1;
+  assign hw2reg.fault_status.phy_intg_err.d   = 1'b1;
+  assign hw2reg.fault_status.oob_err.de       = hw_err.oob_err;
+  assign hw2reg.fault_status.mp_err.de        = hw_err.mp_err;
+  assign hw2reg.fault_status.rd_err.de        = hw_err.rd_err;
+  assign hw2reg.fault_status.prog_win_err.de  = hw_err.prog_win_err;
+  assign hw2reg.fault_status.prog_type_err.de = hw_err.prog_type_err;
+  assign hw2reg.fault_status.flash_phy_err.de = hw_err.phy_err;
+  assign hw2reg.fault_status.reg_intg_err.de  = intg_err;
+  assign hw2reg.fault_status.phy_intg_err.de  = flash_phy_rsp.intg_err;
+
+  // Correctable ECC count / address
+  for (genvar i = 0; i < NumBanks; i++) begin : gen_ecc_single_err_reg
+    assign hw2reg.ecc_single_err_cnt[i].de = flash_phy_rsp.ecc_single_err[i];
+    assign hw2reg.ecc_single_err_cnt[i].d = &reg2hw.ecc_single_err_cnt[i].q ?
+                                            reg2hw.ecc_single_err_cnt[i].q :
+                                            reg2hw.ecc_single_err_cnt[i].q + 1'b1;
+
+    assign hw2reg.ecc_single_err_addr[i].de = flash_phy_rsp.ecc_single_err[i];
+    assign hw2reg.ecc_single_err_addr[i].d = {flash_phy_rsp.ecc_addr[i], {BusByteWidth{1'b0}}};
   end
 
-  for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_multi_err_cons
-    assign hw2reg.ecc_multi_err_addr[bank].d  = {flash_phy_rsp.ecc_addr[bank],
-      {BusByteWidth{1'b0}}};
-    assign hw2reg.ecc_multi_err_addr[bank].de = flash_phy_rsp.ecc_multi_err[bank];
-  end
-
-  logic [7:0] single_err_cnt_d, multi_err_cnt_d;
-  always_comb begin
-    single_err_cnt_d = reg2hw.ecc_single_err_cnt.q;
-    multi_err_cnt_d = reg2hw.ecc_multi_err_cnt.q;
-
-    if (|flash_phy_rsp.ecc_single_err && single_err_cnt_d < '1) begin
-      single_err_cnt_d = single_err_cnt_d + 1'b1;
-    end
-
-    if (|flash_phy_rsp.ecc_multi_err && multi_err_cnt_d < '1) begin
-      multi_err_cnt_d = multi_err_cnt_d + 1'b1;
-    end
-  end
-
-  // feed back in error count
-  assign hw2reg.ecc_single_err_cnt.de = 1'b1;
-  assign hw2reg.ecc_single_err_cnt.d  = single_err_cnt_d;
-  assign hw2reg.ecc_multi_err_cnt.de  = 1'b1;
-  assign hw2reg.ecc_multi_err_cnt.d   = multi_err_cnt_d;
-
-  // err code interrupt event
-  flash_ctrl_reg2hw_err_code_reg_t err_code_d, err_code_q;
-  logic err_code_intr_event;
-
-  assign err_code_d = reg2hw.err_code & reg2hw.err_code_intr_en;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      err_code_q <= '0;
-    end else begin
-      err_code_q <= err_code_d;
-    end
-  end
-
-  assign err_code_intr_event = err_code_d != err_code_q;
-
   // general interrupt events
-  logic [3:0] intr_src_d;
-  logic [3:0] intr_src_q;
+  logic [LastIntrIdx-1:0] intr_event;
 
-  assign intr_src_d = { ~prog_fifo_rvalid,
-                        reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
-                        rd_fifo_full,
-                        reg2hw.fifo_lvl.rd.q == rd_fifo_depth
-                      };
+  prim_edge_detector #(
+    .Width(1),
+    .ResetValue(1)
+  ) u_prog_empty_event (
+    .clk_i,
+    .rst_ni,
+    .d_i(~prog_fifo_rvalid),
+    .q_sync_o(),
+    .q_posedge_pulse_o(intr_event[ProgEmpty]),
+    .q_negedge_pulse_o()
+  );
 
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      intr_src_q <= 4'h8; //prog_fifo is empty by default
-    end else begin
-      if (sw_sel) begin
-        intr_src_q[3:0] <= intr_src_d[3:0];
-      end
-    end
-  end
+  prim_intr_hw #(.Width(1)) u_intr_prog_empty (
+    .clk_i,
+    .rst_ni,
+    .event_intr_i           (intr_event[ProgEmpty]),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.prog_empty.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.prog_empty.q),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.prog_empty.qe),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.prog_empty.q),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.prog_empty.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.prog_empty.d),
+    .intr_o                 (intr_prog_empty_o)
+  );
 
-  // interrupt events
-  logic [4:0] intr_assert;
-  assign intr_assert[4] = err_code_intr_event;
-  assign intr_assert[3:0] = ~intr_src_q & intr_src_d;
+  prim_edge_detector #(
+    .Width(1),
+    .ResetValue(0)
+  ) u_prog_lvl_event (
+    .clk_i,
+    .rst_ni,
+    .d_i(reg2hw.fifo_lvl.prog.q == prog_fifo_depth),
+    .q_sync_o(),
+    .q_posedge_pulse_o(intr_event[ProgLvl]),
+    .q_negedge_pulse_o()
+  );
 
-  assign intr_prog_empty_o = reg2hw.intr_enable.prog_empty.q & reg2hw.intr_state.prog_empty.q;
-  assign intr_prog_lvl_o = reg2hw.intr_enable.prog_lvl.q & reg2hw.intr_state.prog_lvl.q;
-  assign intr_rd_full_o = reg2hw.intr_enable.rd_full.q & reg2hw.intr_state.rd_full.q;
-  assign intr_rd_lvl_o = reg2hw.intr_enable.rd_lvl.q & reg2hw.intr_state.rd_lvl.q;
-  assign intr_op_done_o = reg2hw.intr_enable.op_done.q & reg2hw.intr_state.op_done.q;
-  assign intr_err_o = reg2hw.intr_enable.err.q & reg2hw.intr_state.err.q;
+  prim_intr_hw #(.Width(1)) u_intr_prog_lvl (
+    .clk_i,
+    .rst_ni,
+    .event_intr_i           (intr_event[ProgLvl]),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.prog_lvl.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.prog_lvl.q),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.prog_lvl.qe),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.prog_lvl.q),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.prog_lvl.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.prog_lvl.d),
+    .intr_o                 (intr_prog_lvl_o)
+  );
 
-  assign hw2reg.intr_state.err.d  = 1'b1;
-  assign hw2reg.intr_state.err.de = intr_assert[4] |
-                                    (reg2hw.intr_test.err.qe  &
-                                    reg2hw.intr_test.err.q);
+  prim_edge_detector #(
+    .Width(1),
+    .ResetValue(0)
+  ) u_rd_full_event (
+    .clk_i,
+    .rst_ni,
+    .d_i(rd_fifo_full),
+    .q_sync_o(),
+    .q_posedge_pulse_o(intr_event[RdFull]),
+    .q_negedge_pulse_o()
+  );
 
-  assign hw2reg.intr_state.prog_empty.d  = 1'b1;
-  assign hw2reg.intr_state.prog_empty.de = intr_assert[3]  |
-                                           (reg2hw.intr_test.prog_empty.qe  &
-                                           reg2hw.intr_test.prog_empty.q);
+  prim_intr_hw #(.Width(1)) u_intr_rd_full (
+    .clk_i,
+    .rst_ni,
+    .event_intr_i           (intr_event[RdFull]),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rd_full.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rd_full.q),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rd_full.qe),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rd_full.q),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.rd_full.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rd_full.d),
+    .intr_o                 (intr_rd_full_o)
+  );
 
-  assign hw2reg.intr_state.prog_lvl.d  = 1'b1;
-  assign hw2reg.intr_state.prog_lvl.de = intr_assert[2]  |
-                                         (reg2hw.intr_test.prog_lvl.qe  &
-                                         reg2hw.intr_test.prog_lvl.q);
+  prim_edge_detector #(
+    .Width(1),
+    .ResetValue(0)
+  ) u_rd_lvl_event (
+    .clk_i,
+    .rst_ni,
+    .d_i(reg2hw.fifo_lvl.rd.q == rd_fifo_depth),
+    .q_sync_o(),
+    .q_posedge_pulse_o(intr_event[RdLvl]),
+    .q_negedge_pulse_o()
+  );
 
-  assign hw2reg.intr_state.rd_full.d  = 1'b1;
-  assign hw2reg.intr_state.rd_full.de = intr_assert[1] |
-                                        (reg2hw.intr_test.rd_full.qe  &
-                                        reg2hw.intr_test.rd_full.q);
+  prim_intr_hw #(.Width(1)) u_intr_rd_lvl (
+    .clk_i,
+    .rst_ni,
+    .event_intr_i           (intr_event[RdLvl]),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rd_lvl.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.rd_lvl.q),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rd_lvl.qe),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.rd_lvl.q),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.rd_lvl.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.rd_lvl.d),
+    .intr_o                 (intr_rd_lvl_o)
+  );
 
-  assign hw2reg.intr_state.rd_lvl.d  = 1'b1;
-  assign hw2reg.intr_state.rd_lvl.de =  intr_assert[0] |
-                                       (reg2hw.intr_test.rd_lvl.qe  &
-                                       reg2hw.intr_test.rd_lvl.q);
+  assign intr_event[OpDone] = sw_ctrl_done;
+  assign intr_event[CorrErr] = |flash_phy_rsp.ecc_single_err;
 
-  assign hw2reg.intr_state.op_done.d  = 1'b1;
-  assign hw2reg.intr_state.op_done.de = sw_ctrl_done  |
-                                        (reg2hw.intr_test.op_done.qe  &
-                                        reg2hw.intr_test.op_done.q);
+  prim_intr_hw #(.Width(1)) u_intr_op_done (
+    .clk_i,
+    .rst_ni,
+    .event_intr_i           (intr_event[OpDone]),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.op_done.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.op_done.q),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.op_done.qe),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.op_done.q),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.op_done.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.op_done.d),
+    .intr_o                 (intr_op_done_o)
+  );
 
-
+  prim_intr_hw #(.Width(1)) u_intr_corr_err (
+    .clk_i,
+    .rst_ni,
+    .event_intr_i           (intr_event[CorrErr]),
+    .reg2hw_intr_enable_q_i (reg2hw.intr_enable.corr_err.q),
+    .reg2hw_intr_test_q_i   (reg2hw.intr_test.corr_err.q),
+    .reg2hw_intr_test_qe_i  (reg2hw.intr_test.corr_err.qe),
+    .reg2hw_intr_state_q_i  (reg2hw.intr_state.corr_err.q),
+    .hw2reg_intr_state_de_o (hw2reg.intr_state.corr_err.de),
+    .hw2reg_intr_state_d_o  (hw2reg.intr_state.corr_err.d),
+    .intr_o                 (intr_corr_err_o)
+  );
 
   // Unused bits
   logic [BusByteWidth-1:0] unused_byte_sel;
@@ -1150,12 +1204,15 @@
   `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o   )
   `ASSERT_KNOWN(IntrRdLvlKnownO_A,      intr_rd_lvl_o    )
   `ASSERT_KNOWN(IntrOpDoneKnownO_A,     intr_op_done_o   )
-  `ASSERT_KNOWN(IntrErrO_A,             intr_err_o       )
+  `ASSERT_KNOWN(IntrErrO_A,             intr_corr_err_o  )
 
-
+  // combined indication that an operation has started
+  // This is used only for assertions
+  logic unused_op_valid;
+  assign unused_op_valid = prog_op_valid | rd_op_valid | erase_op_valid;
 
   // if there is an out of bounds error, flash request should never assert
-  `ASSERT(OutofBoundsReq_A, op_valid & op_addr_oob |-> ~flash_phy_req.req)
+  `ASSERT(OutofBoundsReq_A, unused_op_valid & op_addr_oob |-> ~flash_phy_req.req)
 
   // add more assertions
 

diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
index 4ca672f..59d2a99 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv

@@ -121,10 +121,10 @@
     reg_steer = 2;       // Default set to register
 
     // TODO: Can below codes be unique case () inside ?
-    if (tl_i.a_address[AW-1:0] >= 400 && tl_i.a_address[AW-1:0] < 404) begin
+    if (tl_i.a_address[AW-1:0] >= 388 && tl_i.a_address[AW-1:0] < 392) begin
       reg_steer = 0;
     end
-    if (tl_i.a_address[AW-1:0] >= 404 && tl_i.a_address[AW-1:0] < 408) begin
+    if (tl_i.a_address[AW-1:0] >= 392 && tl_i.a_address[AW-1:0] < 396) begin
       reg_steer = 1;
     end
     if (intg_err) begin
@@ -172,8 +172,8 @@
   logic intr_state_rd_lvl_wd;
   logic intr_state_op_done_qs;
   logic intr_state_op_done_wd;
-  logic intr_state_err_qs;
-  logic intr_state_err_wd;
+  logic intr_state_corr_err_qs;
+  logic intr_state_corr_err_wd;
   logic intr_enable_we;
   logic intr_enable_prog_empty_qs;
   logic intr_enable_prog_empty_wd;
@@ -185,20 +185,18 @@
   logic intr_enable_rd_lvl_wd;
   logic intr_enable_op_done_qs;
   logic intr_enable_op_done_wd;
-  logic intr_enable_err_qs;
-  logic intr_enable_err_wd;
+  logic intr_enable_corr_err_qs;
+  logic intr_enable_corr_err_wd;
   logic intr_test_we;
   logic intr_test_prog_empty_wd;
   logic intr_test_prog_lvl_wd;
   logic intr_test_rd_full_wd;
   logic intr_test_rd_lvl_wd;
   logic intr_test_op_done_wd;
-  logic intr_test_err_wd;
+  logic intr_test_corr_err_wd;
   logic alert_test_we;
   logic alert_test_recov_err_wd;
-  logic alert_test_recov_mp_err_wd;
-  logic alert_test_recov_ecc_err_wd;
-  logic alert_test_fatal_intg_err_wd;
+  logic alert_test_fatal_err_wd;
   logic flash_disable_we;
   logic flash_disable_qs;
   logic flash_disable_wd;
@@ -908,43 +906,35 @@
   logic status_prog_full_qs;
   logic status_prog_empty_qs;
   logic status_init_wip_qs;
-  logic err_code_intr_en_we;
-  logic err_code_intr_en_flash_err_en_qs;
-  logic err_code_intr_en_flash_err_en_wd;
-  logic err_code_intr_en_flash_alert_en_qs;
-  logic err_code_intr_en_flash_alert_en_wd;
-  logic err_code_intr_en_oob_err_qs;
-  logic err_code_intr_en_oob_err_wd;
-  logic err_code_intr_en_mp_err_qs;
-  logic err_code_intr_en_mp_err_wd;
-  logic err_code_intr_en_ecc_single_err_qs;
-  logic err_code_intr_en_ecc_single_err_wd;
-  logic err_code_intr_en_ecc_multi_err_qs;
-  logic err_code_intr_en_ecc_multi_err_wd;
   logic err_code_we;
-  logic err_code_flash_err_qs;
-  logic err_code_flash_err_wd;
-  logic err_code_flash_alert_qs;
-  logic err_code_flash_alert_wd;
   logic err_code_oob_err_qs;
   logic err_code_oob_err_wd;
   logic err_code_mp_err_qs;
   logic err_code_mp_err_wd;
-  logic err_code_ecc_single_err_qs;
-  logic err_code_ecc_single_err_wd;
-  logic err_code_ecc_multi_err_qs;
-  logic err_code_ecc_multi_err_wd;
-  logic [8:0] err_addr_qs;
+  logic err_code_rd_err_qs;
+  logic err_code_rd_err_wd;
+  logic err_code_prog_win_err_qs;
+  logic err_code_prog_win_err_wd;
+  logic err_code_prog_type_err_qs;
+  logic err_code_prog_type_err_wd;
+  logic err_code_flash_phy_err_qs;
+  logic err_code_flash_phy_err_wd;
+  logic fault_status_oob_err_qs;
+  logic fault_status_mp_err_qs;
+  logic fault_status_rd_err_qs;
+  logic fault_status_prog_win_err_qs;
+  logic fault_status_prog_type_err_qs;
+  logic fault_status_flash_phy_err_qs;
+  logic fault_status_reg_intg_err_qs;
+  logic fault_status_phy_intg_err_qs;
+  logic [31:0] err_addr_qs;
   logic ecc_single_err_cnt_we;
-  logic [7:0] ecc_single_err_cnt_qs;
-  logic [7:0] ecc_single_err_cnt_wd;
+  logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
+  logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_wd;
+  logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
+  logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_wd;
   logic [19:0] ecc_single_err_addr_0_qs;
   logic [19:0] ecc_single_err_addr_1_qs;
-  logic ecc_multi_err_cnt_we;
-  logic [7:0] ecc_multi_err_cnt_qs;
-  logic [7:0] ecc_multi_err_cnt_wd;
-  logic [19:0] ecc_multi_err_addr_0_qs;
-  logic [19:0] ecc_multi_err_addr_1_qs;
   logic phy_err_cfg_regwen_we;
   logic phy_err_cfg_regwen_qs;
   logic phy_err_cfg_regwen_wd;
@@ -1098,29 +1088,29 @@
     .qs     (intr_state_op_done_qs)
   );
 
-  //   F[err]: 5:5
+  //   F[corr_err]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_intr_state_err (
+  ) u_intr_state_corr_err (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_state_we),
-    .wd     (intr_state_err_wd),
+    .wd     (intr_state_corr_err_wd),
 
     // from internal hardware
-    .de     (hw2reg.intr_state.err.de),
-    .d      (hw2reg.intr_state.err.d),
+    .de     (hw2reg.intr_state.corr_err.de),
+    .d      (hw2reg.intr_state.corr_err.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_state.err.q),
+    .q      (reg2hw.intr_state.corr_err.q),
 
     // to register interface (read)
-    .qs     (intr_state_err_qs)
+    .qs     (intr_state_corr_err_qs)
   );
 
 
@@ -1250,18 +1240,18 @@
     .qs     (intr_enable_op_done_qs)
   );
 
-  //   F[err]: 5:5
+  //   F[corr_err]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
-  ) u_intr_enable_err (
+  ) u_intr_enable_corr_err (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (intr_enable_we),
-    .wd     (intr_enable_err_wd),
+    .wd     (intr_enable_corr_err_wd),
 
     // from internal hardware
     .de     (1'b0),
@@ -1269,10 +1259,10 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.intr_enable.err.q),
+    .q      (reg2hw.intr_enable.corr_err.q),
 
     // to register interface (read)
-    .qs     (intr_enable_err_qs)
+    .qs     (intr_enable_corr_err_qs)
   );
 
 
@@ -1347,17 +1337,17 @@
     .qs     ()
   );
 
-  //   F[err]: 5:5
+  //   F[corr_err]: 5:5
   prim_subreg_ext #(
     .DW    (1)
-  ) u_intr_test_err (
+  ) u_intr_test_corr_err (
     .re     (1'b0),
     .we     (intr_test_we),
-    .wd     (intr_test_err_wd),
+    .wd     (intr_test_corr_err_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.intr_test.err.qe),
-    .q      (reg2hw.intr_test.err.q),
+    .qe     (reg2hw.intr_test.corr_err.qe),
+    .q      (reg2hw.intr_test.corr_err.q),
     .qs     ()
   );
 
@@ -1377,45 +1367,17 @@
     .qs     ()
   );
 
-  //   F[recov_mp_err]: 1:1
+  //   F[fatal_err]: 1:1
   prim_subreg_ext #(
     .DW    (1)
-  ) u_alert_test_recov_mp_err (
+  ) u_alert_test_fatal_err (
     .re     (1'b0),
     .we     (alert_test_we),
-    .wd     (alert_test_recov_mp_err_wd),
+    .wd     (alert_test_fatal_err_wd),
     .d      ('0),
     .qre    (),
-    .qe     (reg2hw.alert_test.recov_mp_err.qe),
-    .q      (reg2hw.alert_test.recov_mp_err.q),
-    .qs     ()
-  );
-
-  //   F[recov_ecc_err]: 2:2
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_alert_test_recov_ecc_err (
-    .re     (1'b0),
-    .we     (alert_test_we),
-    .wd     (alert_test_recov_ecc_err_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.alert_test.recov_ecc_err.qe),
-    .q      (reg2hw.alert_test.recov_ecc_err.q),
-    .qs     ()
-  );
-
-  //   F[fatal_intg_err]: 3:3
-  prim_subreg_ext #(
-    .DW    (1)
-  ) u_alert_test_fatal_intg_err (
-    .re     (1'b0),
-    .we     (alert_test_we),
-    .wd     (alert_test_fatal_intg_err_wd),
-    .d      ('0),
-    .qre    (),
-    .qe     (reg2hw.alert_test.fatal_intg_err.qe),
-    .q      (reg2hw.alert_test.fatal_intg_err.q),
+    .qe     (reg2hw.alert_test.fatal_err.qe),
+    .q      (reg2hw.alert_test.fatal_err.q),
     .qs     ()
   );
 
@@ -9548,210 +9510,8 @@
   );
 
 
-  // R[err_code_intr_en]: V(False)
-  //   F[flash_err_en]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_err_code_intr_en_flash_err_en (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_intr_en_we),
-    .wd     (err_code_intr_en_flash_err_en_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code_intr_en.flash_err_en.q),
-
-    // to register interface (read)
-    .qs     (err_code_intr_en_flash_err_en_qs)
-  );
-
-  //   F[flash_alert_en]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_err_code_intr_en_flash_alert_en (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_intr_en_we),
-    .wd     (err_code_intr_en_flash_alert_en_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code_intr_en.flash_alert_en.q),
-
-    // to register interface (read)
-    .qs     (err_code_intr_en_flash_alert_en_qs)
-  );
-
-  //   F[oob_err]: 2:2
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_err_code_intr_en_oob_err (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_intr_en_we),
-    .wd     (err_code_intr_en_oob_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code_intr_en.oob_err.q),
-
-    // to register interface (read)
-    .qs     (err_code_intr_en_oob_err_qs)
-  );
-
-  //   F[mp_err]: 3:3
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_err_code_intr_en_mp_err (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_intr_en_we),
-    .wd     (err_code_intr_en_mp_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code_intr_en.mp_err.q),
-
-    // to register interface (read)
-    .qs     (err_code_intr_en_mp_err_qs)
-  );
-
-  //   F[ecc_single_err]: 4:4
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_err_code_intr_en_ecc_single_err (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_intr_en_we),
-    .wd     (err_code_intr_en_ecc_single_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code_intr_en.ecc_single_err.q),
-
-    // to register interface (read)
-    .qs     (err_code_intr_en_ecc_single_err_qs)
-  );
-
-  //   F[ecc_multi_err]: 5:5
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
-    .RESVAL  (1'h0)
-  ) u_err_code_intr_en_ecc_multi_err (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_intr_en_we),
-    .wd     (err_code_intr_en_ecc_multi_err_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code_intr_en.ecc_multi_err.q),
-
-    // to register interface (read)
-    .qs     (err_code_intr_en_ecc_multi_err_qs)
-  );
-
-
   // R[err_code]: V(False)
-  //   F[flash_err]: 0:0
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
-    .RESVAL  (1'h0)
-  ) u_err_code_flash_err (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_we),
-    .wd     (err_code_flash_err_wd),
-
-    // from internal hardware
-    .de     (hw2reg.err_code.flash_err.de),
-    .d      (hw2reg.err_code.flash_err.d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code.flash_err.q),
-
-    // to register interface (read)
-    .qs     (err_code_flash_err_qs)
-  );
-
-  //   F[flash_alert]: 1:1
-  prim_subreg #(
-    .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
-    .RESVAL  (1'h0)
-  ) u_err_code_flash_alert (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (err_code_we),
-    .wd     (err_code_flash_alert_wd),
-
-    // from internal hardware
-    .de     (hw2reg.err_code.flash_alert.de),
-    .d      (hw2reg.err_code.flash_alert.d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.err_code.flash_alert.q),
-
-    // to register interface (read)
-    .qs     (err_code_flash_alert_qs)
-  );
-
-  //   F[oob_err]: 2:2
+  //   F[oob_err]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
@@ -9770,13 +9530,13 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.err_code.oob_err.q),
+    .q      (),
 
     // to register interface (read)
     .qs     (err_code_oob_err_qs)
   );
 
-  //   F[mp_err]: 3:3
+  //   F[mp_err]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
@@ -9795,68 +9555,320 @@
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.err_code.mp_err.q),
+    .q      (),
 
     // to register interface (read)
     .qs     (err_code_mp_err_qs)
   );
 
-  //   F[ecc_single_err]: 4:4
+  //   F[rd_err]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_err_code_ecc_single_err (
+  ) u_err_code_rd_err (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (err_code_we),
-    .wd     (err_code_ecc_single_err_wd),
+    .wd     (err_code_rd_err_wd),
 
     // from internal hardware
-    .de     (hw2reg.err_code.ecc_single_err.de),
-    .d      (hw2reg.err_code.ecc_single_err.d),
+    .de     (hw2reg.err_code.rd_err.de),
+    .d      (hw2reg.err_code.rd_err.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.err_code.ecc_single_err.q),
+    .q      (),
 
     // to register interface (read)
-    .qs     (err_code_ecc_single_err_qs)
+    .qs     (err_code_rd_err_qs)
   );
 
-  //   F[ecc_multi_err]: 5:5
+  //   F[prog_win_err]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
-  ) u_err_code_ecc_multi_err (
+  ) u_err_code_prog_win_err (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (err_code_we),
-    .wd     (err_code_ecc_multi_err_wd),
+    .wd     (err_code_prog_win_err_wd),
 
     // from internal hardware
-    .de     (hw2reg.err_code.ecc_multi_err.de),
-    .d      (hw2reg.err_code.ecc_multi_err.d),
+    .de     (hw2reg.err_code.prog_win_err.de),
+    .d      (hw2reg.err_code.prog_win_err.d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.err_code.ecc_multi_err.q),
+    .q      (),
 
     // to register interface (read)
-    .qs     (err_code_ecc_multi_err_qs)
+    .qs     (err_code_prog_win_err_qs)
+  );
+
+  //   F[prog_type_err]: 4:4
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .RESVAL  (1'h0)
+  ) u_err_code_prog_type_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (err_code_we),
+    .wd     (err_code_prog_type_err_wd),
+
+    // from internal hardware
+    .de     (hw2reg.err_code.prog_type_err.de),
+    .d      (hw2reg.err_code.prog_type_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (err_code_prog_type_err_qs)
+  );
+
+  //   F[flash_phy_err]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .RESVAL  (1'h0)
+  ) u_err_code_flash_phy_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (err_code_we),
+    .wd     (err_code_flash_phy_err_wd),
+
+    // from internal hardware
+    .de     (hw2reg.err_code.flash_phy_err.de),
+    .d      (hw2reg.err_code.flash_phy_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (err_code_flash_phy_err_qs)
+  );
+
+
+  // R[fault_status]: V(False)
+  //   F[oob_err]: 0:0
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_oob_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.oob_err.de),
+    .d      (hw2reg.fault_status.oob_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.oob_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_oob_err_qs)
+  );
+
+  //   F[mp_err]: 1:1
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_mp_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.mp_err.de),
+    .d      (hw2reg.fault_status.mp_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.mp_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_mp_err_qs)
+  );
+
+  //   F[rd_err]: 2:2
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_rd_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.rd_err.de),
+    .d      (hw2reg.fault_status.rd_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.rd_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_rd_err_qs)
+  );
+
+  //   F[prog_win_err]: 3:3
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_prog_win_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.prog_win_err.de),
+    .d      (hw2reg.fault_status.prog_win_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.prog_win_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_prog_win_err_qs)
+  );
+
+  //   F[prog_type_err]: 4:4
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_prog_type_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.prog_type_err.de),
+    .d      (hw2reg.fault_status.prog_type_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.prog_type_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_prog_type_err_qs)
+  );
+
+  //   F[flash_phy_err]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_flash_phy_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.flash_phy_err.de),
+    .d      (hw2reg.fault_status.flash_phy_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.flash_phy_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_flash_phy_err_qs)
+  );
+
+  //   F[reg_intg_err]: 6:6
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_reg_intg_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.reg_intg_err.de),
+    .d      (hw2reg.fault_status.reg_intg_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.reg_intg_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_reg_intg_err_qs)
+  );
+
+  //   F[phy_intg_err]: 7:7
+  prim_subreg #(
+    .DW      (1),
+    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .RESVAL  (1'h0)
+  ) u_fault_status_phy_intg_err (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (1'b0),
+    .wd     ('0),
+
+    // from internal hardware
+    .de     (hw2reg.fault_status.phy_intg_err.de),
+    .d      (hw2reg.fault_status.phy_intg_err.d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.fault_status.phy_intg_err.q),
+
+    // to register interface (read)
+    .qs     (fault_status_phy_intg_err_qs)
   );
 
 
   // R[err_addr]: V(False)
   prim_subreg #(
-    .DW      (9),
+    .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
-    .RESVAL  (9'h0)
+    .RESVAL  (32'h0)
   ) u_err_addr (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
@@ -9878,29 +9890,56 @@
   );
 
 
+  // Subregister 0 of Multireg ecc_single_err_cnt
   // R[ecc_single_err_cnt]: V(False)
+  //   F[ecc_single_err_cnt_0]: 7:0
   prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (8'h0)
-  ) u_ecc_single_err_cnt (
+  ) u_ecc_single_err_cnt_ecc_single_err_cnt_0 (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),
 
     // from register interface
     .we     (ecc_single_err_cnt_we),
-    .wd     (ecc_single_err_cnt_wd),
+    .wd     (ecc_single_err_cnt_ecc_single_err_cnt_0_wd),
 
     // from internal hardware
-    .de     (hw2reg.ecc_single_err_cnt.de),
-    .d      (hw2reg.ecc_single_err_cnt.d),
+    .de     (hw2reg.ecc_single_err_cnt[0].de),
+    .d      (hw2reg.ecc_single_err_cnt[0].d),
 
     // to internal hardware
     .qe     (),
-    .q      (reg2hw.ecc_single_err_cnt.q),
+    .q      (reg2hw.ecc_single_err_cnt[0].q),
 
     // to register interface (read)
-    .qs     (ecc_single_err_cnt_qs)
+    .qs     (ecc_single_err_cnt_ecc_single_err_cnt_0_qs)
+  );
+
+  //   F[ecc_single_err_cnt_1]: 15:8
+  prim_subreg #(
+    .DW      (8),
+    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .RESVAL  (8'h0)
+  ) u_ecc_single_err_cnt_ecc_single_err_cnt_1 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (ecc_single_err_cnt_we),
+    .wd     (ecc_single_err_cnt_ecc_single_err_cnt_1_wd),
+
+    // from internal hardware
+    .de     (hw2reg.ecc_single_err_cnt[1].de),
+    .d      (hw2reg.ecc_single_err_cnt[1].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ecc_single_err_cnt[1].q),
+
+    // to register interface (read)
+    .qs     (ecc_single_err_cnt_ecc_single_err_cnt_1_qs)
   );
 
 
@@ -9958,86 +9997,6 @@
   );
 
 
-  // R[ecc_multi_err_cnt]: V(False)
-  prim_subreg #(
-    .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
-    .RESVAL  (8'h0)
-  ) u_ecc_multi_err_cnt (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (ecc_multi_err_cnt_we),
-    .wd     (ecc_multi_err_cnt_wd),
-
-    // from internal hardware
-    .de     (hw2reg.ecc_multi_err_cnt.de),
-    .d      (hw2reg.ecc_multi_err_cnt.d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.ecc_multi_err_cnt.q),
-
-    // to register interface (read)
-    .qs     (ecc_multi_err_cnt_qs)
-  );
-
-
-  // Subregister 0 of Multireg ecc_multi_err_addr
-  // R[ecc_multi_err_addr_0]: V(False)
-  prim_subreg #(
-    .DW      (20),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
-    .RESVAL  (20'h0)
-  ) u_ecc_multi_err_addr_0 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (1'b0),
-    .wd     ('0),
-
-    // from internal hardware
-    .de     (hw2reg.ecc_multi_err_addr[0].de),
-    .d      (hw2reg.ecc_multi_err_addr[0].d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (),
-
-    // to register interface (read)
-    .qs     (ecc_multi_err_addr_0_qs)
-  );
-
-
-  // Subregister 1 of Multireg ecc_multi_err_addr
-  // R[ecc_multi_err_addr_1]: V(False)
-  prim_subreg #(
-    .DW      (20),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
-    .RESVAL  (20'h0)
-  ) u_ecc_multi_err_addr_1 (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-
-    // from register interface
-    .we     (1'b0),
-    .wd     ('0),
-
-    // from internal hardware
-    .de     (hw2reg.ecc_multi_err_addr[1].de),
-    .d      (hw2reg.ecc_multi_err_addr[1].d),
-
-    // to internal hardware
-    .qe     (),
-    .q      (),
-
-    // to register interface (read)
-    .qs     (ecc_multi_err_addr_1_qs)
-  );
-
-
   // R[phy_err_cfg_regwen]: V(False)
   prim_subreg #(
     .DW      (1),
@@ -10324,7 +10283,7 @@
 
 
 
-  logic [99:0] addr_hit;
+  logic [96:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
@@ -10411,22 +10370,19 @@
     addr_hit[81] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
     addr_hit[82] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
     addr_hit[83] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
-    addr_hit[84] = (reg_addr == FLASH_CTRL_ERR_CODE_INTR_EN_OFFSET);
-    addr_hit[85] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
+    addr_hit[84] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
+    addr_hit[85] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
     addr_hit[86] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
     addr_hit[87] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
     addr_hit[88] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
     addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
-    addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_CNT_OFFSET);
-    addr_hit[91] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_ADDR_0_OFFSET);
-    addr_hit[92] = (reg_addr == FLASH_CTRL_ECC_MULTI_ERR_ADDR_1_OFFSET);
-    addr_hit[93] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET);
-    addr_hit[94] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_OFFSET);
-    addr_hit[95] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
-    addr_hit[96] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
-    addr_hit[97] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
-    addr_hit[98] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
-    addr_hit[99] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+    addr_hit[90] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET);
+    addr_hit[91] = (reg_addr == FLASH_CTRL_PHY_ERR_CFG_OFFSET);
+    addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
+    addr_hit[93] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+    addr_hit[94] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+    addr_hit[95] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+    addr_hit[96] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -10530,10 +10486,7 @@
                (addr_hit[93] & (|(FLASH_CTRL_CORE_PERMIT[93] & ~reg_be))) |
                (addr_hit[94] & (|(FLASH_CTRL_CORE_PERMIT[94] & ~reg_be))) |
                (addr_hit[95] & (|(FLASH_CTRL_CORE_PERMIT[95] & ~reg_be))) |
-               (addr_hit[96] & (|(FLASH_CTRL_CORE_PERMIT[96] & ~reg_be))) |
-               (addr_hit[97] & (|(FLASH_CTRL_CORE_PERMIT[97] & ~reg_be))) |
-               (addr_hit[98] & (|(FLASH_CTRL_CORE_PERMIT[98] & ~reg_be))) |
-               (addr_hit[99] & (|(FLASH_CTRL_CORE_PERMIT[99] & ~reg_be)))));
+               (addr_hit[96] & (|(FLASH_CTRL_CORE_PERMIT[96] & ~reg_be)))));
   end
   assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
 
@@ -10547,7 +10500,7 @@
 
   assign intr_state_op_done_wd = reg_wdata[4];
 
-  assign intr_state_err_wd = reg_wdata[5];
+  assign intr_state_corr_err_wd = reg_wdata[5];
   assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
 
   assign intr_enable_prog_empty_wd = reg_wdata[0];
@@ -10560,7 +10513,7 @@
 
   assign intr_enable_op_done_wd = reg_wdata[4];
 
-  assign intr_enable_err_wd = reg_wdata[5];
+  assign intr_enable_corr_err_wd = reg_wdata[5];
   assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
 
   assign intr_test_prog_empty_wd = reg_wdata[0];
@@ -10573,16 +10526,12 @@
 
   assign intr_test_op_done_wd = reg_wdata[4];
 
-  assign intr_test_err_wd = reg_wdata[5];
+  assign intr_test_corr_err_wd = reg_wdata[5];
   assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
 
   assign alert_test_recov_err_wd = reg_wdata[0];
 
-  assign alert_test_recov_mp_err_wd = reg_wdata[1];
-
-  assign alert_test_recov_ecc_err_wd = reg_wdata[2];
-
-  assign alert_test_fatal_intg_err_wd = reg_wdata[3];
+  assign alert_test_fatal_err_wd = reg_wdata[1];
   assign flash_disable_we = addr_hit[4] & reg_we & !reg_error;
 
   assign flash_disable_wd = reg_wdata[0];
@@ -11286,58 +11235,44 @@
   assign op_status_done_wd = reg_wdata[0];
 
   assign op_status_err_wd = reg_wdata[1];
-  assign err_code_intr_en_we = addr_hit[84] & reg_we & !reg_error;
+  assign err_code_we = addr_hit[84] & reg_we & !reg_error;
 
-  assign err_code_intr_en_flash_err_en_wd = reg_wdata[0];
+  assign err_code_oob_err_wd = reg_wdata[0];
 
-  assign err_code_intr_en_flash_alert_en_wd = reg_wdata[1];
+  assign err_code_mp_err_wd = reg_wdata[1];
 
-  assign err_code_intr_en_oob_err_wd = reg_wdata[2];
+  assign err_code_rd_err_wd = reg_wdata[2];
 
-  assign err_code_intr_en_mp_err_wd = reg_wdata[3];
+  assign err_code_prog_win_err_wd = reg_wdata[3];
 
-  assign err_code_intr_en_ecc_single_err_wd = reg_wdata[4];
+  assign err_code_prog_type_err_wd = reg_wdata[4];
 
-  assign err_code_intr_en_ecc_multi_err_wd = reg_wdata[5];
-  assign err_code_we = addr_hit[85] & reg_we & !reg_error;
-
-  assign err_code_flash_err_wd = reg_wdata[0];
-
-  assign err_code_flash_alert_wd = reg_wdata[1];
-
-  assign err_code_oob_err_wd = reg_wdata[2];
-
-  assign err_code_mp_err_wd = reg_wdata[3];
-
-  assign err_code_ecc_single_err_wd = reg_wdata[4];
-
-  assign err_code_ecc_multi_err_wd = reg_wdata[5];
+  assign err_code_flash_phy_err_wd = reg_wdata[5];
   assign ecc_single_err_cnt_we = addr_hit[87] & reg_we & !reg_error;
 
-  assign ecc_single_err_cnt_wd = reg_wdata[7:0];
-  assign ecc_multi_err_cnt_we = addr_hit[90] & reg_we & !reg_error;
+  assign ecc_single_err_cnt_ecc_single_err_cnt_0_wd = reg_wdata[7:0];
 
-  assign ecc_multi_err_cnt_wd = reg_wdata[7:0];
-  assign phy_err_cfg_regwen_we = addr_hit[93] & reg_we & !reg_error;
+  assign ecc_single_err_cnt_ecc_single_err_cnt_1_wd = reg_wdata[15:8];
+  assign phy_err_cfg_regwen_we = addr_hit[90] & reg_we & !reg_error;
 
   assign phy_err_cfg_regwen_wd = reg_wdata[0];
-  assign phy_err_cfg_we = addr_hit[94] & reg_we & !reg_error;
+  assign phy_err_cfg_we = addr_hit[91] & reg_we & !reg_error;
 
   assign phy_err_cfg_wd = reg_wdata[0];
-  assign phy_alert_cfg_we = addr_hit[95] & reg_we & !reg_error;
+  assign phy_alert_cfg_we = addr_hit[92] & reg_we & !reg_error;
 
   assign phy_alert_cfg_alert_ack_wd = reg_wdata[0];
 
   assign phy_alert_cfg_alert_trig_wd = reg_wdata[1];
-  assign scratch_we = addr_hit[97] & reg_we & !reg_error;
+  assign scratch_we = addr_hit[94] & reg_we & !reg_error;
 
   assign scratch_wd = reg_wdata[31:0];
-  assign fifo_lvl_we = addr_hit[98] & reg_we & !reg_error;
+  assign fifo_lvl_we = addr_hit[95] & reg_we & !reg_error;
 
   assign fifo_lvl_prog_wd = reg_wdata[4:0];
 
   assign fifo_lvl_rd_wd = reg_wdata[12:8];
-  assign fifo_rst_we = addr_hit[99] & reg_we & !reg_error;
+  assign fifo_rst_we = addr_hit[96] & reg_we & !reg_error;
 
   assign fifo_rst_wd = reg_wdata[0];
 
@@ -11351,7 +11286,7 @@
         reg_rdata_next[2] = intr_state_rd_full_qs;
         reg_rdata_next[3] = intr_state_rd_lvl_qs;
         reg_rdata_next[4] = intr_state_op_done_qs;
-        reg_rdata_next[5] = intr_state_err_qs;
+        reg_rdata_next[5] = intr_state_corr_err_qs;
       end
 
       addr_hit[1]: begin
@@ -11360,7 +11295,7 @@
         reg_rdata_next[2] = intr_enable_rd_full_qs;
         reg_rdata_next[3] = intr_enable_rd_lvl_qs;
         reg_rdata_next[4] = intr_enable_op_done_qs;
-        reg_rdata_next[5] = intr_enable_err_qs;
+        reg_rdata_next[5] = intr_enable_corr_err_qs;
       end
 
       addr_hit[2]: begin
@@ -11375,8 +11310,6 @@
       addr_hit[3]: begin
         reg_rdata_next[0] = '0;
         reg_rdata_next[1] = '0;
-        reg_rdata_next[2] = '0;
-        reg_rdata_next[3] = '0;
       end
 
       addr_hit[4]: begin
@@ -11938,29 +11871,32 @@
       end
 
       addr_hit[84]: begin
-        reg_rdata_next[0] = err_code_intr_en_flash_err_en_qs;
-        reg_rdata_next[1] = err_code_intr_en_flash_alert_en_qs;
-        reg_rdata_next[2] = err_code_intr_en_oob_err_qs;
-        reg_rdata_next[3] = err_code_intr_en_mp_err_qs;
-        reg_rdata_next[4] = err_code_intr_en_ecc_single_err_qs;
-        reg_rdata_next[5] = err_code_intr_en_ecc_multi_err_qs;
+        reg_rdata_next[0] = err_code_oob_err_qs;
+        reg_rdata_next[1] = err_code_mp_err_qs;
+        reg_rdata_next[2] = err_code_rd_err_qs;
+        reg_rdata_next[3] = err_code_prog_win_err_qs;
+        reg_rdata_next[4] = err_code_prog_type_err_qs;
+        reg_rdata_next[5] = err_code_flash_phy_err_qs;
       end
 
       addr_hit[85]: begin
-        reg_rdata_next[0] = err_code_flash_err_qs;
-        reg_rdata_next[1] = err_code_flash_alert_qs;
-        reg_rdata_next[2] = err_code_oob_err_qs;
-        reg_rdata_next[3] = err_code_mp_err_qs;
-        reg_rdata_next[4] = err_code_ecc_single_err_qs;
-        reg_rdata_next[5] = err_code_ecc_multi_err_qs;
+        reg_rdata_next[0] = fault_status_oob_err_qs;
+        reg_rdata_next[1] = fault_status_mp_err_qs;
+        reg_rdata_next[2] = fault_status_rd_err_qs;
+        reg_rdata_next[3] = fault_status_prog_win_err_qs;
+        reg_rdata_next[4] = fault_status_prog_type_err_qs;
+        reg_rdata_next[5] = fault_status_flash_phy_err_qs;
+        reg_rdata_next[6] = fault_status_reg_intg_err_qs;
+        reg_rdata_next[7] = fault_status_phy_intg_err_qs;
       end
 
       addr_hit[86]: begin
-        reg_rdata_next[8:0] = err_addr_qs;
+        reg_rdata_next[31:0] = err_addr_qs;
       end
 
       addr_hit[87]: begin
-        reg_rdata_next[7:0] = ecc_single_err_cnt_qs;
+        reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
+        reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
       end
 
       addr_hit[88]: begin
@@ -11972,46 +11908,34 @@
       end
 
       addr_hit[90]: begin
-        reg_rdata_next[7:0] = ecc_multi_err_cnt_qs;
-      end
-
-      addr_hit[91]: begin
-        reg_rdata_next[19:0] = ecc_multi_err_addr_0_qs;
-      end
-
-      addr_hit[92]: begin
-        reg_rdata_next[19:0] = ecc_multi_err_addr_1_qs;
-      end
-
-      addr_hit[93]: begin
         reg_rdata_next[0] = phy_err_cfg_regwen_qs;
       end
 
-      addr_hit[94]: begin
+      addr_hit[91]: begin
         reg_rdata_next[0] = phy_err_cfg_qs;
       end
 
-      addr_hit[95]: begin
+      addr_hit[92]: begin
         reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
         reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
       end
 
-      addr_hit[96]: begin
+      addr_hit[93]: begin
         reg_rdata_next[0] = phy_status_init_wip_qs;
         reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
         reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
       end
 
-      addr_hit[97]: begin
+      addr_hit[94]: begin
         reg_rdata_next[31:0] = scratch_qs;
       end
 
-      addr_hit[98]: begin
+      addr_hit[95]: begin
         reg_rdata_next[4:0] = fifo_lvl_prog_qs;
         reg_rdata_next[12:8] = fifo_lvl_rd_qs;
       end
 
-      addr_hit[99]: begin
+      addr_hit[96]: begin
         reg_rdata_next[0] = fifo_rst_qs;
       end
 

diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
index 07e2a76..972f9cd 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv

@@ -370,10 +370,7 @@
     logic [BusWidth-1:0] rd_data;
     logic                init_busy;
     logic                flash_err;
-    logic                flash_alert_p;
-    logic                flash_alert_n;
     logic [NumBanks-1:0] ecc_single_err;
-    logic [NumBanks-1:0] ecc_multi_err;
     logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
     jtag_pkg::jtag_rsp_t jtag_rsp;
     logic                intg_err;
@@ -389,10 +386,7 @@
     rd_data:            '0,
     init_busy:          1'b0,
     flash_err:          1'b0,
-    flash_alert_p:      1'b0,
-    flash_alert_n:      1'b1,
     ecc_single_err:     '0,
-    ecc_multi_err:      '0,
     ecc_addr:           '0,
     jtag_rsp:           '0,
     intg_err:           '0
@@ -474,6 +468,27 @@
     FlashLcDftLast
   } flash_lc_jtag_e;
 
+  // Error bit positioning
+  typedef struct packed {
+    logic oob_err;
+    logic mp_err;
+    logic rd_err;
+    logic prog_win_err;
+    logic prog_type_err;
+    logic phy_err;
+  } flash_ctrl_err_t;
+
+  // interrupt bit positioning
+  typedef enum logic[2:0] {
+    ProgEmpty,
+    ProgLvl,
+    RdFull,
+    RdLvl,
+    OpDone,
+    CorrErr,
+    LastIntrIdx
+  } flash_ctrl_intr_e;
+
   // find the max number pages among info types
   function automatic integer max_info_pages(int infos[InfoTypes]);
     int current_max = 0;

diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
index a069b9f..7a10dce 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv

@@ -20,7 +20,7 @@
   parameter int BytesPerWord = 8;
   parameter int BytesPerPage = 2048;
   parameter int BytesPerBank = 524288;
-  parameter int NumAlerts = 4;
+  parameter int NumAlerts = 2;
 
   // Address widths within the block
   parameter int CoreAw = 9;
@@ -49,7 +49,7 @@
     } op_done;
     struct packed {
       logic        q;
-    } err;
+    } corr_err;
   } flash_ctrl_reg2hw_intr_state_reg_t;
 
   typedef struct packed {
@@ -70,7 +70,7 @@
     } op_done;
     struct packed {
       logic        q;
-    } err;
+    } corr_err;
   } flash_ctrl_reg2hw_intr_enable_reg_t;
 
   typedef struct packed {
@@ -97,7 +97,7 @@
     struct packed {
       logic        q;
       logic        qe;
-    } err;
+    } corr_err;
   } flash_ctrl_reg2hw_intr_test_reg_t;
 
   typedef struct packed {
@@ -108,15 +108,7 @@
     struct packed {
       logic        q;
       logic        qe;
-    } recov_mp_err;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } recov_ecc_err;
-    struct packed {
-      logic        q;
-      logic        qe;
-    } fatal_intg_err;
+    } fatal_err;
   } flash_ctrl_reg2hw_alert_test_reg_t;
 
   typedef struct packed {
@@ -370,52 +362,33 @@
   typedef struct packed {
     struct packed {
       logic        q;
-    } flash_err_en;
-    struct packed {
-      logic        q;
-    } flash_alert_en;
-    struct packed {
-      logic        q;
     } oob_err;
     struct packed {
       logic        q;
     } mp_err;
     struct packed {
       logic        q;
-    } ecc_single_err;
+    } rd_err;
     struct packed {
       logic        q;
-    } ecc_multi_err;
-  } flash_ctrl_reg2hw_err_code_intr_en_reg_t;
-
-  typedef struct packed {
+    } prog_win_err;
     struct packed {
       logic        q;
-    } flash_err;
+    } prog_type_err;
     struct packed {
       logic        q;
-    } flash_alert;
+    } flash_phy_err;
     struct packed {
       logic        q;
-    } oob_err;
+    } reg_intg_err;
     struct packed {
       logic        q;
-    } mp_err;
-    struct packed {
-      logic        q;
-    } ecc_single_err;
-    struct packed {
-      logic        q;
-    } ecc_multi_err;
-  } flash_ctrl_reg2hw_err_code_reg_t;
+    } phy_intg_err;
+  } flash_ctrl_reg2hw_fault_status_reg_t;
 
   typedef struct packed {
     logic [7:0]  q;
-  } flash_ctrl_reg2hw_ecc_single_err_cnt_reg_t;
-
-  typedef struct packed {
-    logic [7:0]  q;
-  } flash_ctrl_reg2hw_ecc_multi_err_cnt_reg_t;
+  } flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t;
 
   typedef struct packed {
     logic        q;
@@ -471,7 +444,7 @@
     struct packed {
       logic        d;
       logic        de;
-    } err;
+    } corr_err;
   } flash_ctrl_hw2reg_intr_state_reg_t;
 
   typedef struct packed {
@@ -528,11 +501,30 @@
     struct packed {
       logic        d;
       logic        de;
-    } flash_err;
+    } oob_err;
     struct packed {
       logic        d;
       logic        de;
-    } flash_alert;
+    } mp_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } rd_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } prog_win_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } prog_type_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } flash_phy_err;
+  } flash_ctrl_hw2reg_err_code_reg_t;
+
+  typedef struct packed {
     struct packed {
       logic        d;
       logic        de;
@@ -544,22 +536,38 @@
     struct packed {
       logic        d;
       logic        de;
-    } ecc_single_err;
+    } rd_err;
     struct packed {
       logic        d;
       logic        de;
-    } ecc_multi_err;
-  } flash_ctrl_hw2reg_err_code_reg_t;
+    } prog_win_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } prog_type_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } flash_phy_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } reg_intg_err;
+    struct packed {
+      logic        d;
+      logic        de;
+    } phy_intg_err;
+  } flash_ctrl_hw2reg_fault_status_reg_t;
 
   typedef struct packed {
-    logic [8:0]  d;
+    logic [31:0] d;
     logic        de;
   } flash_ctrl_hw2reg_err_addr_reg_t;
 
   typedef struct packed {
     logic [7:0]  d;
     logic        de;
-  } flash_ctrl_hw2reg_ecc_single_err_cnt_reg_t;
+  } flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t;
 
   typedef struct packed {
     logic [19:0] d;
@@ -567,16 +575,6 @@
   } flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t;
 
   typedef struct packed {
-    logic [7:0]  d;
-    logic        de;
-  } flash_ctrl_hw2reg_ecc_multi_err_cnt_reg_t;
-
-  typedef struct packed {
-    logic [19:0] d;
-    logic        de;
-  } flash_ctrl_hw2reg_ecc_multi_err_addr_mreg_t;
-
-  typedef struct packed {
     struct packed {
       logic        d;
       logic        de;
@@ -593,29 +591,27 @@
 
   // Register -> HW type for core interface
   typedef struct packed {
-    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [560:555]
-    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [554:549]
-    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [548:537]
-    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [536:529]
-    flash_ctrl_reg2hw_flash_disable_reg_t flash_disable; // [528:528]
-    flash_ctrl_reg2hw_init_reg_t init; // [527:527]
-    flash_ctrl_reg2hw_control_reg_t control; // [526:507]
-    flash_ctrl_reg2hw_addr_reg_t addr; // [506:475]
-    flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [474:473]
-    flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [472:472]
-    flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [471:264]
-    flash_ctrl_reg2hw_default_region_reg_t default_region; // [263:258]
-    flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [9:0] bank0_info0_page_cfg; // [257:188]
-    flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [0:0] bank0_info1_page_cfg; // [187:181]
-    flash_ctrl_reg2hw_bank0_info2_page_cfg_mreg_t [1:0] bank0_info2_page_cfg; // [180:167]
-    flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [9:0] bank1_info0_page_cfg; // [166:97]
-    flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [0:0] bank1_info1_page_cfg; // [96:90]
-    flash_ctrl_reg2hw_bank1_info2_page_cfg_mreg_t [1:0] bank1_info2_page_cfg; // [89:76]
-    flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [75:74]
-    flash_ctrl_reg2hw_err_code_intr_en_reg_t err_code_intr_en; // [73:68]
-    flash_ctrl_reg2hw_err_code_reg_t err_code; // [67:62]
-    flash_ctrl_reg2hw_ecc_single_err_cnt_reg_t ecc_single_err_cnt; // [61:54]
-    flash_ctrl_reg2hw_ecc_multi_err_cnt_reg_t ecc_multi_err_cnt; // [53:46]
+    flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [552:547]
+    flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [546:541]
+    flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [540:529]
+    flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [528:525]
+    flash_ctrl_reg2hw_flash_disable_reg_t flash_disable; // [524:524]
+    flash_ctrl_reg2hw_init_reg_t init; // [523:523]
+    flash_ctrl_reg2hw_control_reg_t control; // [522:503]
+    flash_ctrl_reg2hw_addr_reg_t addr; // [502:471]
+    flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [470:469]
+    flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [468:468]
+    flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [467:260]
+    flash_ctrl_reg2hw_default_region_reg_t default_region; // [259:254]
+    flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [9:0] bank0_info0_page_cfg; // [253:184]
+    flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [0:0] bank0_info1_page_cfg; // [183:177]
+    flash_ctrl_reg2hw_bank0_info2_page_cfg_mreg_t [1:0] bank0_info2_page_cfg; // [176:163]
+    flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [9:0] bank1_info0_page_cfg; // [162:93]
+    flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [0:0] bank1_info1_page_cfg; // [92:86]
+    flash_ctrl_reg2hw_bank1_info2_page_cfg_mreg_t [1:0] bank1_info2_page_cfg; // [85:72]
+    flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [71:70]
+    flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [69:62]
+    flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [61:46]
     flash_ctrl_reg2hw_phy_err_cfg_reg_t phy_err_cfg; // [45:45]
     flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
     flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
@@ -625,18 +621,17 @@
 
   // HW -> register type for core interface
   typedef struct packed {
-    flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [160:149]
-    flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [148:148]
-    flash_ctrl_hw2reg_control_reg_t control; // [147:146]
-    flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [145:144]
-    flash_ctrl_hw2reg_op_status_reg_t op_status; // [143:140]
-    flash_ctrl_hw2reg_status_reg_t status; // [139:130]
-    flash_ctrl_hw2reg_err_code_reg_t err_code; // [129:118]
-    flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [117:108]
-    flash_ctrl_hw2reg_ecc_single_err_cnt_reg_t ecc_single_err_cnt; // [107:99]
-    flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [98:57]
-    flash_ctrl_hw2reg_ecc_multi_err_cnt_reg_t ecc_multi_err_cnt; // [56:48]
-    flash_ctrl_hw2reg_ecc_multi_err_addr_mreg_t [1:0] ecc_multi_err_addr; // [47:6]
+    flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [157:146]
+    flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [145:145]
+    flash_ctrl_hw2reg_control_reg_t control; // [144:143]
+    flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [142:141]
+    flash_ctrl_hw2reg_op_status_reg_t op_status; // [140:137]
+    flash_ctrl_hw2reg_status_reg_t status; // [136:127]
+    flash_ctrl_hw2reg_err_code_reg_t err_code; // [126:115]
+    flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [114:99]
+    flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [98:66]
+    flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [65:48]
+    flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [47:6]
     flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [5:0]
   } flash_ctrl_core_hw2reg_t;
 
@@ -725,22 +720,19 @@
   parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h 144;
   parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 148;
   parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 14c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_INTR_EN_OFFSET = 9'h 150;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 154;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 150;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 154;
   parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 158;
   parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 15c;
   parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 160;
   parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 164;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_CNT_OFFSET = 9'h 168;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_ADDR_0_OFFSET = 9'h 16c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_MULTI_ERR_ADDR_1_OFFSET = 9'h 170;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET = 9'h 174;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_OFFSET = 9'h 178;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 17c;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 180;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 184;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 188;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 18c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_REGWEN_OFFSET = 9'h 168;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ERR_CFG_OFFSET = 9'h 16c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 170;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 174;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 178;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 17c;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 180;
 
   // Reset values for hwext registers and their fields for core interface
   parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h 0;
@@ -749,19 +741,17 @@
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
-  parameter logic [0:0] FLASH_CTRL_INTR_TEST_ERR_RESVAL = 1'h 0;
-  parameter logic [3:0] FLASH_CTRL_ALERT_TEST_RESVAL = 4'h 0;
+  parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
+  parameter logic [1:0] FLASH_CTRL_ALERT_TEST_RESVAL = 2'h 0;
   parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
-  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_MP_ERR_RESVAL = 1'h 0;
-  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ECC_ERR_RESVAL = 1'h 0;
-  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_INTG_ERR_RESVAL = 1'h 0;
+  parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
   parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
 
   // Window parameters for core interface
-  parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 190;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 184;
   parameter int unsigned       FLASH_CTRL_PROG_FIFO_SIZE   = 'h 4;
-  parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 194;
+  parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 188;
   parameter int unsigned       FLASH_CTRL_RD_FIFO_SIZE   = 'h 4;
 
   // Register index for core interface
@@ -850,15 +840,12 @@
     FLASH_CTRL_MP_BANK_CFG,
     FLASH_CTRL_OP_STATUS,
     FLASH_CTRL_STATUS,
-    FLASH_CTRL_ERR_CODE_INTR_EN,
     FLASH_CTRL_ERR_CODE,
+    FLASH_CTRL_FAULT_STATUS,
     FLASH_CTRL_ERR_ADDR,
     FLASH_CTRL_ECC_SINGLE_ERR_CNT,
     FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0,
     FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1,
-    FLASH_CTRL_ECC_MULTI_ERR_CNT,
-    FLASH_CTRL_ECC_MULTI_ERR_ADDR_0,
-    FLASH_CTRL_ECC_MULTI_ERR_ADDR_1,
     FLASH_CTRL_PHY_ERR_CFG_REGWEN,
     FLASH_CTRL_PHY_ERR_CFG,
     FLASH_CTRL_PHY_ALERT_CFG,
@@ -869,7 +856,7 @@
   } flash_ctrl_core_id_e;
 
   // Register width information to check illegal writes for core interface
-  parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [100] = '{
+  parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [97] = '{
     4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
     4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
     4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
@@ -954,22 +941,19 @@
     4'b 0001, // index[81] FLASH_CTRL_MP_BANK_CFG
     4'b 0001, // index[82] FLASH_CTRL_OP_STATUS
     4'b 0001, // index[83] FLASH_CTRL_STATUS
-    4'b 0001, // index[84] FLASH_CTRL_ERR_CODE_INTR_EN
-    4'b 0001, // index[85] FLASH_CTRL_ERR_CODE
-    4'b 0011, // index[86] FLASH_CTRL_ERR_ADDR
-    4'b 0001, // index[87] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+    4'b 0001, // index[84] FLASH_CTRL_ERR_CODE
+    4'b 0001, // index[85] FLASH_CTRL_FAULT_STATUS
+    4'b 1111, // index[86] FLASH_CTRL_ERR_ADDR
+    4'b 0011, // index[87] FLASH_CTRL_ECC_SINGLE_ERR_CNT
     4'b 0111, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
     4'b 0111, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
-    4'b 0001, // index[90] FLASH_CTRL_ECC_MULTI_ERR_CNT
-    4'b 0111, // index[91] FLASH_CTRL_ECC_MULTI_ERR_ADDR_0
-    4'b 0111, // index[92] FLASH_CTRL_ECC_MULTI_ERR_ADDR_1
-    4'b 0001, // index[93] FLASH_CTRL_PHY_ERR_CFG_REGWEN
-    4'b 0001, // index[94] FLASH_CTRL_PHY_ERR_CFG
-    4'b 0001, // index[95] FLASH_CTRL_PHY_ALERT_CFG
-    4'b 0001, // index[96] FLASH_CTRL_PHY_STATUS
-    4'b 1111, // index[97] FLASH_CTRL_SCRATCH
-    4'b 0011, // index[98] FLASH_CTRL_FIFO_LVL
-    4'b 0001  // index[99] FLASH_CTRL_FIFO_RST
+    4'b 0001, // index[90] FLASH_CTRL_PHY_ERR_CFG_REGWEN
+    4'b 0001, // index[91] FLASH_CTRL_PHY_ERR_CFG
+    4'b 0001, // index[92] FLASH_CTRL_PHY_ALERT_CFG
+    4'b 0001, // index[93] FLASH_CTRL_PHY_STATUS
+    4'b 1111, // index[94] FLASH_CTRL_SCRATCH
+    4'b 0011, // index[95] FLASH_CTRL_FIFO_LVL
+    4'b 0001  // index[96] FLASH_CTRL_FIFO_RST
   };
 
 endpackage

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 1d63f8b..425c2c2 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

@@ -484,7 +484,7 @@
   logic intr_flash_ctrl_rd_full;
   logic intr_flash_ctrl_rd_lvl;
   logic intr_flash_ctrl_op_done;
-  logic intr_flash_ctrl_err;
+  logic intr_flash_ctrl_corr_err;
   logic intr_hmac_hmac_done;
   logic intr_hmac_fifo_empty;
   logic intr_hmac_hmac_err;
@@ -1834,7 +1834,7 @@
   );
 
   flash_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:32]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
     .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
     .RndCnstDataKey(RndCnstFlashCtrlDataKey),
     .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -1856,13 +1856,11 @@
       .intr_rd_full_o    (intr_flash_ctrl_rd_full),
       .intr_rd_lvl_o     (intr_flash_ctrl_rd_lvl),
       .intr_op_done_o    (intr_flash_ctrl_op_done),
-      .intr_err_o        (intr_flash_ctrl_err),
+      .intr_corr_err_o   (intr_flash_ctrl_corr_err),
       // [32]: recov_err
-      // [33]: recov_mp_err
-      // [34]: recov_ecc_err
-      // [35]: fatal_intg_err
-      .alert_tx_o  ( alert_tx[35:32] ),
-      .alert_rx_i  ( alert_rx[35:32] ),
+      // [33]: fatal_err
+      .alert_tx_o  ( alert_tx[33:32] ),
+      .alert_rx_i  ( alert_rx[33:32] ),
 
       // Inter-module signals
       .otp_o(flash_ctrl_otp_req),
@@ -1903,12 +1901,12 @@
   );
 
   rv_dm #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:36]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]),
     .IdcodeValue(RvDmIdcodeValue)
   ) u_rv_dm (
-      // [36]: fatal_fault
-      .alert_tx_o  ( alert_tx[36:36] ),
-      .alert_rx_i  ( alert_rx[36:36] ),
+      // [34]: fatal_fault
+      .alert_tx_o  ( alert_tx[34:34] ),
+      .alert_rx_i  ( alert_rx[34:34] ),
 
       // Inter-module signals
       .jtag_i(pinmux_aon_rv_jtag_req),
@@ -1933,11 +1931,11 @@
   );
 
   rv_plic #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:37])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:35])
   ) u_rv_plic (
-      // [37]: fatal_fault
-      .alert_tx_o  ( alert_tx[37:37] ),
-      .alert_rx_i  ( alert_rx[37:37] ),
+      // [35]: fatal_fault
+      .alert_tx_o  ( alert_tx[35:35] ),
+      .alert_rx_i  ( alert_rx[35:35] ),
 
       // Inter-module signals
       .irq_o(rv_plic_irq),
@@ -1953,7 +1951,7 @@
   );
 
   aes #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:38]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:36]),
     .AES192Enable(1'b1),
     .Masking(AesMasking),
     .SBoxImpl(AesSBoxImpl),
@@ -1966,10 +1964,10 @@
     .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
     .RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
   ) u_aes (
-      // [38]: recov_ctrl_update_err
-      // [39]: fatal_fault
-      .alert_tx_o  ( alert_tx[39:38] ),
-      .alert_rx_i  ( alert_rx[39:38] ),
+      // [36]: recov_ctrl_update_err
+      // [37]: fatal_fault
+      .alert_tx_o  ( alert_tx[37:36] ),
+      .alert_rx_i  ( alert_rx[37:36] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[0]),
@@ -1989,16 +1987,16 @@
   );
 
   hmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38])
   ) u_hmac (
 
       // Interrupt
       .intr_hmac_done_o  (intr_hmac_hmac_done),
       .intr_fifo_empty_o (intr_hmac_fifo_empty),
       .intr_hmac_err_o   (intr_hmac_hmac_err),
-      // [40]: fatal_fault
-      .alert_tx_o  ( alert_tx[40:40] ),
-      .alert_rx_i  ( alert_rx[40:40] ),
+      // [38]: fatal_fault
+      .alert_tx_o  ( alert_tx[38:38] ),
+      .alert_rx_i  ( alert_rx[38:38] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[1]),
@@ -2011,7 +2009,7 @@
   );
 
   kmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:39]),
     .EnMasking(KmacEnMasking),
     .ReuseShare(KmacReuseShare),
     .SecCmdDelay(SecKmacCmdDelay),
@@ -2023,9 +2021,9 @@
       .intr_kmac_done_o  (intr_kmac_kmac_done),
       .intr_fifo_empty_o (intr_kmac_fifo_empty),
       .intr_kmac_err_o   (intr_kmac_kmac_err),
-      // [41]: fatal_fault
-      .alert_tx_o  ( alert_tx[41:41] ),
-      .alert_rx_i  ( alert_rx[41:41] ),
+      // [39]: fatal_fault
+      .alert_tx_o  ( alert_tx[39:39] ),
+      .alert_rx_i  ( alert_rx[39:39] ),
 
       // Inter-module signals
       .keymgr_key_i(keymgr_kmac_key),
@@ -2046,7 +2044,7 @@
   );
 
   keymgr #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]),
     .KmacEnMasking(KeymgrKmacEnMasking),
     .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
     .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
@@ -2065,10 +2063,10 @@
 
       // Interrupt
       .intr_op_done_o (intr_keymgr_op_done),
-      // [42]: fatal_fault_err
-      // [43]: recov_operation_err
-      .alert_tx_o  ( alert_tx[43:42] ),
-      .alert_rx_i  ( alert_rx[43:42] ),
+      // [40]: fatal_fault_err
+      // [41]: recov_operation_err
+      .alert_tx_o  ( alert_tx[41:40] ),
+      .alert_rx_i  ( alert_rx[41:40] ),
 
       // Inter-module signals
       .edn_o(edn0_edn_req[0]),
@@ -2097,7 +2095,7 @@
   );
 
   csrng #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:44]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
     .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
     .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
     .SBoxImpl(CsrngSBoxImpl)
@@ -2108,10 +2106,10 @@
       .intr_cs_entropy_req_o  (intr_csrng_cs_entropy_req),
       .intr_cs_hw_inst_exc_o  (intr_csrng_cs_hw_inst_exc),
       .intr_cs_fatal_err_o    (intr_csrng_cs_fatal_err),
-      // [44]: recov_alert
-      // [45]: fatal_alert
-      .alert_tx_o  ( alert_tx[45:44] ),
-      .alert_rx_i  ( alert_rx[45:44] ),
+      // [42]: recov_alert
+      // [43]: fatal_alert
+      .alert_tx_o  ( alert_tx[43:42] ),
+      .alert_rx_i  ( alert_rx[43:42] ),
 
       // Inter-module signals
       .csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2131,7 +2129,7 @@
   );
 
   entropy_src #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:44]),
     .Stub(EntropySrcStub)
   ) u_entropy_src (
 
@@ -2140,10 +2138,10 @@
       .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
       .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
       .intr_es_fatal_err_o          (intr_entropy_src_es_fatal_err),
-      // [46]: recov_alert
-      // [47]: fatal_alert
-      .alert_tx_o  ( alert_tx[47:46] ),
-      .alert_rx_i  ( alert_rx[47:46] ),
+      // [44]: recov_alert
+      // [45]: fatal_alert
+      .alert_tx_o  ( alert_tx[45:44] ),
+      .alert_rx_i  ( alert_rx[45:44] ),
 
       // Inter-module signals
       .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2166,16 +2164,16 @@
   );
 
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46])
   ) u_edn0 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn0_edn_fatal_err),
-      // [48]: recov_alert
-      // [49]: fatal_alert
-      .alert_tx_o  ( alert_tx[49:48] ),
-      .alert_rx_i  ( alert_rx[49:48] ),
+      // [46]: recov_alert
+      // [47]: fatal_alert
+      .alert_tx_o  ( alert_tx[47:46] ),
+      .alert_rx_i  ( alert_rx[47:46] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2191,16 +2189,16 @@
   );
 
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48])
   ) u_edn1 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn1_edn_fatal_err),
-      // [50]: recov_alert
-      // [51]: fatal_alert
-      .alert_tx_o  ( alert_tx[51:50] ),
-      .alert_rx_i  ( alert_rx[51:50] ),
+      // [48]: recov_alert
+      // [49]: fatal_alert
+      .alert_tx_o  ( alert_tx[49:48] ),
+      .alert_rx_i  ( alert_rx[49:48] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2216,7 +2214,7 @@
   );
 
   sram_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:52]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:50]),
     .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
     .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
     .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
@@ -2224,9 +2222,9 @@
     .MemSizeRam(131072),
     .InstrExec(SramCtrlMainInstrExec)
   ) u_sram_ctrl_main (
-      // [52]: fatal_error
-      .alert_tx_o  ( alert_tx[52:52] ),
-      .alert_rx_i  ( alert_rx[52:52] ),
+      // [50]: fatal_error
+      .alert_tx_o  ( alert_tx[50:50] ),
+      .alert_rx_i  ( alert_rx[50:50] ),
 
       // Inter-module signals
       .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2248,7 +2246,7 @@
   );
 
   otbn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]),
     .Stub(OtbnStub),
     .RegFile(OtbnRegFile),
     .RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
@@ -2259,10 +2257,10 @@
 
       // Interrupt
       .intr_done_o (intr_otbn_done),
-      // [53]: fatal
-      // [54]: recov
-      .alert_tx_o  ( alert_tx[54:53] ),
-      .alert_rx_i  ( alert_rx[54:53] ),
+      // [51]: fatal
+      // [52]: recov
+      .alert_tx_o  ( alert_tx[52:51] ),
+      .alert_rx_i  ( alert_rx[52:51] ),
 
       // Inter-module signals
       .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
@@ -2288,15 +2286,15 @@
   );
 
   rom_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:55]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]),
     .BootRomInitFile(RomCtrlBootRomInitFile),
     .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
     .RndCnstScrKey(RndCnstRomCtrlScrKey),
     .SecDisableScrambling(SecRomCtrlDisableScrambling)
   ) u_rom_ctrl (
-      // [55]: fatal
-      .alert_tx_o  ( alert_tx[55:55] ),
-      .alert_rx_i  ( alert_rx[55:55] ),
+      // [53]: fatal
+      .alert_tx_o  ( alert_tx[53:53] ),
+      .alert_rx_i  ( alert_rx[53:53] ),
 
       // Inter-module signals
       .rom_cfg_i(ast_rom_cfg),
@@ -2315,7 +2313,7 @@
   );
 
   rv_core_ibex #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:56]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:54]),
     .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed),
     .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm),
     .PMPEnable(RvCoreIbexPMPEnable),
@@ -2338,12 +2336,12 @@
     .DmExceptionAddr(RvCoreIbexDmExceptionAddr),
     .PipeLine(RvCoreIbexPipeLine)
   ) u_rv_core_ibex (
-      // [56]: fatal_sw_err
-      // [57]: recov_sw_err
-      // [58]: fatal_hw_err
-      // [59]: recov_hw_err
-      .alert_tx_o  ( alert_tx[59:56] ),
-      .alert_rx_i  ( alert_rx[59:56] ),
+      // [54]: fatal_sw_err
+      // [55]: recov_sw_err
+      // [56]: fatal_hw_err
+      // [57]: recov_hw_err
+      .alert_tx_o  ( alert_tx[57:54] ),
+      .alert_rx_i  ( alert_rx[57:54] ),
 
       // Inter-module signals
       .rst_cpu_n_o(rv_core_ibex_rst_cpu_n),
@@ -2399,7 +2397,7 @@
       intr_hmac_hmac_err, // IDs [163 +: 1]
       intr_hmac_fifo_empty, // IDs [162 +: 1]
       intr_hmac_hmac_done, // IDs [161 +: 1]
-      intr_flash_ctrl_err, // IDs [160 +: 1]
+      intr_flash_ctrl_corr_err, // IDs [160 +: 1]
       intr_flash_ctrl_op_done, // IDs [159 +: 1]
       intr_flash_ctrl_rd_lvl, // IDs [158 +: 1]
       intr_flash_ctrl_rd_full, // IDs [157 +: 1]

diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 90a6918..26800ba 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c

@@ -172,7 +172,7 @@
   [kTopEarlgreyPlicIrqIdFlashCtrlRdFull] = kTopEarlgreyPlicPeripheralFlashCtrl,
   [kTopEarlgreyPlicIrqIdFlashCtrlRdLvl] = kTopEarlgreyPlicPeripheralFlashCtrl,
   [kTopEarlgreyPlicIrqIdFlashCtrlOpDone] = kTopEarlgreyPlicPeripheralFlashCtrl,
-  [kTopEarlgreyPlicIrqIdFlashCtrlErr] = kTopEarlgreyPlicPeripheralFlashCtrl,
+  [kTopEarlgreyPlicIrqIdFlashCtrlCorrErr] = kTopEarlgreyPlicPeripheralFlashCtrl,
   [kTopEarlgreyPlicIrqIdHmacHmacDone] = kTopEarlgreyPlicPeripheralHmac,
   [kTopEarlgreyPlicIrqIdHmacFifoEmpty] = kTopEarlgreyPlicPeripheralHmac,
   [kTopEarlgreyPlicIrqIdHmacHmacErr] = kTopEarlgreyPlicPeripheralHmac,
@@ -203,7 +203,7 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[60] = {
+    top_earlgrey_alert_for_peripheral[58] = {
   [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0,
   [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1,
   [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2,
@@ -237,9 +237,7 @@
   [kTopEarlgreyAlertIdSensorCtrlFatalAlert] = kTopEarlgreyAlertPeripheralSensorCtrl,
   [kTopEarlgreyAlertIdSramCtrlRetAonFatalError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon,
   [kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
-  [kTopEarlgreyAlertIdFlashCtrlRecovMpErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
-  [kTopEarlgreyAlertIdFlashCtrlRecovEccErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
-  [kTopEarlgreyAlertIdFlashCtrlFatalIntgErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
+  [kTopEarlgreyAlertIdFlashCtrlFatalErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
   [kTopEarlgreyAlertIdRvDmFatalFault] = kTopEarlgreyAlertPeripheralRvDm,
   [kTopEarlgreyAlertIdRvPlicFatalFault] = kTopEarlgreyAlertPeripheralRvPlic,
   [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,

diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index f1fbfbf..9602486 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h

@@ -1174,7 +1174,7 @@
   kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 157, /**< flash_ctrl_rd_full */
   kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 158, /**< flash_ctrl_rd_lvl */
   kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 159, /**< flash_ctrl_op_done */
-  kTopEarlgreyPlicIrqIdFlashCtrlErr = 160, /**< flash_ctrl_err */
+  kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 160, /**< flash_ctrl_corr_err */
   kTopEarlgreyPlicIrqIdHmacHmacDone = 161, /**< hmac_hmac_done */
   kTopEarlgreyPlicIrqIdHmacFifoEmpty = 162, /**< hmac_fifo_empty */
   kTopEarlgreyPlicIrqIdHmacHmacErr = 163, /**< hmac_hmac_err */
@@ -1309,34 +1309,32 @@
   kTopEarlgreyAlertIdSensorCtrlFatalAlert = 30, /**< sensor_ctrl_fatal_alert */
   kTopEarlgreyAlertIdSramCtrlRetAonFatalError = 31, /**< sram_ctrl_ret_aon_fatal_error */
   kTopEarlgreyAlertIdFlashCtrlRecovErr = 32, /**< flash_ctrl_recov_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 33, /**< flash_ctrl_recov_mp_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 34, /**< flash_ctrl_recov_ecc_err */
-  kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 35, /**< flash_ctrl_fatal_intg_err */
-  kTopEarlgreyAlertIdRvDmFatalFault = 36, /**< rv_dm_fatal_fault */
-  kTopEarlgreyAlertIdRvPlicFatalFault = 37, /**< rv_plic_fatal_fault */
-  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 38, /**< aes_recov_ctrl_update_err */
-  kTopEarlgreyAlertIdAesFatalFault = 39, /**< aes_fatal_fault */
-  kTopEarlgreyAlertIdHmacFatalFault = 40, /**< hmac_fatal_fault */
-  kTopEarlgreyAlertIdKmacFatalFault = 41, /**< kmac_fatal_fault */
-  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 42, /**< keymgr_fatal_fault_err */
-  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 43, /**< keymgr_recov_operation_err */
-  kTopEarlgreyAlertIdCsrngRecovAlert = 44, /**< csrng_recov_alert */
-  kTopEarlgreyAlertIdCsrngFatalAlert = 45, /**< csrng_fatal_alert */
-  kTopEarlgreyAlertIdEntropySrcRecovAlert = 46, /**< entropy_src_recov_alert */
-  kTopEarlgreyAlertIdEntropySrcFatalAlert = 47, /**< entropy_src_fatal_alert */
-  kTopEarlgreyAlertIdEdn0RecovAlert = 48, /**< edn0_recov_alert */
-  kTopEarlgreyAlertIdEdn0FatalAlert = 49, /**< edn0_fatal_alert */
-  kTopEarlgreyAlertIdEdn1RecovAlert = 50, /**< edn1_recov_alert */
-  kTopEarlgreyAlertIdEdn1FatalAlert = 51, /**< edn1_fatal_alert */
-  kTopEarlgreyAlertIdSramCtrlMainFatalError = 52, /**< sram_ctrl_main_fatal_error */
-  kTopEarlgreyAlertIdOtbnFatal = 53, /**< otbn_fatal */
-  kTopEarlgreyAlertIdOtbnRecov = 54, /**< otbn_recov */
-  kTopEarlgreyAlertIdRomCtrlFatal = 55, /**< rom_ctrl_fatal */
-  kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 56, /**< rv_core_ibex_fatal_sw_err */
-  kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 57, /**< rv_core_ibex_recov_sw_err */
-  kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 58, /**< rv_core_ibex_fatal_hw_err */
-  kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 59, /**< rv_core_ibex_recov_hw_err */
-  kTopEarlgreyAlertIdLast = 59, /**< \internal The Last Valid Alert ID. */
+  kTopEarlgreyAlertIdFlashCtrlFatalErr = 33, /**< flash_ctrl_fatal_err */
+  kTopEarlgreyAlertIdRvDmFatalFault = 34, /**< rv_dm_fatal_fault */
+  kTopEarlgreyAlertIdRvPlicFatalFault = 35, /**< rv_plic_fatal_fault */
+  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 36, /**< aes_recov_ctrl_update_err */
+  kTopEarlgreyAlertIdAesFatalFault = 37, /**< aes_fatal_fault */
+  kTopEarlgreyAlertIdHmacFatalFault = 38, /**< hmac_fatal_fault */
+  kTopEarlgreyAlertIdKmacFatalFault = 39, /**< kmac_fatal_fault */
+  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 40, /**< keymgr_fatal_fault_err */
+  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 41, /**< keymgr_recov_operation_err */
+  kTopEarlgreyAlertIdCsrngRecovAlert = 42, /**< csrng_recov_alert */
+  kTopEarlgreyAlertIdCsrngFatalAlert = 43, /**< csrng_fatal_alert */
+  kTopEarlgreyAlertIdEntropySrcRecovAlert = 44, /**< entropy_src_recov_alert */
+  kTopEarlgreyAlertIdEntropySrcFatalAlert = 45, /**< entropy_src_fatal_alert */
+  kTopEarlgreyAlertIdEdn0RecovAlert = 46, /**< edn0_recov_alert */
+  kTopEarlgreyAlertIdEdn0FatalAlert = 47, /**< edn0_fatal_alert */
+  kTopEarlgreyAlertIdEdn1RecovAlert = 48, /**< edn1_recov_alert */
+  kTopEarlgreyAlertIdEdn1FatalAlert = 49, /**< edn1_fatal_alert */
+  kTopEarlgreyAlertIdSramCtrlMainFatalError = 50, /**< sram_ctrl_main_fatal_error */
+  kTopEarlgreyAlertIdOtbnFatal = 51, /**< otbn_fatal */
+  kTopEarlgreyAlertIdOtbnRecov = 52, /**< otbn_recov */
+  kTopEarlgreyAlertIdRomCtrlFatal = 53, /**< rom_ctrl_fatal */
+  kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 54, /**< rv_core_ibex_fatal_sw_err */
+  kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 55, /**< rv_core_ibex_recov_sw_err */
+  kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 56, /**< rv_core_ibex_fatal_hw_err */
+  kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 57, /**< rv_core_ibex_recov_hw_err */
+  kTopEarlgreyAlertIdLast = 57, /**< \internal The Last Valid Alert ID. */
 } top_earlgrey_alert_id_t;
 
 /**
@@ -1346,7 +1344,7 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 extern const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[60];
+    top_earlgrey_alert_for_peripheral[58];
 
 #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
commit	63a0f5e3f58641fe53c7df0d52db551219b282f4	[log] [tgz]
author	Timothy Chen <timothytim@google.com>	Wed Sep 15 15:33:06 2021 -0700
committer	tjaychen <timothytim@google.com>	Tue Sep 21 15:40:21 2021 -0700
tree	3c8911da6aaf486f88b9c0af506502bc49bee364
parent	37eec2cbcb02ab1639382d3dbb8ab2bc5b3b904d [diff]