commit 634f8cc318e778faa5fb1a5969caaaf34062c257
author Weicai Yang <weicai@google.com> Fri Oct 25 14:05:03 2019 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Fri Oct 25 18:25:11 2019 -0700
tree 86275eda6623485fd3e9c6050654f5c9b832a898
parent 7dcdbac7c595aa4f919d05b7a0e47f9a3178f4a9

[uart/dv] Fix TB diagram not show in the web

hw/ip/uart/doc/uart_dv_plan.md

diff --git a/hw/ip/uart/doc/uart_dv_plan.md b/hw/ip/uart/doc/uart_dv_plan.md
index b501c31..709fd43 100644
--- a/hw/ip/uart/doc/uart_dv_plan.md
+++ b/hw/ip/uart/doc/uart_dv_plan.md
@@ -22,7 +22,7 @@
 UART testbench has been constructed based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md).
 
 ### Block diagram
-[Block diagram](tb.svg)
+![Block diagram](tb.svg)
 
 ### Top level testbench
 Top level testbench is located at `hw/ip/uart/dv/tb/tb.sv`. It instantiates the UART DUT module `hw/ip/uart/rtl/uart.sv`.