| commit | b029556e7f3c2ba628e9c86d110792cc492f78c1 | [log] [tgz] |
|---|---|---|
| author | Silvestrs Timofejevs <silvestrst@lowrisc.org> | Tue Jan 19 10:29:35 2021 +0000 |
| committer | Silvestrs Timofejevs <silvestrst@lowrisc.org> | Wed Jan 27 16:35:30 2021 +0000 |
| tree | 9db5f052039eb8558e84eb4acf93101bfcdc9c0f | |
| parent | efa09012447465537326d1809469330f5489607d [diff] |
[sw, plic] Refactor DIF PLIC to be top level agnostic Recent OT changes have introduced "secondary" top levels, which can have different number of IP blocks (more or less than "MAIN" top_earlgrey). This has an impact on peripherals like PLIC that have number of interrupt sources and targets directly dependent on presence of IP blocks on the chip. As the result: We cannot: - Use any top_earlgrey related defines or harcoded values - Assume top_earlgrey number of targets - Assume top_earlgrey number of interrupt sources In this change we assume that related registers and multireg registers are consecutive in the address space (IE00..IENN). All the addresses are calculated at runtime, and depend on the input parameters into public API, such as interrupt source id and target id. Internal check and other calculation values come from the peripheral auto-generated definitions, which are generated per instantiation, and will always have correct parameters (NUM_SOURCES, etc...). The static asserts have been moved into the unittest, as that is expected to be top_earlgrey exclusive (at least for now). Signed-off-by: Silvestrs Timofejevs <silvestrst@lowrisc.org>
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