commit 627f782f3648293efd398045a5959509f255eacc
author Srikrishna Iyer <sriyer@google.com> Wed Jan 15 21:39:29 2020 -0800
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Tue Jan 21 12:38:46 2020 -0800
tree 41b7c9bd5815e29a3abbbbac407abb4c7c02b11e
parent 4efd35ebfa4686ed7dc2df3873753d3f063727e7

[usbdev dv] Initial dv bench

- Full UVM DV bench for usbdev
- Added a skeleton usb20 UVM agent just in case someone has BW to
develop it
- RTL and testbench compiles cleanly
- Basic CSR power on reset test passing with 100 seeds

- Added usbdev links to hw/_index.md to get it to show the USBDEV spec
and DV plan docs
- Renamed usbdev.sv tl ports from tl_d_i to tl_i and tl_d_o to tl_o
  - Reason for this is to support automation (conformity across all IPs
  helps)
- Minor fixes to uvmdvgen templates

Signed-off-by: Srikrishna Iyer <sriyer@google.com>

util/build_docs.py

diff --git a/util/build_docs.py b/util/build_docs.py
index 53a7635..7e4d065 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -81,6 +81,7 @@
         "hw/ip/rv_timer/data/rv_timer_testplan.hjson",
         "hw/ip/spi_device/data/spi_device_testplan.hjson",
         "hw/ip/uart/data/uart_testplan.hjson",
+        "hw/ip/usbdev/data/usbdev_testplan.hjson",
         "hw/ip/tlul/data/tlul_testplan.hjson",
         "hw/top_earlgrey/data/standalone_sw_testplan.hjson",
         "util/testplanner/examples/foo_testplan.hjson",