[dv] Update sec_cm testplan
Also update keymgr testplan to add additional check for sec_cm
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/dv/tools/dvsim/testplans/harden_countermeasures_testplan.hjson b/hw/dv/tools/dvsim/testplans/sec_cm_testplan.hjson
similarity index 92%
rename from hw/dv/tools/dvsim/testplans/harden_countermeasures_testplan.hjson
rename to hw/dv/tools/dvsim/testplans/sec_cm_testplan.hjson
index 7dea3a4..a283887 100644
--- a/hw/dv/tools/dvsim/testplans/harden_countermeasures_testplan.hjson
+++ b/hw/dv/tools/dvsim/testplans/sec_cm_testplan.hjson
@@ -18,7 +18,7 @@
- Check that err_code/fault_status is updated correctly and preserved until reset.
- Check the following operation should be failed if applicable.'''
milestone: V2
- tests: ["{name}_harden_countermeasures"]
+ tests: ["{name}_sec_cm"]
}
{
name: redundant_coding_fsm_check
@@ -31,7 +31,7 @@
Same checks as `one_hot_check`'''
milestone: V2
- tests: ["{name}_harden_countermeasures"]
+ tests: ["{name}_sec_cm"]
}
{
name: hardened_counter_check
@@ -45,7 +45,7 @@
Same checks as `one_hot_check`'''
milestone: V2
- tests: ["{name}_harden_countermeasures"]
+ tests: ["{name}_sec_cm"]
}
]
}
diff --git a/hw/ip/keymgr/data/keymgr_testplan.hjson b/hw/ip/keymgr/data/keymgr_testplan.hjson
index 045adf5..e5214a7 100644
--- a/hw/ip/keymgr/data/keymgr_testplan.hjson
+++ b/hw/ip/keymgr/data/keymgr_testplan.hjson
@@ -8,7 +8,7 @@
"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/harden_countermeasures_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/sec_cm_testplan.hjson",
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson"]
testpoints: [
{
@@ -179,6 +179,21 @@
tests: ["keymgr_sync_async_fault_cross"]
}
{
+ name: sec_cm_check
+ desc: '''
+ Verify the outcome after injecting faults to security countermeasures.
+
+ Stimulus:
+ As mentioned in `sec_cm_testplan`.
+
+ Checks:
+ - Besides checking alert and `fault_status`, issue an operation after injecting faults,
+ then ensure that `op_status` is failed and design enters `StInvalid`.
+ '''
+ milestone: V2
+ tests: ["keymgr_sec_cm"]
+ }
+ {
name: stress_all
desc: '''
- Combine above sequences in one test to run sequentially, except csr sequence and
