| commit | 60fd43f8b21c4d85651ab4bf30babce24af3a4b2 | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@google.com> | Tue Aug 11 21:54:53 2020 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Wed Aug 26 15:42:13 2020 -0700 |
| tree | 80fedae709e057daf3691912763137c1e731abf3 | |
| parent | c9af7b9259f5a8c0ba3fa70e8f457ee5976648e4 [diff] |
[dv/alert] support async alert This PR intends to solve issue #3135 To support async alert: 1). Add two clk cycle delays when alert is detected if the alert async mode is on 2). If signal int error detected, and it is the first clock cycle, ignore this error because it could potentially be a `clk_skew` 3). In alert_esc_if add async clocks (randomly generate freqs) and reset (currently tied to rst_n) Signed-off-by: Cindy Chen <chencindy@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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