[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index b07f87e..786bbbe 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -10780,6 +10780,13 @@
module_name: flash_ctrl
}
{
+ name: flash_ctrl_fatal_intg_err
+ width: 1
+ type: alert
+ async: "1"
+ module_name: flash_ctrl
+ }
+ {
name: aes_recov_ctrl_update_err
width: 1
type: alert
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 789e490..3e51530 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -20,17 +20,18 @@
assign alert_if[13].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
assign alert_if[14].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
assign alert_if[15].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[29].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index cb01a93..63196b7 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -21,6 +21,7 @@
"flash_ctrl_recov_err",
"flash_ctrl_recov_mp_err",
"flash_ctrl_recov_ecc_err",
+ "flash_ctrl_fatal_intg_err",
"aes_recov_ctrl_update_err",
"aes_fatal_fault",
"keymgr_fatal_fault_err",
@@ -37,4 +38,4 @@
"rom_ctrl_fatal"
};
-parameter uint NUM_ALERTS = 30;
+parameter uint NUM_ALERTS = 31;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index d1df40e..585c2b6 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "30",
+ default: "31",
local: "true"
},
{ name: "EscCntDw",
@@ -66,7 +66,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "30'b111111111111111110000000000000",
+ default: "31'b1111111111111111110000000000000",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 0df3e1a..64c7743 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 30;
+ parameter int NAlerts = 31;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
- parameter logic [NAlerts-1:0] AsyncOn = 30'b111111111111111110000000000000;
+ parameter logic [NAlerts-1:0] AsyncOn = 31'b1111111111111111110000000000000;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -454,14 +454,14 @@
// Register -> HW type
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [944:941]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [940:937]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [936:929]
- alert_handler_reg2hw_regwen_reg_t regwen; // [928:928]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [927:904]
- alert_handler_reg2hw_alert_en_mreg_t [29:0] alert_en; // [903:874]
- alert_handler_reg2hw_alert_class_mreg_t [29:0] alert_class; // [873:814]
- alert_handler_reg2hw_alert_cause_mreg_t [29:0] alert_cause; // [813:784]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [948:945]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [944:941]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [940:933]
+ alert_handler_reg2hw_regwen_reg_t regwen; // [932:932]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [931:908]
+ alert_handler_reg2hw_alert_en_mreg_t [30:0] alert_en; // [907:877]
+ alert_handler_reg2hw_alert_class_mreg_t [30:0] alert_class; // [876:815]
+ alert_handler_reg2hw_alert_cause_mreg_t [30:0] alert_cause; // [814:784]
alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
@@ -501,8 +501,8 @@
// HW -> register type
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [287:280]
- alert_handler_hw2reg_alert_cause_mreg_t [29:0] alert_cause; // [279:220]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [289:282]
+ alert_handler_hw2reg_alert_cause_mreg_t [30:0] alert_cause; // [281:220]
alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [219:212]
alert_handler_hw2reg_classa_regwen_reg_t classa_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index c24c559..27ebb77 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -232,6 +232,9 @@
logic alert_en_en_a_29_qs;
logic alert_en_en_a_29_wd;
logic alert_en_en_a_29_we;
+ logic alert_en_en_a_30_qs;
+ logic alert_en_en_a_30_wd;
+ logic alert_en_en_a_30_we;
logic [1:0] alert_class_0_class_a_0_qs;
logic [1:0] alert_class_0_class_a_0_wd;
logic alert_class_0_class_a_0_we;
@@ -322,6 +325,9 @@
logic [1:0] alert_class_1_class_a_29_qs;
logic [1:0] alert_class_1_class_a_29_wd;
logic alert_class_1_class_a_29_we;
+ logic [1:0] alert_class_1_class_a_30_qs;
+ logic [1:0] alert_class_1_class_a_30_wd;
+ logic alert_class_1_class_a_30_we;
logic alert_cause_a_0_qs;
logic alert_cause_a_0_wd;
logic alert_cause_a_0_we;
@@ -412,6 +418,9 @@
logic alert_cause_a_29_qs;
logic alert_cause_a_29_wd;
logic alert_cause_a_29_we;
+ logic alert_cause_a_30_qs;
+ logic alert_cause_a_30_wd;
+ logic alert_cause_a_30_we;
logic loc_alert_en_en_la_0_qs;
logic loc_alert_en_en_la_0_wd;
logic loc_alert_en_en_la_0_we;
@@ -1798,6 +1807,32 @@
);
+ // F[en_a_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a_30 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a_30_we & regwen_qs),
+ .wd (alert_en_en_a_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[30].q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a_30_qs)
+ );
+
+
// Subregister 0 of Multireg alert_class
@@ -2586,6 +2621,32 @@
);
+ // F[class_a_30]: 29:28
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_1_class_a_30 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_1_class_a_30_we & regwen_qs),
+ .wd (alert_class_1_class_a_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[30].q ),
+
+ // to register interface (read)
+ .qs (alert_class_1_class_a_30_qs)
+ );
+
+
// Subregister 0 of Multireg alert_cause
@@ -3371,6 +3432,32 @@
);
+ // F[a_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a_30 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a_30_we),
+ .wd (alert_cause_a_30_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[30].de),
+ .d (hw2reg.alert_cause[30].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[30].q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a_30_qs)
+ );
+
+
// Subregister 0 of Multireg loc_alert_en
@@ -6065,6 +6152,9 @@
assign alert_en_en_a_29_we = addr_hit[5] & reg_we & !reg_error;
assign alert_en_en_a_29_wd = reg_wdata[29];
+ assign alert_en_en_a_30_we = addr_hit[5] & reg_we & !reg_error;
+ assign alert_en_en_a_30_wd = reg_wdata[30];
+
assign alert_class_0_class_a_0_we = addr_hit[6] & reg_we & !reg_error;
assign alert_class_0_class_a_0_wd = reg_wdata[1:0];
@@ -6155,6 +6245,9 @@
assign alert_class_1_class_a_29_we = addr_hit[7] & reg_we & !reg_error;
assign alert_class_1_class_a_29_wd = reg_wdata[27:26];
+ assign alert_class_1_class_a_30_we = addr_hit[7] & reg_we & !reg_error;
+ assign alert_class_1_class_a_30_wd = reg_wdata[29:28];
+
assign alert_cause_a_0_we = addr_hit[8] & reg_we & !reg_error;
assign alert_cause_a_0_wd = reg_wdata[0];
@@ -6245,6 +6338,9 @@
assign alert_cause_a_29_we = addr_hit[8] & reg_we & !reg_error;
assign alert_cause_a_29_wd = reg_wdata[29];
+ assign alert_cause_a_30_we = addr_hit[8] & reg_we & !reg_error;
+ assign alert_cause_a_30_wd = reg_wdata[30];
+
assign loc_alert_en_en_la_0_we = addr_hit[9] & reg_we & !reg_error;
assign loc_alert_en_en_la_0_wd = reg_wdata[0];
@@ -6585,6 +6681,7 @@
reg_rdata_next[27] = alert_en_en_a_27_qs;
reg_rdata_next[28] = alert_en_en_a_28_qs;
reg_rdata_next[29] = alert_en_en_a_29_qs;
+ reg_rdata_next[30] = alert_en_en_a_30_qs;
end
addr_hit[6]: begin
@@ -6621,6 +6718,7 @@
reg_rdata_next[23:22] = alert_class_1_class_a_27_qs;
reg_rdata_next[25:24] = alert_class_1_class_a_28_qs;
reg_rdata_next[27:26] = alert_class_1_class_a_29_qs;
+ reg_rdata_next[29:28] = alert_class_1_class_a_30_qs;
end
addr_hit[8]: begin
@@ -6654,6 +6752,7 @@
reg_rdata_next[27] = alert_cause_a_27_qs;
reg_rdata_next[28] = alert_cause_a_28_qs;
reg_rdata_next[29] = alert_cause_a_29_qs;
+ reg_rdata_next[30] = alert_cause_a_30_qs;
end
addr_hit[9]: begin
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index ac344e3..27dd346 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -46,6 +46,9 @@
{ name: "recov_ecc_err",
desc: "recoverable flash alert for ecc error"
},
+ { name: "fatal_intg_err",
+ desc: "Fatal integrity error"
+ },
],
// Define flash_ctrl <-> flash_phy struct package
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index d342862..860ef3c 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -88,7 +88,9 @@
tlul_pkg::tl_d2h_t tl_win_d2h [2];
assign prim_tl_o = flash_i.tl_flash_p2c;
+
// Register module
+ logic intg_err;
flash_ctrl_core_reg_top u_reg_core (
.clk_i,
.rst_ni,
@@ -102,7 +104,7 @@
.reg2hw,
.hw2reg,
- .intg_err_o (),
+ .intg_err_o (intg_err),
.devmode_i (1'b1)
);
@@ -163,7 +165,9 @@
// Flash control arbitration connections to hardware interface
flash_key_t addr_key;
+ flash_key_t rand_addr_key;
flash_key_t data_key;
+ flash_key_t rand_data_key;
flash_ctrl_reg2hw_control_reg_t hw_ctrl;
logic hw_req;
logic [top_pkg::TL_AW-1:0] hw_addr;
@@ -424,6 +428,8 @@
.otp_key_rsp_i(otp_i),
.addr_key_o(addr_key),
.data_key_o(data_key),
+ .rand_addr_key_o(rand_addr_key),
+ .rand_data_key_o(rand_data_key),
// entropy interface
.edn_req_o(lfsr_seed_en),
@@ -788,6 +794,8 @@
assign flash_o.region_cfgs = region_cfgs;
assign flash_o.addr_key = addr_key;
assign flash_o.data_key = data_key;
+ assign flash_o.rand_addr_key = rand_addr_key;
+ assign flash_o.rand_data_key = rand_data_key;
assign flash_o.tl_flash_c2p = prim_tl_i;
assign flash_o.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q;
assign flash_o.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q;
@@ -796,6 +804,7 @@
assign flash_o.jtag_req.tdi = cio_tdi_i;
assign flash_o.jtag_req.trst_n = '0;
assign flash_o.ecc_multi_err_en = reg2hw.phy_err_cfg.q;
+ assign flash_o.intg_err = intg_err;
assign cio_tdo_o = flash_i.jtag_rsp.tdo;
assign cio_tdo_en_o = flash_i.jtag_rsp.tdo_oe;
assign flash_rd_err = flash_i.rd_err;
@@ -804,6 +813,7 @@
+
// Interface to pwrmgr
// flash is not idle as long as there is a stateful operation ongoing
logic flash_idle_d;
@@ -836,19 +846,26 @@
logic recov_ecc_err;
assign recov_ecc_err = |flash_i.ecc_single_err | |flash_i.ecc_multi_err;
- assign alert_srcs = { recov_ecc_err,
+ logic fatal_intg_err;
+ assign fatal_intg_err = flash_i.intg_err | intg_err;
+
+ assign alert_srcs = { fatal_intg_err,
+ recov_ecc_err,
recov_mp_err,
recov_err
};
- assign alert_tests = { reg2hw.alert_test.recov_ecc_err.q & reg2hw.alert_test.recov_ecc_err.qe,
+ assign alert_tests = { reg2hw.alert_test.fatal_intg_err.q & reg2hw.alert_test.fatal_intg_err.qe,
+ reg2hw.alert_test.recov_ecc_err.q & reg2hw.alert_test.recov_ecc_err.qe,
reg2hw.alert_test.recov_mp_err.q & reg2hw.alert_test.recov_mp_err.qe,
reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
};
+ localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0, 1'b0, 1'b0};
for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
prim_alert_sender #(
- .AsyncOn(AlertAsyncOn[i])
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(IsFatal[i])
) u_alert_sender (
.clk_i,
.rst_ni,
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
index 3eebec7..1b7eb76 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
@@ -211,6 +211,8 @@
logic alert_test_recov_mp_err_we;
logic alert_test_recov_ecc_err_wd;
logic alert_test_recov_ecc_err_we;
+ logic alert_test_fatal_intg_err_wd;
+ logic alert_test_fatal_intg_err_we;
logic ctrl_regwen_qs;
logic ctrl_regwen_re;
logic control_start_qs;
@@ -1673,6 +1675,21 @@
);
+ // F[fatal_intg_err]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_intg_err (
+ .re (1'b0),
+ .we (alert_test_fatal_intg_err_we),
+ .wd (alert_test_fatal_intg_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.fatal_intg_err.qe),
+ .q (reg2hw.alert_test.fatal_intg_err.q ),
+ .qs ()
+ );
+
+
// R[ctrl_regwen]: V(True)
prim_subreg_ext #(
@@ -11074,6 +11091,9 @@
assign alert_test_recov_ecc_err_we = addr_hit[3] & reg_we & !reg_error;
assign alert_test_recov_ecc_err_wd = reg_wdata[2];
+ assign alert_test_fatal_intg_err_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_test_fatal_intg_err_wd = reg_wdata[3];
+
assign ctrl_regwen_re = addr_hit[4] & reg_re & !reg_error;
assign control_start_we = addr_hit[5] & reg_we & !reg_error;
@@ -12101,6 +12121,7 @@
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
end
addr_hit[4]: begin
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
index e2540b3..0f6d22b 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
@@ -305,10 +305,13 @@
mp_region_cfg_t [MpRegions:0] region_cfgs;
logic [KeyWidth-1:0] addr_key;
logic [KeyWidth-1:0] data_key;
+ logic [KeyWidth-1:0] rand_addr_key;
+ logic [KeyWidth-1:0] rand_data_key;
tlul_pkg::tl_h2d_t tl_flash_c2p;
logic alert_trig;
logic alert_ack;
jtag_pkg::jtag_req_t jtag_req;
+ logic intg_err;
} flash_req_t;
// default value of flash_req_t (for dangling ports)
@@ -333,10 +336,13 @@
region_cfgs: '0,
addr_key: RndCnstAddrKeyDefault,
data_key: RndCnstDataKeyDefault,
+ rand_addr_key: '0,
+ rand_data_key: '0,
tl_flash_c2p: '0,
alert_trig: 1'b0,
alert_ack: 1'b0,
- jtag_req: '0
+ jtag_req: '0,
+ intg_err: '0
};
// memory to flash controller
@@ -356,6 +362,7 @@
logic [NumBanks-1:0] ecc_multi_err;
logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
jtag_pkg::jtag_rsp_t jtag_rsp;
+ logic intg_err;
} flash_rsp_t;
// default value of flash_rsp_t (for dangling ports)
@@ -374,7 +381,8 @@
ecc_single_err: '0,
ecc_multi_err: '0,
ecc_addr: '0,
- jtag_rsp: '0
+ jtag_rsp: '0,
+ intg_err: '0
};
// RMA entries
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
index 143387e..7a24434 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -20,7 +20,7 @@
parameter int BytesPerWord = 8;
parameter int BytesPerPage = 2048;
parameter int BytesPerBank = 524288;
- parameter int NumAlerts = 3;
+ parameter int NumAlerts = 4;
// Address widths within the block
parameter int CoreAw = 9;
@@ -112,6 +112,10 @@
logic q;
logic qe;
} recov_ecc_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_intg_err;
} flash_ctrl_reg2hw_alert_test_reg_t;
typedef struct packed {
@@ -570,10 +574,10 @@
// Register -> HW type for core interface
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [554:549]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [548:543]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [542:531]
- flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [530:525]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [556:551]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [550:545]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [544:533]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [532:525]
flash_ctrl_reg2hw_control_reg_t control; // [524:505]
flash_ctrl_reg2hw_addr_reg_t addr; // [504:473]
flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [472:471]
@@ -723,10 +727,11 @@
parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_INTR_TEST_ERR_RESVAL = 1'h 0;
- parameter logic [2:0] FLASH_CTRL_ALERT_TEST_RESVAL = 3'h 0;
+ parameter logic [3:0] FLASH_CTRL_ALERT_TEST_RESVAL = 4'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_MP_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ECC_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_INTG_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index dde6dde..2cff1ba 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -945,6 +945,7 @@
logic flash_host_rderr;
logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata;
logic [flash_ctrl_pkg::BusAddrW-1:0] flash_host_addr;
+ logic flash_host_intg_err;
tlul_adapter_sram #(
.SramAw(flash_ctrl_pkg::BusAddrW),
@@ -969,7 +970,7 @@
.addr_o (flash_host_addr),
.wdata_o (),
.wmask_o (),
- .intg_error_o(), // TODO: connect to flash controller and flash scramble later
+ .intg_error_o(flash_host_intg_err),
.rdata_i (flash_host_rdata),
.rvalid_i (flash_host_req_done),
.rerror_i ({flash_host_rderr,1'b0})
@@ -979,6 +980,7 @@
.clk_i (clkmgr_aon_clocks.clk_main_infra),
.rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
.host_req_i (flash_host_req),
+ .host_intg_err_i (flash_host_intg_err),
.host_req_type_i (flash_host_req_type),
.host_addr_i (flash_host_addr),
.host_req_rdy_o (flash_host_req_rdy),
@@ -1868,7 +1870,7 @@
);
flash_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:13]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:13]),
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
.RndCnstDataKey(RndCnstFlashCtrlDataKey),
.RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -1894,8 +1896,9 @@
// [13]: recov_err
// [14]: recov_mp_err
// [15]: recov_ecc_err
- .alert_tx_o ( alert_tx[15:13] ),
- .alert_rx_i ( alert_rx[15:13] ),
+ // [16]: fatal_intg_err
+ .alert_tx_o ( alert_tx[16:13] ),
+ .alert_rx_i ( alert_rx[16:13] ),
// Inter-module signals
.flash_o(flash_ctrl_flash_req),
@@ -1942,7 +1945,7 @@
);
aes #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[17:16]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:17]),
.AES192Enable(1'b1),
.Masking(AesMasking),
.SBoxImpl(AesSBoxImpl),
@@ -1955,10 +1958,10 @@
.RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
.RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
) u_aes (
- // [16]: recov_ctrl_update_err
- // [17]: fatal_fault
- .alert_tx_o ( alert_tx[17:16] ),
- .alert_rx_i ( alert_rx[17:16] ),
+ // [17]: recov_ctrl_update_err
+ // [18]: fatal_fault
+ .alert_tx_o ( alert_tx[18:17] ),
+ .alert_rx_i ( alert_rx[18:17] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[0]),
@@ -2020,7 +2023,7 @@
);
keymgr #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:18]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:19]),
.RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
.RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
.RndCnstRandPerm(RndCnstKeymgrRandPerm),
@@ -2038,10 +2041,10 @@
// Interrupt
.intr_op_done_o (intr_keymgr_op_done),
- // [18]: fatal_fault_err
- // [19]: recov_operation_err
- .alert_tx_o ( alert_tx[19:18] ),
- .alert_rx_i ( alert_rx[19:18] ),
+ // [19]: fatal_fault_err
+ // [20]: recov_operation_err
+ .alert_tx_o ( alert_tx[20:19] ),
+ .alert_rx_i ( alert_rx[20:19] ),
// Inter-module signals
.edn_o(edn0_edn_req[0]),
@@ -2067,7 +2070,7 @@
);
csrng #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]),
.SBoxImpl(CsrngSBoxImpl)
) u_csrng (
@@ -2076,9 +2079,9 @@
.intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
.intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
.intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
- // [20]: fatal_alert
- .alert_tx_o ( alert_tx[20:20] ),
- .alert_rx_i ( alert_rx[20:20] ),
+ // [21]: fatal_alert
+ .alert_tx_o ( alert_tx[21:21] ),
+ .alert_rx_i ( alert_rx[21:21] ),
// Inter-module signals
.csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2098,17 +2101,17 @@
);
entropy_src #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:21])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:22])
) u_entropy_src (
// Interrupt
.intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid),
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
.intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [21]: recov_alert
- // [22]: fatal_alert
- .alert_tx_o ( alert_tx[22:21] ),
- .alert_rx_i ( alert_rx[22:21] ),
+ // [22]: recov_alert
+ // [23]: fatal_alert
+ .alert_tx_o ( alert_tx[23:22] ),
+ .alert_rx_i ( alert_rx[23:22] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2130,15 +2133,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:23])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:24])
) u_edn0 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
- // [23]: fatal_alert
- .alert_tx_o ( alert_tx[23:23] ),
- .alert_rx_i ( alert_rx[23:23] ),
+ // [24]: fatal_alert
+ .alert_tx_o ( alert_tx[24:24] ),
+ .alert_rx_i ( alert_rx[24:24] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2154,15 +2157,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:24])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:25])
) u_edn1 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
- // [24]: fatal_alert
- .alert_tx_o ( alert_tx[24:24] ),
- .alert_rx_i ( alert_rx[24:24] ),
+ // [25]: fatal_alert
+ .alert_tx_o ( alert_tx[25:25] ),
+ .alert_rx_i ( alert_rx[25:25] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2178,16 +2181,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:26]),
.RndCnstSramKey(RndCnstSramCtrlMainSramKey),
.RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm),
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [25]: fatal_intg_error
- // [26]: fatal_parity_error
- .alert_tx_o ( alert_tx[26:25] ),
- .alert_rx_i ( alert_rx[26:25] ),
+ // [26]: fatal_intg_error
+ // [27]: fatal_parity_error
+ .alert_tx_o ( alert_tx[27:26] ),
+ .alert_rx_i ( alert_rx[27:26] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2212,16 +2215,16 @@
);
otbn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:27]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]),
.RegFile(OtbnRegFile)
) u_otbn (
// Interrupt
.intr_done_o (intr_otbn_done),
- // [27]: fatal
- // [28]: recov
- .alert_tx_o ( alert_tx[28:27] ),
- .alert_rx_i ( alert_rx[28:27] ),
+ // [28]: fatal
+ // [29]: recov
+ .alert_tx_o ( alert_tx[29:28] ),
+ .alert_rx_i ( alert_rx[29:28] ),
// Inter-module signals
.edn_rnd_o(edn1_edn_req[0]),
@@ -2241,12 +2244,12 @@
);
rom_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]),
.BootRomInitFile(RomCtrlBootRomInitFile)
) u_rom_ctrl (
- // [29]: fatal
- .alert_tx_o ( alert_tx[29:29] ),
- .alert_rx_i ( alert_rx[29:29] ),
+ // [30]: fatal
+ .alert_tx_o ( alert_tx[30:30] ),
+ .alert_rx_i ( alert_rx[30:30] ),
// Inter-module signals
.rom_cfg_i(ast_rom_cfg),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index d5d71c4..f58a052 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -201,7 +201,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[30] = {
+ top_earlgrey_alert_for_peripheral[31] = {
[kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
[kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
@@ -218,6 +218,7 @@
[kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdFlashCtrlRecovMpErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdFlashCtrlRecovEccErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
+ [kTopEarlgreyAlertIdFlashCtrlFatalIntgErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdKeymgrFatalFaultErr] = kTopEarlgreyAlertPeripheralKeymgr,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 4cd7720..f700017 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1109,21 +1109,22 @@
kTopEarlgreyAlertIdFlashCtrlRecovErr = 13, /**< flash_ctrl_recov_err */
kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 14, /**< flash_ctrl_recov_mp_err */
kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 15, /**< flash_ctrl_recov_ecc_err */
- kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 16, /**< aes_recov_ctrl_update_err */
- kTopEarlgreyAlertIdAesFatalFault = 17, /**< aes_fatal_fault */
- kTopEarlgreyAlertIdKeymgrFatalFaultErr = 18, /**< keymgr_fatal_fault_err */
- kTopEarlgreyAlertIdKeymgrRecovOperationErr = 19, /**< keymgr_recov_operation_err */
- kTopEarlgreyAlertIdCsrngFatalAlert = 20, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdEntropySrcRecovAlert = 21, /**< entropy_src_recov_alert */
- kTopEarlgreyAlertIdEntropySrcFatalAlert = 22, /**< entropy_src_fatal_alert */
- kTopEarlgreyAlertIdEdn0FatalAlert = 23, /**< edn0_fatal_alert */
- kTopEarlgreyAlertIdEdn1FatalAlert = 24, /**< edn1_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 25, /**< sram_ctrl_main_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 26, /**< sram_ctrl_main_fatal_parity_error */
- kTopEarlgreyAlertIdOtbnFatal = 27, /**< otbn_fatal */
- kTopEarlgreyAlertIdOtbnRecov = 28, /**< otbn_recov */
- kTopEarlgreyAlertIdRomCtrlFatal = 29, /**< rom_ctrl_fatal */
- kTopEarlgreyAlertIdLast = 29, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 16, /**< flash_ctrl_fatal_intg_err */
+ kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 17, /**< aes_recov_ctrl_update_err */
+ kTopEarlgreyAlertIdAesFatalFault = 18, /**< aes_fatal_fault */
+ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 19, /**< keymgr_fatal_fault_err */
+ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 20, /**< keymgr_recov_operation_err */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 21, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 22, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 23, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdEdn0FatalAlert = 24, /**< edn0_fatal_alert */
+ kTopEarlgreyAlertIdEdn1FatalAlert = 25, /**< edn1_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 26, /**< sram_ctrl_main_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 27, /**< sram_ctrl_main_fatal_parity_error */
+ kTopEarlgreyAlertIdOtbnFatal = 28, /**< otbn_fatal */
+ kTopEarlgreyAlertIdOtbnRecov = 29, /**< otbn_recov */
+ kTopEarlgreyAlertIdRomCtrlFatal = 30, /**< rom_ctrl_fatal */
+ kTopEarlgreyAlertIdLast = 30, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1133,7 +1134,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[30];
+ top_earlgrey_alert_for_peripheral[31];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
