| commit | 5fe43c77f2fbcb836af8d79b3398e84f0c96236e | [log] [tgz] |
|---|---|---|
| author | Guillermo Maturana <maturana@google.com> | Fri Jan 28 15:03:42 2022 -0800 |
| committer | Matute <maturana@google.com> | Tue Feb 01 13:34:15 2022 -0800 |
| tree | 840b74731b66d3fea1f0768a6c267dfd5a3ac5cd | |
| parent | 0409944012596a05d679a976fa2510a5c73ad781 [diff] |
[dw/rstmgr] Add stress_all test Disable POR check on entry to some tests unless they run standalone. Disable the portions of some tests that modify sw_rst_regwen, since writes are irreversible. Remove peripheral reset checks from rstmgr_cascading_sva_if since they are checked in rstmgr_sw_rst_sva_if due to their additional dependencies. Force clk_rst_if.rst_n to the actual rst used by the hardware, since it is the source of truth. Signed-off-by: Guillermo Maturana <maturana@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).