[flash_ctrl,dv] closed source regression fix
flash_ctrl_cov_if is located under cov directory.
When such module or dv component is used in env class, it
can cause compile error in closed source test.
Remove flash_ctrl_cov_if reference from env class.
Signed-off-by: Jaedon Kim <jdonjdon@google.com>
diff --git a/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov.core b/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov.core
index d04d5e1..7a5da02 100644
--- a/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov.core
+++ b/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov.core
@@ -11,7 +11,6 @@
- lowrisc:dv:dv_utils
- lowrisc:ip:flash_ctrl
files:
- - flash_ctrl_cov_if.sv
- flash_ctrl_cov_bind.sv
file_type: systemVerilogSource
diff --git a/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv b/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv
index ee2e927..9f0c72f 100644
--- a/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv
+++ b/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv
@@ -10,7 +10,6 @@
);
module flash_ctrl_cov_bind;
- bind flash_ctrl flash_ctrl_cov_if u_flash_ctrl_cov_if (.*);
`FLASH_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en)
`FLASH_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en)
diff --git a/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_if.sv b/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_if.sv
deleted file mode 100644
index c9eb5bc..0000000
--- a/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov_if.sv
+++ /dev/null
@@ -1,25 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Implements functional coverage for FLASH_CTRL
-
-interface flash_ctrl_cov_if (
- input logic clk_i,
- input logic rst_ni
-);
-
- import uvm_pkg::*;
- import flash_ctrl_pkg::*;
- import lc_ctrl_pkg::*;
- import dv_utils_pkg::*;
- `include "dv_fcov_macros.svh"
-
- logic rd_buf_en;
- lc_tx_t rma_req;
- rma_state_e rma_state;
- logic [10:0] prog_state0;
- logic [10:0] prog_state1;
- logic [10:0] lcmgr_state;
- logic init;
-endinterface
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env.sv
index a729498..26d0905 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env.sv
@@ -30,10 +30,6 @@
)) begin
`uvm_fatal(`gfn, "failed to get flash_ctrl_vif from uvm_config_db")
end
- if (!uvm_config_db#(virtual flash_ctrl_cov_if)::get(
- this, "", "flash_ctrl_cov_vif", cfg.flash_ctrl_cov_vif)) begin
- `uvm_fatal(`gfn, "failed to get flash_ctrl_cov_vif from uvm_config_db")
- end
for (int i = 0; i < NumBanks; i++) begin
if (!uvm_config_db#(virtual flash_ctrl_mem_if)::get(
this, "", $sformatf("flash_ctrl_mem_vif[%0d]", i), cfg.flash_ctrl_mem_vif[i])) begin
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
index 2e3e33a..900a478 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
@@ -22,7 +22,6 @@
flash_phy_prim_agent_cfg m_fpp_agent_cfg;
// interface
virtual flash_ctrl_if flash_ctrl_vif;
- virtual flash_ctrl_cov_if flash_ctrl_cov_vif;
virtual clk_rst_if clk_rst_vif_flash_ctrl_eflash_reg_block;
virtual clk_rst_if clk_rst_vif_flash_ctrl_prim_reg_block;
virtual flash_ctrl_mem_if flash_ctrl_mem_vif[NumBanks];
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv
index 6c6f0dd..50d7b4e 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_if.sv
@@ -50,4 +50,12 @@
logic [flash_ctrl_pkg::NumBanks-1:0] evict_erase;
logic fatal_err;
+ // rma coverage
+ logic rd_buf_en;
+ rma_state_e rma_state;
+ logic [10:0] prog_state0;
+ logic [10:0] prog_state1;
+ logic [10:0] lcmgr_state;
+ logic init;
+
endinterface : flash_ctrl_if
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
index 529e618..22b1461 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
@@ -85,9 +85,9 @@
bit init_set = 0;
forever begin
@(negedge cfg.clk_rst_vif.clk);
- if (init_set == 0 && cfg.flash_ctrl_cov_vif.init == 1) begin
+ if (init_set == 0 && cfg.flash_ctrl_vif.init == 1) begin
init_set = 1;
- if (cfg.en_cov) cov.rma_init_cg.sample(cfg.flash_ctrl_cov_vif.rma_state);
+ if (cfg.en_cov) cov.rma_init_cg.sample(cfg.flash_ctrl_vif.rma_state);
end
end
endtask // mon_rma
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_hw_rma_reset_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_hw_rma_reset_vseq.sv
index d2b3ff8..14fd550 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_hw_rma_reset_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_hw_rma_reset_vseq.sv
@@ -56,7 +56,7 @@
reset_state_index_e reset_state_index = $urandom_range(DVStRmaPageSel, DVStRmaRdVerify);
// Assert reset during RMA state transition
`uvm_info("Test", $sformatf("Reset index: %s", reset_state_index.name), UVM_LOW)
- `DV_SPINWAIT(wait(cfg.flash_ctrl_cov_vif.rma_state == dv2rma_st(reset_state_index));,
+ `DV_SPINWAIT(wait(cfg.flash_ctrl_vif.rma_state == dv2rma_st(reset_state_index));,
$sformatf("Timed out waiting for rma_state: %s", reset_state_index.name),
state_wait_timeout_ns)
// Give more cycles for long stages
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otp_reset_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otp_reset_vseq.sv
index d0f8f9a..87ccb61 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otp_reset_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otp_reset_vseq.sv
@@ -46,7 +46,7 @@
csr_wr(.ptr(ral.init), .value(1));
`uvm_info("Test","OTP",UVM_LOW)
otp_model();
- `DV_SPINWAIT(wait(cfg.flash_ctrl_cov_vif.rd_buf_en == 1);,
+ `DV_SPINWAIT(wait(cfg.flash_ctrl_vif.rd_buf_en == 1);,
"Timed out waiting for rd_buf_en",
state_wait_timeout_ns)
`uvm_info("Test", "RMA REQUEST START", UVM_LOW)
@@ -70,7 +70,7 @@
if (reset_index == DVWaitRmaRsp) wait_time = long_wait_timeout_ns;
else wait_time = state_wait_timeout_ns;
- `DV_SPINWAIT(wait(cfg.flash_ctrl_cov_vif.lcmgr_state == dv2rtl_st(reset_index));,
+ `DV_SPINWAIT(wait(cfg.flash_ctrl_vif.lcmgr_state == dv2rtl_st(reset_index));,
$sformatf("Timed out waiting for %s", reset_index.name),
wait_time)
// Since these are single cycle state,
@@ -138,7 +138,7 @@
cfg.clk_rst_vif.wait_clks(2);
`uvm_info("Test","OTP after loop",UVM_LOW)
otp_model();
- `DV_SPINWAIT(wait(cfg.flash_ctrl_cov_vif.rd_buf_en == 1);,
+ `DV_SPINWAIT(wait(cfg.flash_ctrl_vif.rd_buf_en == 1);,
"Timed out waiting for rd_buf_en",
state_wait_timeout_ns)
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_prog_reset_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_prog_reset_vseq.sv
index 9787cdb..5b49a64 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_prog_reset_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_prog_reset_vseq.sv
@@ -69,8 +69,8 @@
string path1, path2;
reset_index_e reset_index = $urandom_range(DVStPrePack, DVStCalcEcc);
`uvm_info("Test", $sformatf("reset_idx: %s", reset_index.name), UVM_MEDIUM)
- `DV_SPINWAIT(wait(cfg.flash_ctrl_cov_vif.prog_state0 == dv2rtl_st(reset_index) ||
- cfg.flash_ctrl_cov_vif.prog_state1 == dv2rtl_st(reset_index));,
+ `DV_SPINWAIT(wait(cfg.flash_ctrl_vif.prog_state0 == dv2rtl_st(reset_index) ||
+ cfg.flash_ctrl_vif.prog_state1 == dv2rtl_st(reset_index));,
$sformatf("Timed out waiting for %s", reset_index.name),
// Use long time out.
// Some unique state does not always guarantee to reach.
@@ -87,7 +87,7 @@
csr_wr(.ptr(ral.init), .value(1));
`uvm_info("Test","OTP",UVM_LOW)
otp_model();
- `DV_SPINWAIT(wait(cfg.flash_ctrl_cov_vif.rd_buf_en == 1);,
+ `DV_SPINWAIT(wait(cfg.flash_ctrl_vif.rd_buf_en == 1);,
"Timed out waiting for rd_buf_en",
state_timeout_ns)
diff --git a/hw/ip/flash_ctrl/dv/tb/tb.sv b/hw/ip/flash_ctrl/dv/tb/tb.sv
index 4619e5c..c9d6c43 100644
--- a/hw/ip/flash_ctrl/dv/tb/tb.sv
+++ b/hw/ip/flash_ctrl/dv/tb/tb.sv
@@ -107,15 +107,14 @@
assign otp_rsp.rand_key = flash_ctrl_if.otp_rsp.rand_key;
assign otp_rsp.seed_valid = flash_ctrl_if.otp_rsp.seed_valid;
- assign dut.u_flash_ctrl_cov_if.rd_buf_en = tb.dut.u_flash_hw_if.rd_buf_en_o;
- assign dut.u_flash_ctrl_cov_if.rma_req = tb.dut.u_flash_hw_if.rma_req_i;
- assign dut.u_flash_ctrl_cov_if.rma_state = tb.dut.u_flash_hw_if.rma_state_q;
- assign dut.u_flash_ctrl_cov_if.prog_state0 =
+ assign flash_ctrl_if.rd_buf_en = tb.dut.u_flash_hw_if.rd_buf_en_o;
+ assign flash_ctrl_if.rma_state = tb.dut.u_flash_hw_if.rma_state_q;
+ assign flash_ctrl_if.prog_state0 =
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.state_q;
- assign dut.u_flash_ctrl_cov_if.prog_state1 =
+ assign flash_ctrl_if.prog_state1 =
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.state_q;
- assign dut.u_flash_ctrl_cov_if.lcmgr_state = tb.dut.u_flash_hw_if.state_q;
- assign dut.u_flash_ctrl_cov_if.init = tb.dut.u_flash_hw_if.init_i;
+ assign flash_ctrl_if.lcmgr_state = tb.dut.u_flash_hw_if.state_q;
+ assign flash_ctrl_if.init = tb.dut.u_flash_hw_if.init_i;
wire flash_test_v;
assign (pull1, pull0) flash_test_v = 1'b1;
@@ -336,8 +335,6 @@
prim_tl_if);
uvm_config_db#(virtual flash_ctrl_if)::set(null, "*.env", "flash_ctrl_vif", flash_ctrl_if);
uvm_config_db#(virtual flash_phy_prim_if)::set(null, "*.env.m_fpp_agent*", "vif", fpp_if);
- uvm_config_db#(virtual flash_ctrl_cov_if)::set(null, "*.env", "flash_ctrl_cov_vif",
- dut.u_flash_ctrl_cov_if);
$timeformat(-9, 1, " ns", 9);
run_test();
end
