| commit | 8f0feb009e547da8bde9f228403eed2f50ac8ba5 | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Wed Jan 19 01:04:13 2022 -0800 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Mon Jan 24 15:25:18 2022 -0800 |
| tree | 1506a2fed9a7fe7aaf6b2554f4c3c777c75f92ac | |
| parent | ea7d240f8537e9e8b600b8ef0859ef2e67a48fa5 [diff] |
[chip dv] Fix plic_all_irqs_test for Verilator ...and FPGA. The logging mechanism which uses UART0 in Verilator and FPGA setups messes up this test, which is meant to enable and test ALL interrupts from all peripherals in the device, including UART0. The fix is to skip testing UART0 interrupts for Verilator and FPGA. Fixes #8656. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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