commit 8191b24586d6c532134254cff175ba540f8d300c
author Rupert Swarbrick <rswarbrick@lowrisc.org> Fri Jun 05 10:32:09 2020 +0100
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Mon Jun 08 12:57:51 2020 -0700
tree d0e8e21112816d33345a00f16158ad3505f445e4
parent 95f55d551ed00d576bf126a08e87bc9962029a58

[dv] Allow a test to have "simple" timestamps

Before this patch the clock phase was always randomised so, even if
you had a clock frequency that would give you a nice period (50MHz)
and no jitter, the time stamps would still look weird.

In a test with a single clock and the default reset strategy, the
clock phase was the sum of the time before reset (dly_ps in
apply_reset) and 0-10ps chosen at random in the driving block.

This patch changes wait_for_reset so that it always waits a whole
number of clock periods, decoupling the "reset at a random time" event
from the clock phase. It then lengthens the random delay in the
driving block from 0 -> 10ps to 0 -> clk_period. This should give the
same randomness in phase as before.

However, tests which only have one clock don't really need the random
clock phase and it makes the timestamps look odd in dumped waves. This
patch adds a "sole_clock" flag which disables the random delay, so the
clock ends up exactly in phase. The flag defaults to false, so the
default behaviour is as before.

You can now get simple timestamps in a given test. To do so:

  - Constrain the frequency. Since the frequency doesn't affect a
    non-gate-level test with only one clock, we may as well pick
    something helpful.

    If your test uses dv_lib, your <block>_env_cfg class, which
    derives from dv_base_env_cfg, should gain a constraint like:

      constraint clk_freq_50_c {
        clk_freq_mhz == ClkFreq50Mhz;
      }

    This will give a clock edge every 10ns. Other enum values that
    will look OK are ClkFreq25Mhz or ClkFreq100Mhz. If you don't force
    this, you might get a 24MHz or 48MHz clock, which looks a little
    weird.

  - Set the sole_clock flag. The easiest place to do this is the
    build_phase of the environment class. If <block>_env derives from
    dv_base_env, add something like this to its build_phase function:

      cfg.clk_rst_vif.set_sole_clock();

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>