[sw] Delete all extant uses of non-_REG_OFFSET register defines
Signed-off-by: Miguel Young de la Sota <mcyoung@google.com>
diff --git a/sw/device/examples/hello_usbdev/hello_usbdev.c b/sw/device/examples/hello_usbdev/hello_usbdev.c
index 59e1512..b3713c5 100644
--- a/sw/device/examples/hello_usbdev/hello_usbdev.c
+++ b/sw/device/examples/hello_usbdev/hello_usbdev.c
@@ -187,8 +187,9 @@
CHECK(dif_gpio_write_all(&gpio, rcv_char << 8) == kDifGpioOk);
if (rcv_char == '/') {
- uint32_t usb_irq_state = REG32(USBDEV_INTR_STATE());
- uint32_t usb_stat = REG32(USBDEV_USBSTAT());
+ uint32_t usb_irq_state =
+ REG32(USBDEV_BASE_ADDR + USBDEV_INTR_STATE_REG_OFFSET);
+ uint32_t usb_stat = REG32(USBDEV_BASE_ADDR + USBDEV_USBSTAT_REG_OFFSET);
LOG_INFO("I%4x-%8x", usb_irq_state, usb_stat);
} else {
usb_simpleserial_send_byte(&simple_serial0, rcv_char);
diff --git a/sw/device/lib/aes.c b/sw/device/lib/aes.c
index 55d8dbc..1e9cc6e 100644
--- a/sw/device/lib/aes.c
+++ b/sw/device/lib/aes.c
@@ -22,8 +22,8 @@
((aes_cfg.key_len & AES_CTRL_SHADOWED_KEY_LEN_MASK)
<< AES_CTRL_SHADOWED_KEY_LEN_OFFSET) |
(aes_cfg.manual_operation << AES_CTRL_SHADOWED_MANUAL_OPERATION);
- REG32(AES_CTRL_SHADOWED(0)) = cfg_val;
- REG32(AES_CTRL_SHADOWED(0)) = cfg_val;
+ REG32(AES0_BASE_ADDR + AES_CTRL_SHADOWED_REG_OFFSET) = cfg_val;
+ REG32(AES0_BASE_ADDR + AES_CTRL_SHADOWED_REG_OFFSET) = cfg_val;
};
void aes_key_put(const void *key_share0, const void *key_share1,
@@ -40,23 +40,26 @@
// Write the used key registers.
for (int i = 0; i < num_regs_key_used; ++i) {
- REG32(AES_KEY_SHARE0_0(0) + i * sizeof(uint32_t)) =
+ REG32(AES0_BASE_ADDR + AES_KEY_SHARE0_0_REG_OFFSET + i * sizeof(uint32_t)) =
((uint32_t *)key_share0)[i];
- REG32(AES_KEY_SHARE1_0(0) + i * sizeof(uint32_t)) =
+ REG32(AES0_BASE_ADDR + AES_KEY_SHARE1_0_REG_OFFSET + i * sizeof(uint32_t)) =
((uint32_t *)key_share1)[i];
}
// Write the unused key registers (the AES unit requires all key registers to
// be written).
for (int i = num_regs_key_used; i < AES_NUM_REGS_KEY; ++i) {
- REG32(AES_KEY_SHARE0_0(0) + i * sizeof(uint32_t)) = 0x0;
- REG32(AES_KEY_SHARE1_0(0) + i * sizeof(uint32_t)) = 0x0;
+ REG32(AES0_BASE_ADDR + AES_KEY_SHARE0_0_REG_OFFSET + i * sizeof(uint32_t)) =
+ 0x0;
+ REG32(AES0_BASE_ADDR + AES_KEY_SHARE1_0_REG_OFFSET + i * sizeof(uint32_t)) =
+ 0x0;
}
}
void aes_iv_put(const void *iv) {
// Write the four initialization vector registers.
for (int i = 0; i < AES_NUM_REGS_IV; ++i) {
- REG32(AES_IV_0(0) + i * sizeof(uint32_t)) = ((uint32_t *)iv)[i];
+ REG32(AES0_BASE_ADDR + AES_IV_0_REG_OFFSET + i * sizeof(uint32_t)) =
+ ((uint32_t *)iv)[i];
}
}
@@ -72,7 +75,8 @@
void aes_data_put(const void *data) {
// Write the four input data registers.
for (int i = 0; i < AES_NUM_REGS_DATA; ++i) {
- REG32(AES_DATA_IN_0(0) + i * sizeof(uint32_t)) = ((uint32_t *)data)[i];
+ REG32(AES0_BASE_ADDR + AES_DATA_IN_0_REG_OFFSET + i * sizeof(uint32_t)) =
+ ((uint32_t *)data)[i];
}
}
@@ -88,24 +92,28 @@
void aes_data_get(void *data) {
// Read the four output data registers.
for (int i = 0; i < AES_NUM_REGS_DATA; ++i) {
- ((uint32_t *)data)[i] = REG32(AES_DATA_OUT_0(0) + i * sizeof(uint32_t));
+ ((uint32_t *)data)[i] = REG32(AES0_BASE_ADDR + AES_DATA_OUT_0_REG_OFFSET +
+ i * sizeof(uint32_t));
}
}
bool aes_data_ready(void) {
- return (REG32(AES_STATUS(0)) & (0x1u << AES_STATUS_INPUT_READY));
+ return (REG32(AES0_BASE_ADDR + AES_STATUS_REG_OFFSET) &
+ (0x1u << AES_STATUS_INPUT_READY));
}
bool aes_data_valid(void) {
- return (REG32(AES_STATUS(0)) & (0x1u << AES_STATUS_OUTPUT_VALID));
+ return (REG32(AES0_BASE_ADDR + AES_STATUS_REG_OFFSET) &
+ (0x1u << AES_STATUS_OUTPUT_VALID));
}
bool aes_idle(void) {
- return (REG32(AES_STATUS(0)) & (0x1u << AES_STATUS_IDLE));
+ return (REG32(AES0_BASE_ADDR + AES_STATUS_REG_OFFSET) &
+ (0x1u << AES_STATUS_IDLE));
}
void aes_manual_trigger(void) {
- REG32(AES_TRIGGER(0)) = 0x1u << AES_TRIGGER_START;
+ REG32(AES0_BASE_ADDR + AES_TRIGGER_REG_OFFSET) = 0x1u << AES_TRIGGER_START;
}
void aes_clear(void) {
@@ -115,14 +123,14 @@
// Disable autostart
uint32_t cfg_val = 0x1u << AES_CTRL_SHADOWED_MANUAL_OPERATION;
- REG32(AES_CTRL_SHADOWED(0)) = cfg_val;
- REG32(AES_CTRL_SHADOWED(0)) = cfg_val;
+ REG32(AES0_BASE_ADDR + AES_CTRL_SHADOWED_REG_OFFSET) = cfg_val;
+ REG32(AES0_BASE_ADDR + AES_CTRL_SHADOWED_REG_OFFSET) = cfg_val;
// Clear internal key and output registers
- REG32(AES_TRIGGER(0)) = (0x1u << AES_TRIGGER_KEY_CLEAR) |
- (0x1u << AES_TRIGGER_IV_CLEAR) |
- (0x1u << AES_TRIGGER_DATA_IN_CLEAR) |
- (0x1u << AES_TRIGGER_DATA_OUT_CLEAR);
+ REG32(AES0_BASE_ADDR + AES_TRIGGER_REG_OFFSET) =
+ (0x1u << AES_TRIGGER_KEY_CLEAR) | (0x1u << AES_TRIGGER_IV_CLEAR) |
+ (0x1u << AES_TRIGGER_DATA_IN_CLEAR) |
+ (0x1u << AES_TRIGGER_DATA_OUT_CLEAR);
// Wait for output not valid, and input ready
while (!(!aes_data_valid() && aes_data_ready())) {
diff --git a/sw/device/lib/flash_ctrl.c b/sw/device/lib/flash_ctrl.c
index 1235a1f..cbe623b 100644
--- a/sw/device/lib/flash_ctrl.c
+++ b/sw/device/lib/flash_ctrl.c
@@ -26,23 +26,24 @@
/* Wait for flash command to complete and set ACK in controller */
static inline void wait_done_and_ack(void) {
- while ((REG32(FLASH_CTRL_OP_STATUS(0)) & (1 << FLASH_CTRL_OP_STATUS_DONE)) ==
- 0) {
+ while ((REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_OP_STATUS_REG_OFFSET) &
+ (1 << FLASH_CTRL_OP_STATUS_DONE)) == 0) {
}
- REG32(FLASH_CTRL_OP_STATUS(0)) = 0;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_OP_STATUS_REG_OFFSET) = 0;
}
void flash_init_block(void) {
- while ((REG32(FLASH_CTRL_STATUS(0)) & (1 << FLASH_CTRL_STATUS_INIT_WIP)) >
- 0) {
+ while ((REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_STATUS_REG_OFFSET) &
+ (1 << FLASH_CTRL_STATUS_INIT_WIP)) > 0) {
}
}
/* Return status error and clear internal status register */
static int get_clr_err(void) {
uint32_t err_status =
- REG32(FLASH_CTRL_INTR_STATE(0)) & (0x1 << FLASH_CTRL_INTR_STATE_OP_ERROR);
- REG32(FLASH_CTRL_INTR_STATE(0)) = err_status;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_INTR_STATE_REG_OFFSET) &
+ (0x1 << FLASH_CTRL_INTR_STATE_OP_ERROR);
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_INTR_STATE_REG_OFFSET) = err_status;
return err_status;
}
@@ -71,10 +72,10 @@
flash_cfg_bank_erase(idx, /*erase_en=*/true);
// TODO: Add timeout conditions and add error codes.
- REG32(FLASH_CTRL_ADDR(0)) = (idx == FLASH_BANK_0)
- ? FLASH_MEM_BASE_ADDR
- : (FLASH_MEM_BASE_ADDR + FLASH_BANK_SZ);
- REG32(FLASH_CTRL_CONTROL(0)) =
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_ADDR_REG_OFFSET) =
+ (idx == FLASH_BANK_0) ? FLASH_MEM_BASE_ADDR
+ : (FLASH_MEM_BASE_ADDR + FLASH_BANK_SZ);
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_CONTROL_REG_OFFSET) =
(FLASH_ERASE << FLASH_CTRL_CONTROL_OP_OFFSET |
FLASH_BANK_ERASE << FLASH_CTRL_CONTROL_ERASE_SEL |
0x1 << FLASH_CTRL_CONTROL_START);
@@ -86,12 +87,12 @@
}
int flash_page_erase(uint32_t addr, part_type_t part) {
- REG32(FLASH_CTRL_ADDR(0)) = addr;
- REG32(FLASH_CTRL_CONTROL(0)) = FLASH_ERASE << FLASH_CTRL_CONTROL_OP_OFFSET |
- FLASH_PAGE_ERASE
- << FLASH_CTRL_CONTROL_ERASE_SEL |
- part << FLASH_CTRL_CONTROL_PARTITION_SEL |
- 0x1 << FLASH_CTRL_CONTROL_START;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_ADDR_REG_OFFSET) = addr;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_CONTROL_REG_OFFSET) =
+ FLASH_ERASE << FLASH_CTRL_CONTROL_OP_OFFSET |
+ FLASH_PAGE_ERASE << FLASH_CTRL_CONTROL_ERASE_SEL |
+ part << FLASH_CTRL_CONTROL_PARTITION_SEL |
+ 0x1 << FLASH_CTRL_CONTROL_START;
wait_done_and_ack();
return get_clr_err();
}
@@ -100,13 +101,14 @@
const uint32_t *data, uint32_t size) {
// TODO: Do we need to select bank as part of the write?
// TODO: Update with address alignment requirements.
- REG32(FLASH_CTRL_ADDR(0)) = addr;
- REG32(FLASH_CTRL_CONTROL(0)) = (FLASH_PROG << FLASH_CTRL_CONTROL_OP_OFFSET |
- part << FLASH_CTRL_CONTROL_PARTITION_SEL |
- (size - 1) << FLASH_CTRL_CONTROL_NUM_OFFSET |
- 0x1 << FLASH_CTRL_CONTROL_START);
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_ADDR_REG_OFFSET) = addr;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_CONTROL_REG_OFFSET) =
+ (FLASH_PROG << FLASH_CTRL_CONTROL_OP_OFFSET |
+ part << FLASH_CTRL_CONTROL_PARTITION_SEL |
+ (size - 1) << FLASH_CTRL_CONTROL_NUM_OFFSET |
+ 0x1 << FLASH_CTRL_CONTROL_START);
for (int i = 0; i < size; ++i) {
- REG32(FLASH_CTRL_PROG_FIFO(0)) = data[i];
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_PROG_FIFO_REG_OFFSET) = data[i];
}
wait_done_and_ack();
return get_clr_err();
@@ -119,15 +121,17 @@
}
int flash_read(uint32_t addr, part_type_t part, uint32_t size, uint32_t *data) {
- REG32(FLASH_CTRL_ADDR(0)) = addr;
- REG32(FLASH_CTRL_CONTROL(0)) = FLASH_READ << FLASH_CTRL_CONTROL_OP_OFFSET |
- part << FLASH_CTRL_CONTROL_PARTITION_SEL |
- (size - 1) << FLASH_CTRL_CONTROL_NUM_OFFSET |
- 0x1 << FLASH_CTRL_CONTROL_START;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_ADDR_REG_OFFSET) = addr;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_CONTROL_REG_OFFSET) =
+ FLASH_READ << FLASH_CTRL_CONTROL_OP_OFFSET |
+ part << FLASH_CTRL_CONTROL_PARTITION_SEL |
+ (size - 1) << FLASH_CTRL_CONTROL_NUM_OFFSET |
+ 0x1 << FLASH_CTRL_CONTROL_START;
for (uint32_t i = 0; i < size;) {
- if (((REG32(FLASH_CTRL_STATUS(0)) >> FLASH_CTRL_STATUS_RD_EMPTY) & 0x1) ==
- 0) {
- *data++ = REG32(FLASH_CTRL_RD_FIFO(0));
+ if (((REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_STATUS_REG_OFFSET) >>
+ FLASH_CTRL_STATUS_RD_EMPTY) &
+ 0x1) == 0) {
+ *data++ = REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_RD_FIFO_REG_OFFSET);
i++;
}
}
@@ -136,13 +140,17 @@
}
void flash_cfg_bank_erase(bank_index_t bank, bool erase_en) {
- REG32(FLASH_CTRL_MP_BANK_CFG(0)) =
- (erase_en) ? SETBIT(REG32(FLASH_CTRL_MP_BANK_CFG(0)), bank)
- : CLRBIT(REG32(FLASH_CTRL_MP_BANK_CFG(0)), bank);
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_MP_BANK_CFG_REG_OFFSET) =
+ (erase_en) ? SETBIT(REG32(FLASH_CTRL0_BASE_ADDR +
+ FLASH_CTRL_MP_BANK_CFG_REG_OFFSET),
+ bank)
+ : CLRBIT(REG32(FLASH_CTRL0_BASE_ADDR +
+ FLASH_CTRL_MP_BANK_CFG_REG_OFFSET),
+ bank);
}
void flash_default_region_access(bool rd_en, bool prog_en, bool erase_en) {
- REG32(FLASH_CTRL_DEFAULT_REGION(0)) =
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_DEFAULT_REGION_REG_OFFSET) =
rd_en << FLASH_CTRL_DEFAULT_REGION_RD_EN |
prog_en << FLASH_CTRL_DEFAULT_REGION_PROG_EN |
erase_en << FLASH_CTRL_DEFAULT_REGION_ERASE_EN;
@@ -153,7 +161,8 @@
bank_index_t bank_sel;
if (region_cfg->part == kDataPartition) {
- REG32(FLASH_CTRL_MP_REGION_CFG_0(0) + region_cfg->num * 4) =
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_MP_REGION_CFG_0_REG_OFFSET +
+ region_cfg->num * 4) =
region_cfg->base << FLASH_CTRL_MP_REGION_CFG_0_BASE_0_OFFSET |
region_cfg->size << FLASH_CTRL_MP_REGION_CFG_0_SIZE_0_OFFSET |
region_cfg->rd_en << FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0 |
@@ -172,17 +181,21 @@
bank_sel = region_cfg->base / FLASH_PAGES_PER_BANK;
if (bank_sel == FLASH_BANK_0) {
- REG32(FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0(0) + region_cfg->num * 4) =
- reg_value;
+ REG32(FLASH_CTRL0_BASE_ADDR +
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_REG_OFFSET +
+ region_cfg->num * 4) = reg_value;
} else {
- REG32(FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0(0) + region_cfg->num * 4) =
- reg_value;
+ REG32(FLASH_CTRL0_BASE_ADDR +
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_REG_OFFSET +
+ region_cfg->num * 4) = reg_value;
}
}
}
void flash_write_scratch_reg(uint32_t value) {
- REG32(FLASH_CTRL_SCRATCH(0)) = value;
+ REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_SCRATCH_REG_OFFSET) = value;
}
-uint32_t flash_read_scratch_reg(void) { return REG32(FLASH_CTRL_SCRATCH(0)); }
+uint32_t flash_read_scratch_reg(void) {
+ return REG32(FLASH_CTRL0_BASE_ADDR + FLASH_CTRL_SCRATCH_REG_OFFSET);
+}
diff --git a/sw/device/lib/hmac.c b/sw/device/lib/hmac.c
index 0647a90..082e127 100644
--- a/sw/device/lib/hmac.c
+++ b/sw/device/lib/hmac.c
@@ -14,17 +14,19 @@
#define REG32(add) *((volatile uint32_t *)(add))
void hmac_init(hmac_cfg_t hmac_cfg) {
- REG32(HMAC_CFG(0)) = hmac_cfg.input_endian_swap << HMAC_CFG_ENDIAN_SWAP |
- 1 << hmac_cfg.mode |
- hmac_cfg.digest_endian_swap << HMAC_CFG_DIGEST_SWAP;
+ REG32(HMAC0_BASE_ADDR + HMAC_CFG_REG_OFFSET) =
+ hmac_cfg.input_endian_swap << HMAC_CFG_ENDIAN_SWAP | 1 << hmac_cfg.mode |
+ hmac_cfg.digest_endian_swap << HMAC_CFG_DIGEST_SWAP;
for (int i = 0; i < 8; i++) {
- REG32(HMAC_KEY_0(0) + i * sizeof(uint32_t)) = hmac_cfg.keys[i];
+ REG32(HMAC0_BASE_ADDR + HMAC_KEY_0_REG_OFFSET + i * sizeof(uint32_t)) =
+ hmac_cfg.keys[i];
}
- REG32(HMAC_CMD(0)) = 1 << HMAC_CMD_HASH_START;
+ REG32(HMAC0_BASE_ADDR + HMAC_CMD_REG_OFFSET) = 1 << HMAC_CMD_HASH_START;
};
static int hmac_fifo_depth(void) {
- return (REG32(HMAC_STATUS(0)) >> HMAC_STATUS_FIFO_DEPTH_OFFSET) &
+ return (REG32(HMAC0_BASE_ADDR + HMAC_STATUS_REG_OFFSET) >>
+ HMAC_STATUS_FIFO_DEPTH_OFFSET) &
HMAC_STATUS_FIFO_DEPTH_MASK;
}
@@ -44,34 +46,38 @@
}
// write a whole group
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
words_remaining -= HMAC_FIFO_GROUP_SIZE;
} else {
- REG32(HMAC_MSG_FIFO(0)) = *wp++;
+ REG32(HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *wp++;
words_remaining--;
};
}
const uint8_t *bp = (const uint8_t *)wp;
for (; bytes_left_over > 0; --bytes_left_over) {
- *((volatile uint8_t *)HMAC_MSG_FIFO(0)) = *bp++;
+ *((volatile uint8_t *)HMAC0_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET) = *bp++;
}
}
void hmac_done(uint32_t *digest) {
- REG32(HMAC_CMD(0)) = 1 << HMAC_CMD_HASH_PROCESS;
- while (!((REG32(HMAC_INTR_STATE(0)) >> HMAC_INTR_STATE_HMAC_DONE) & 0x1)) {
+ REG32(HMAC0_BASE_ADDR + HMAC_CMD_REG_OFFSET) = 1 << HMAC_CMD_HASH_PROCESS;
+ while (!((REG32(HMAC0_BASE_ADDR + HMAC_INTR_STATE_REG_OFFSET) >>
+ HMAC_INTR_STATE_HMAC_DONE) &
+ 0x1)) {
}
- REG32(HMAC_INTR_STATE(0)) = 1 << HMAC_INTR_STATE_HMAC_DONE;
+ REG32(HMAC0_BASE_ADDR + HMAC_INTR_STATE_REG_OFFSET) =
+ 1 << HMAC_INTR_STATE_HMAC_DONE;
for (uint32_t i = 0; i < 8; i++) {
- *digest++ = REG32(HMAC_DIGEST_0(0) + i * sizeof(uintptr_t));
+ *digest++ = REG32(HMAC0_BASE_ADDR + HMAC_DIGEST_0_REG_OFFSET +
+ i * sizeof(uintptr_t));
}
}
diff --git a/sw/device/lib/pinmux.c b/sw/device/lib/pinmux.c
index aacf5ad..d186236 100644
--- a/sw/device/lib/pinmux.c
+++ b/sw/device/lib/pinmux.c
@@ -31,14 +31,14 @@
void pinmux_init(void) {
// input: assign MIO0..MIO31 to GPIO0..GPIO31
- init_pinmux_reg(PINMUX_PERIPH_INSEL_0(0), PINMUX_PERIPH_INSEL_0_IN_1_OFFSET,
- 32 / PINMUX_PERIPH_INSEL_0_IN_1_OFFSET,
- PINMUX_PERIPH_INSEL_0_IN_0_MASK,
- PINMUX_PERIPH_INSEL_IDX_OFFSET);
+ init_pinmux_reg(
+ PINMUX0_BASE_ADDR + PINMUX_PERIPH_INSEL_0_REG_OFFSET,
+ PINMUX_PERIPH_INSEL_0_IN_1_OFFSET, 32 / PINMUX_PERIPH_INSEL_0_IN_1_OFFSET,
+ PINMUX_PERIPH_INSEL_0_IN_0_MASK, PINMUX_PERIPH_INSEL_IDX_OFFSET);
// output: assign GPIO0..GPIO31 to MIO0..MIO31
- init_pinmux_reg(PINMUX_MIO_OUTSEL_0(0), PINMUX_MIO_OUTSEL_0_OUT_1_OFFSET,
- 32 / PINMUX_MIO_OUTSEL_0_OUT_1_OFFSET,
- PINMUX_MIO_OUTSEL_0_OUT_0_MASK,
- PINMUX_PERIPH_OUTSEL_IDX_OFFSET);
+ init_pinmux_reg(
+ PINMUX0_BASE_ADDR + PINMUX_MIO_OUTSEL_0_REG_OFFSET,
+ PINMUX_MIO_OUTSEL_0_OUT_1_OFFSET, 32 / PINMUX_MIO_OUTSEL_0_OUT_1_OFFSET,
+ PINMUX_MIO_OUTSEL_0_OUT_0_MASK, PINMUX_PERIPH_OUTSEL_IDX_OFFSET);
}
diff --git a/sw/device/lib/usbdev.c b/sw/device/lib/usbdev.c
index 0341644..ba46e48 100644
--- a/sw/device/lib/usbdev.c
+++ b/sw/device/lib/usbdev.c
@@ -44,7 +44,8 @@
}
uint32_t *usbdev_buf_idtoaddr(usbdev_ctx_t *ctx, usbbufid_t buf) {
- return (uint32_t *)(USBDEV_BUFFER() + (buf * BUF_LENGTH));
+ return (uint32_t *)(USBDEV_BASE_ADDR + USBDEV_BUFFER_REG_OFFSET +
+ (buf * BUF_LENGTH));
}
void usbdev_buf_copyto_byid(usbdev_ctx_t *ctx, usbbufid_t buf, const void *from,
@@ -66,19 +67,21 @@
// Supply as many buffers to the receive available fifo as possible
inline static void fill_av_fifo(usbdev_ctx_t *ctx) {
- while (!(REG32(USBDEV_USBSTAT()) & (1 << USBDEV_USBSTAT_AV_FULL))) {
+ while (!(REG32(USBDEV_BASE_ADDR + USBDEV_USBSTAT_REG_OFFSET) &
+ (1 << USBDEV_USBSTAT_AV_FULL))) {
usbbufid_t buf = usbdev_buf_allocate_byid(ctx);
if (buf < 0) {
// no more free buffers, can't fill AV FIFO
break;
}
- REG32(USBDEV_AVBUFFER()) = buf;
+ REG32(USBDEV_BASE_ADDR + USBDEV_AVBUFFER_REG_OFFSET) = buf;
}
}
void usbdev_sendbuf_byid(usbdev_ctx_t *ctx, usbbufid_t buf, size_t size,
int endpoint) {
- uint32_t configin = USBDEV_CONFIGIN_0() + (4 * endpoint);
+ uint32_t configin =
+ USBDEV_BASE_ADDR + USBDEV_CONFIGIN_0_REG_OFFSET + (4 * endpoint);
if ((endpoint >= NUM_ENDPOINTS) || (buf >= NUM_BUFS)) {
return;
@@ -94,7 +97,7 @@
}
void usbdev_poll(usbdev_ctx_t *ctx) {
- uint32_t istate = REG32(USBDEV_INTR_STATE());
+ uint32_t istate = REG32(USBDEV_BASE_ADDR + USBDEV_INTR_STATE_REG_OFFSET);
// Do this first to keep things going
fill_av_fifo(ctx);
@@ -102,8 +105,8 @@
// Process IN completions first so we get the fact that send completed
// before processing a response
if (istate & (1 << USBDEV_INTR_STATE_PKT_SENT)) {
- uint32_t sentep = REG32(USBDEV_IN_SENT());
- uint32_t configin = USBDEV_CONFIGIN_0();
+ uint32_t sentep = REG32(USBDEV_BASE_ADDR + USBDEV_IN_SENT_REG_OFFSET);
+ uint32_t configin = USBDEV_BASE_ADDR + USBDEV_CONFIGIN_0_REG_OFFSET;
TRC_C('a' + sentep);
for (int ep = 0; ep < NUM_ENDPOINTS; ep++) {
if (sentep & (1 << ep)) {
@@ -116,14 +119,16 @@
}
}
// Write one to clear all the ones we handled
- REG32(USBDEV_IN_SENT()) = sentep;
+ REG32(USBDEV_BASE_ADDR + USBDEV_IN_SENT_REG_OFFSET) = sentep;
// Clear the interupt
- REG32(USBDEV_INTR_STATE()) = (1 << USBDEV_INTR_STATE_PKT_SENT);
+ REG32(USBDEV_BASE_ADDR + USBDEV_INTR_STATE_REG_OFFSET) =
+ (1 << USBDEV_INTR_STATE_PKT_SENT);
}
if (istate & (1 << USBDEV_INTR_STATE_PKT_RECEIVED)) {
- while (!(REG32(USBDEV_USBSTAT()) & (1 << USBDEV_USBSTAT_RX_EMPTY))) {
- uint32_t rxinfo = REG32(USBDEV_RXFIFO());
+ while (!(REG32(USBDEV_BASE_ADDR + USBDEV_USBSTAT_REG_OFFSET) &
+ (1 << USBDEV_USBSTAT_RX_EMPTY))) {
+ uint32_t rxinfo = REG32(USBDEV_BASE_ADDR + USBDEV_RXFIFO_REG_OFFSET);
usbbufid_t buf = EXTRACT(rxinfo, RXFIFO_BUFFER);
int size = EXTRACT(rxinfo, RXFIFO_SIZE);
int endpoint = EXTRACT(rxinfo, RXFIFO_EP);
@@ -138,7 +143,8 @@
usbdev_buf_free_byid(ctx, buf);
}
// Clear the interupt
- REG32(USBDEV_INTR_STATE()) = (1 << USBDEV_INTR_STATE_PKT_RECEIVED);
+ REG32(USBDEV_BASE_ADDR + USBDEV_INTR_STATE_REG_OFFSET) =
+ (1 << USBDEV_INTR_STATE_PKT_RECEIVED);
}
if (istate &
~((1 << USBDEV_INTR_STATE_PKT_RECEIVED) |
@@ -146,9 +152,9 @@
TRC_C('I');
TRC_I(istate, 12);
TRC_C(' ');
- REG32(USBDEV_INTR_STATE()) = istate &
- ~((1 << USBDEV_INTR_STATE_PKT_RECEIVED) |
- (1 << USBDEV_INTR_STATE_PKT_SENT));
+ REG32(USBDEV_BASE_ADDR + USBDEV_INTR_STATE_REG_OFFSET) =
+ istate & ~((1 << USBDEV_INTR_STATE_PKT_RECEIVED) |
+ (1 << USBDEV_INTR_STATE_PKT_SENT));
if (istate & (1 << USBDEV_INTR_ENABLE_LINK_RESET)) {
// Link reset
for (int ep = 0; ep < NUM_ENDPOINTS; ep++) {
@@ -158,14 +164,16 @@
}
// Clear the interupt
- REG32(USBDEV_INTR_STATE()) = (1 << USBDEV_INTR_ENABLE_LINK_RESET);
+ REG32(USBDEV_BASE_ADDR + USBDEV_INTR_STATE_REG_OFFSET) =
+ (1 << USBDEV_INTR_ENABLE_LINK_RESET);
}
}
// TODO - clean this up
// Frame ticks every 1ms, use to flush data every 16ms
// (faster in DPI but this seems to work ok)
// At reset frame count is 0, compare to 1 so no calls before SOF received
- uint32_t usbframe = EXTRACT(REG32(USBDEV_USBSTAT()), USBSTAT_FRAME);
+ uint32_t usbframe = EXTRACT(
+ REG32(USBDEV_BASE_ADDR + USBDEV_USBSTAT_REG_OFFSET), USBSTAT_FRAME);
if ((usbframe & 0xf) == 1) {
if (ctx->flushed == 0) {
for (int i = 0; i < NUM_ENDPOINTS; i++) {
@@ -182,35 +190,38 @@
}
unsigned int usbdev_get_status(usbdev_ctx_t *ctx) {
- unsigned int status = REG32(USBDEV_USBSTAT());
+ unsigned int status = REG32(USBDEV_BASE_ADDR + USBDEV_USBSTAT_REG_OFFSET);
return status;
}
unsigned int usbdev_get_link_state(usbdev_ctx_t *ctx) {
- unsigned int link_state =
- EXTRACT(REG32(USBDEV_USBSTAT()), USBSTAT_LINK_STATE);
+ unsigned int link_state = EXTRACT(
+ REG32(USBDEV_BASE_ADDR + USBDEV_USBSTAT_REG_OFFSET), USBSTAT_LINK_STATE);
return link_state;
}
unsigned int usbdev_get_address(usbdev_ctx_t *ctx) {
- unsigned int addr = EXTRACT(REG32(USBDEV_USBCTRL()), USBCTRL_DEVICE_ADDRESS);
+ unsigned int addr =
+ EXTRACT(REG32(USBDEV_BASE_ADDR + USBDEV_USBCTRL_REG_OFFSET),
+ USBCTRL_DEVICE_ADDRESS);
return addr;
}
void usbdev_set_deviceid(usbdev_ctx_t *ctx, int deviceid) {
- REG32(USBDEV_USBCTRL()) = (1 << USBDEV_USBCTRL_ENABLE) |
- (deviceid << USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET);
+ REG32(USBDEV_BASE_ADDR + USBDEV_USBCTRL_REG_OFFSET) =
+ (1 << USBDEV_USBCTRL_ENABLE) |
+ (deviceid << USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET);
}
void usbdev_halt(usbdev_ctx_t *ctx, int endpoint, int enable) {
uint32_t epbit = 1 << endpoint;
- uint32_t stall = REG32(USBDEV_STALL());
+ uint32_t stall = REG32(USBDEV_BASE_ADDR + USBDEV_STALL_REG_OFFSET);
if (enable) {
stall |= epbit;
} else {
stall &= ~epbit;
}
- REG32(USBDEV_STALL()) = stall;
+ REG32(USBDEV_BASE_ADDR + USBDEV_STALL_REG_OFFSET) = stall;
ctx->halted = stall;
// TODO future addition would be to callback the endpoint driver
// for now it just sees its traffic has stopped
@@ -218,21 +229,26 @@
void usbdev_set_iso(usbdev_ctx_t *ctx, int endpoint, int enable) {
if (enable) {
- REG32(USBDEV_ISO()) = SETBIT(REG32(USBDEV_ISO()), endpoint);
+ REG32(USBDEV_BASE_ADDR + USBDEV_ISO_REG_OFFSET) =
+ SETBIT(REG32(USBDEV_BASE_ADDR + USBDEV_ISO_REG_OFFSET), endpoint);
} else {
- REG32(USBDEV_ISO()) = CLRBIT(REG32(USBDEV_ISO()), endpoint);
+ REG32(USBDEV_BASE_ADDR + USBDEV_ISO_REG_OFFSET) =
+ CLRBIT(REG32(USBDEV_BASE_ADDR + USBDEV_ISO_REG_OFFSET), endpoint);
}
}
void usbdev_clear_data_toggle(usbdev_ctx_t *ctx, int endpoint) {
- REG32(USBDEV_DATA_TOGGLE_CLEAR()) = (1 << endpoint);
+ REG32(USBDEV_BASE_ADDR + USBDEV_DATA_TOGGLE_CLEAR_REG_OFFSET) =
+ (1 << endpoint);
}
void usbdev_set_ep0_stall(usbdev_ctx_t *ctx, int stall) {
if (stall) {
- REG32(USBDEV_STALL()) = REG32(USBDEV_STALL()) | 1;
+ REG32(USBDEV_BASE_ADDR + USBDEV_STALL_REG_OFFSET) =
+ REG32(USBDEV_BASE_ADDR + USBDEV_STALL_REG_OFFSET) | 1;
} else {
- REG32(USBDEV_STALL()) = REG32(USBDEV_STALL()) & ~(1);
+ REG32(USBDEV_BASE_ADDR + USBDEV_STALL_REG_OFFSET) =
+ REG32(USBDEV_BASE_ADDR + USBDEV_STALL_REG_OFFSET) & ~(1);
}
}
@@ -249,9 +265,9 @@
ctx->flush[ep] = flush;
ctx->reset[ep] = reset;
if (enableout) {
- uint32_t rxen = REG32(USBDEV_RXENABLE_OUT());
+ uint32_t rxen = REG32(USBDEV_BASE_ADDR + USBDEV_RXENABLE_OUT_REG_OFFSET);
rxen |= (1 << (ep + USBDEV_RXENABLE_OUT_OUT_0));
- REG32(USBDEV_RXENABLE_OUT()) = rxen;
+ REG32(USBDEV_BASE_ADDR + USBDEV_RXENABLE_OUT_REG_OFFSET) = rxen;
}
}
@@ -265,19 +281,22 @@
buf_init(ctx);
// All about polling...
- REG32(USBDEV_INTR_ENABLE()) = 0;
+ REG32(USBDEV_BASE_ADDR + USBDEV_INTR_ENABLE_REG_OFFSET) = 0;
// Provide buffers for any reception
fill_av_fifo(ctx);
- REG32(USBDEV_RXENABLE_SETUP()) = (1 << USBDEV_RXENABLE_SETUP_SETUP_0);
- REG32(USBDEV_RXENABLE_OUT()) = (1 << USBDEV_RXENABLE_OUT_OUT_0);
+ REG32(USBDEV_BASE_ADDR + USBDEV_RXENABLE_SETUP_REG_OFFSET) =
+ (1 << USBDEV_RXENABLE_SETUP_SETUP_0);
+ REG32(USBDEV_BASE_ADDR + USBDEV_RXENABLE_OUT_REG_OFFSET) =
+ (1 << USBDEV_RXENABLE_OUT_OUT_0);
uint32_t phy_config = (pinflip << USBDEV_PHY_CONFIG_PINFLIP) |
(diff_rx << USBDEV_PHY_CONFIG_RX_DIFFERENTIAL_MODE) |
(diff_tx << USBDEV_PHY_CONFIG_TX_DIFFERENTIAL_MODE) |
(1 << USBDEV_PHY_CONFIG_EOP_SINGLE_BIT);
- REG32(USBDEV_PHY_CONFIG()) = phy_config;
+ REG32(USBDEV_BASE_ADDR + USBDEV_PHY_CONFIG_REG_OFFSET) = phy_config;
- REG32(USBDEV_USBCTRL()) = (1 << USBDEV_USBCTRL_ENABLE);
+ REG32(USBDEV_BASE_ADDR + USBDEV_USBCTRL_REG_OFFSET) =
+ (1 << USBDEV_USBCTRL_ENABLE);
}
