[top] Align tops to use JTAG port from pinmux
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 6d2fe8b..3960515 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -471,6 +471,25 @@
}
]
}
+ {
+ name: rv_dm
+ type: rv_dm
+ inter_signal_list:
+ [
+ {
+ struct: jtag
+ type: req_rsp
+ name: jtag
+ act: rsp
+ package: jtag_pkg
+ inst_name: rv_dm
+ width: 1
+ default: ""
+ top_signame: pinmux_aon_rv_jtag
+ index: -1
+ }
+ ]
+ }
]
module:
[
@@ -2471,7 +2490,17 @@
clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
}
size: 0x1000
- param_list: []
+ param_list:
+ [
+ {
+ name: TargetCfg
+ desc: Target specific pinmux configuration.
+ type: pinmux_pkg::target_cfg_t
+ default: pinmux_pkg::DefaultTargetCfg
+ expose: "true"
+ name_top: PinmuxAonTargetCfg
+ }
+ ]
inter_signal_list:
[
{
@@ -2519,6 +2548,9 @@
act: req
width: 1
inst_name: pinmux_aon
+ default: ""
+ end_idx: -1
+ top_signame: pinmux_aon_rv_jtag
index: -1
}
{
@@ -5035,6 +5067,10 @@
[
lc_ctrl.jtag
]
+ pinmux_aon.rv_jtag:
+ [
+ rv_dm.jtag
+ ]
otp_ctrl.otp_lc_data:
[
lc_ctrl.otp_lc_data
@@ -9965,6 +10001,9 @@
act: req
width: 1
inst_name: pinmux_aon
+ default: ""
+ end_idx: -1
+ top_signame: pinmux_aon_rv_jtag
index: -1
}
{
@@ -11952,6 +11991,18 @@
index: -1
}
{
+ struct: jtag
+ type: req_rsp
+ name: jtag
+ act: rsp
+ package: jtag_pkg
+ inst_name: rv_dm
+ width: 1
+ default: ""
+ top_signame: pinmux_aon_rv_jtag
+ index: -1
+ }
+ {
struct: edn
type: req_rsp
name: edn
@@ -12884,6 +12935,28 @@
default: ""
}
{
+ package: jtag_pkg
+ struct: jtag_req
+ signame: pinmux_aon_rv_jtag_req
+ width: 1
+ type: req_rsp
+ end_idx: -1
+ act: req
+ suffix: req
+ default: ""
+ }
+ {
+ package: jtag_pkg
+ struct: jtag_rsp
+ signame: pinmux_aon_rv_jtag_rsp
+ width: 1
+ type: req_rsp
+ end_idx: -1
+ act: req
+ suffix: rsp
+ default: ""
+ }
+ {
package: otp_ctrl_pkg
struct: otp_lc_data
signame: otp_ctrl_otp_lc_data
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index e9745ae..8d04ace 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -204,7 +204,17 @@
},
],
}
-
+ { name: "rv_dm",
+ type: "rv_dm",
+ inter_signal_list: [
+ { struct: "jtag",
+ type: "req_rsp",
+ name: "jtag",
+ act: "rsp",
+ package: "jtag_pkg",
+ },
+ ]
+ }
]
// `module` defines the peripherals.
@@ -804,9 +814,7 @@
// automatically by the DFT insertion tool,
// hence it does not have to be connected here.
'pinmux_aon.lc_jtag' : ['lc_ctrl.jtag'],
- // TODO: connect this once JTAG muxing is functional
- // and also works on FPGA.
- //'pinmux_aon.rv_jtag' : ['rv_dm.jtag'],
+ 'pinmux_aon.rv_jtag' : ['rv_dm.jtag'],
// OTP LC interface
'otp_ctrl.otp_lc_data' : ['lc_ctrl.otp_lc_data'],
@@ -821,7 +829,6 @@
'lc_ctrl.lc_keymgr_div' : ['keymgr.lc_keymgr_div'],
// LC function control signal broadcast
- // TODO(#3920): connect all these signals once top-level sim and FPGA can backload LC state
'lc_ctrl.lc_dft_en' : ['otp_ctrl.lc_dft_en',
'pinmux_aon.lc_dft_en'],
'lc_ctrl.lc_nvm_debug_en' : ['eflash.lc_nvm_debug_en'],
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 31530a6..d57ff98 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -54,13 +54,6 @@
// Reset, clocks defined as part of intermodule
input rst_ni,
- // JTAG interface
- input jtag_tck_i,
- input jtag_tms_i,
- input jtag_trst_ni,
- input jtag_tdi_i,
- output jtag_tdo_o,
-
% if num_mio != 0:
// Multiplexed I/O
input ${lib.bitarray(num_mio, max_sigwidth)} mio_in_i,
@@ -296,19 +289,6 @@
// Debug Module (RISC-V Debug Spec 0.13)
//
- // TODO: this will be routed to the pinmux for TAP selection
- // based on straps and LC control signals.
- jtag_pkg::jtag_req_t jtag_req;
- jtag_pkg::jtag_rsp_t jtag_rsp;
- logic unused_jtag_tdo_oe_o;
-
- assign jtag_req.tck = jtag_tck_i;
- assign jtag_req.tms = jtag_tms_i;
- assign jtag_req.trst_n = jtag_trst_ni;
- assign jtag_req.tdi = jtag_tdi_i;
- assign jtag_tdo_o = jtag_rsp.tdo;
- assign unused_jtag_tdo_oe_o = jtag_rsp.tdo_oe;
-
rv_dm #(
.NrHarts (1),
.IdcodeValue (JTAG_IDCODE)
@@ -331,8 +311,8 @@
.tl_h_i (main_tl_dm_sba_rsp),
//JTAG
- .jtag_req_i (jtag_req),
- .jtag_rsp_o (jtag_rsp)
+ .jtag_req_i (pinmux_aon_rv_jtag_req),
+ .jtag_rsp_o (pinmux_aon_rv_jtag_rsp)
);
assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req;
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
index 2658312..b9bdd35 100644
--- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -220,6 +220,17 @@
default: "5",
local: "true"
},
+ // Since the target-specific top-levels often have slightly
+ // different debug signal positions, we need a way to pass
+ // this info from the target specific top-level into the pinmux
+ // logic. The parameter struct below serves this purpose.
+ { name: "TargetCfg",
+ desc: "Target specific pinmux configuration.",
+ type: "pinmux_pkg::target_cfg_t",
+ default: "pinmux_pkg::DefaultTargetCfg",
+ local: "false",
+ expose: "true"
+ },
],
registers: [
//////////////////////////
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 93e1f7a..72611d1 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -13,6 +13,7 @@
module top_earlgrey #(
// Auto-inferred parameters
parameter OtpCtrlMemInitFile = "",
+ parameter pinmux_pkg::target_cfg_t PinmuxAonTargetCfg = pinmux_pkg::DefaultTargetCfg,
parameter bit SramCtrlRetAonInstrExec = 1,
parameter bit AesMasking = 1'b1,
parameter aes_pkg::sbox_impl_e AesSBoxImpl = aes_pkg::SBoxImplDom,
@@ -34,13 +35,6 @@
// Reset, clocks defined as part of intermodule
input rst_ni,
- // JTAG interface
- input jtag_tck_i,
- input jtag_tms_i,
- input jtag_trst_ni,
- input jtag_tdi_i,
- output jtag_tdo_o,
-
// Multiplexed I/O
input [43:0] mio_in_i,
output logic [43:0] mio_out_o,
@@ -457,6 +451,8 @@
logic [3:0] clkmgr_aon_idle;
jtag_pkg::jtag_req_t pinmux_aon_lc_jtag_req;
jtag_pkg::jtag_rsp_t pinmux_aon_lc_jtag_rsp;
+ jtag_pkg::jtag_req_t pinmux_aon_rv_jtag_req;
+ jtag_pkg::jtag_rsp_t pinmux_aon_rv_jtag_rsp;
otp_ctrl_pkg::otp_lc_data_t otp_ctrl_otp_lc_data;
otp_ctrl_pkg::lc_otp_program_req_t lc_ctrl_lc_otp_program_req;
otp_ctrl_pkg::lc_otp_program_rsp_t lc_ctrl_lc_otp_program_rsp;
@@ -693,19 +689,6 @@
// Debug Module (RISC-V Debug Spec 0.13)
//
- // TODO: this will be routed to the pinmux for TAP selection
- // based on straps and LC control signals.
- jtag_pkg::jtag_req_t jtag_req;
- jtag_pkg::jtag_rsp_t jtag_rsp;
- logic unused_jtag_tdo_oe_o;
-
- assign jtag_req.tck = jtag_tck_i;
- assign jtag_req.tms = jtag_tms_i;
- assign jtag_req.trst_n = jtag_trst_ni;
- assign jtag_req.tdi = jtag_tdi_i;
- assign jtag_tdo_o = jtag_rsp.tdo;
- assign unused_jtag_tdo_oe_o = jtag_rsp.tdo_oe;
-
rv_dm #(
.NrHarts (1),
.IdcodeValue (JTAG_IDCODE)
@@ -728,8 +711,8 @@
.tl_h_i (main_tl_dm_sba_rsp),
//JTAG
- .jtag_req_i (jtag_req),
- .jtag_rsp_o (jtag_rsp)
+ .jtag_req_i (pinmux_aon_rv_jtag_req),
+ .jtag_rsp_o (pinmux_aon_rv_jtag_rsp)
);
assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req;
@@ -1643,15 +1626,17 @@
.rst_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
);
- pinmux u_pinmux_aon (
+ pinmux #(
+ .TargetCfg(PinmuxAonTargetCfg)
+ ) u_pinmux_aon (
// Inter-module signals
.lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
.lc_dft_en_i(lc_ctrl_lc_dft_en),
.lc_jtag_o(pinmux_aon_lc_jtag_req),
.lc_jtag_i(pinmux_aon_lc_jtag_rsp),
- .rv_jtag_o(),
- .rv_jtag_i(jtag_pkg::JTAG_RSP_DEFAULT),
+ .rv_jtag_o(pinmux_aon_rv_jtag_req),
+ .rv_jtag_i(pinmux_aon_rv_jtag_rsp),
.dft_jtag_o(),
.dft_jtag_i(jtag_pkg::JTAG_RSP_DEFAULT),
.dft_strap_test_o(),
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index 0481f10..e93bbef 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -191,9 +191,26 @@
act: "req",
package: "ibex_pkg",
},
+
+ { struct: "lc_tx_t",
+ type: "uni",
+ name: "lc_cpu_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
],
}
-
+ { name: "rv_dm",
+ type: "rv_dm",
+ inter_signal_list: [
+ { struct: "jtag",
+ type: "req_rsp",
+ name: "jtag",
+ act: "rsp",
+ package: "jtag_pkg",
+ },
+ ]
+ }
]
// `module` defines the peripherals.
@@ -596,17 +613,24 @@
// an empty list.
'clkmgr_aon.idle' : [],
+ // Pinmux JTAG signals
+ // Note that the DFT TAP will be connected
+ // automatically by the DFT insertion tool,
+ // hence it does not have to be connected here.
+ 'pinmux_aon.lc_jtag' : ['lc_ctrl.jtag'],
+ 'pinmux_aon.rv_jtag' : ['rv_dm.jtag'],
+
// LC function control signal broadcast
- // TODO(#3920): connect all these signals once top-level sim and FPGA can backload LC state
- 'lc_ctrl.lc_dft_en' : [],
+ 'lc_ctrl.lc_dft_en' : ['pinmux_aon.lc_dft_en'],
'lc_ctrl.lc_nvm_debug_en' : ['eflash.lc_nvm_debug_en'],
'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en',
- 'sram_ctrl_ret_aon.lc_hw_debug_en'],
- 'lc_ctrl.lc_cpu_en' : [],
- 'lc_ctrl.lc_escalate_en' : ['sram_ctrl_main.lc_escalate_en',
- 'sram_ctrl_ret_aon.lc_escalate_en'],
- 'lc_ctrl.lc_check_byp_en' : [],
- // TODO: OTP Clock bypass signal going from LC to AST/clkmgr
+ 'sram_ctrl_ret_aon.lc_hw_debug_en',
+ 'pinmux_aon.lc_hw_debug_en'],
+ 'lc_ctrl.lc_cpu_en' : ['rv_core_ibex.lc_cpu_en'],
+ 'lc_ctrl.lc_keymgr_en' : [],
+ 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en',
+ 'sram_ctrl_main.lc_escalate_en',
+ 'sram_ctrl_ret_aon.lc_escalate_en'], // TODO: OTP Clock bypass signal going from LC to AST/clkmgr
'lc_ctrl.lc_clk_byp_ack' : ['clkmgr_aon.lc_clk_bypass_ack'],
// LC access control signal broadcast
