[syn] Minor updates to synthesis script
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/aes/syn/constraints.sdc b/hw/ip/aes/syn/constraints.sdc
index 151bea0..cd84ef7 100644
--- a/hw/ip/aes/syn/constraints.sdc
+++ b/hw/ip/aes/syn/constraints.sdc
@@ -38,8 +38,8 @@
#####################
# attach load and drivers to IOs to get a more realistic estimate
-set_driving_cell -no_design_rule -lib_cell ${driving_cell} -pin X [all_inputs]
-set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs]
+set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin X [all_inputs]
+set_load [load_of ${LOAD_LIB}/${LOAD_CELL}/A] [all_outputs]
# set a nonzero critical range to be able to spot the violating paths better
# in the report
diff --git a/hw/syn/tools/dc/run-syn.tcl b/hw/syn/tools/dc/run-syn.tcl
index ef52d2f..5a1d758 100644
--- a/hw/syn/tools/dc/run-syn.tcl
+++ b/hw/syn/tools/dc/run-syn.tcl
@@ -62,7 +62,7 @@
# this PRIM_DEFAULT_IMPL selects the appropriate technology by defining
# PRIM_DEFAULT_IMPL=prim_pkg::Impl<tech identifier>
# PRIM_DEFAULT_IMPL is set inside the library setup script
-set DEFINE "PRIM_DEFAULT_IMPL=${PRIM_DEFAULT_IMPL} "
+set DEFINE "PRIM_DEFAULT_IMPL=${PRIM_DEFAULT_IMPL}+${PRIM_STD_CELL_VARIANT}"
# additional parameters
set PARAMS ""
diff --git a/hw/syn/tools/dc/sweep.tcl b/hw/syn/tools/dc/sweep.tcl
index fd8a9b3..018654c 100644
--- a/hw/syn/tools/dc/sweep.tcl
+++ b/hw/syn/tools/dc/sweep.tcl
@@ -86,8 +86,8 @@
set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${CLK_PIN}}] -clock ${CLK_PIN}
set_output_delay ${OUT_DEL} [all_outputs] -clock ${CLK_PIN}
- set_driving_cell -no_design_rule -lib_cell ${driving_cell} -pin X [all_inputs]
- set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs]
+ set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin X [all_inputs]
+ set_load [load_of ${LOAD_LIB}/${LOAD_CELL}/A] [all_outputs]
######################
## MAP DESIGN ##
diff --git a/hw/syn/tools/dc/testsynth.tcl b/hw/syn/tools/dc/testsynth.tcl
index d73cbe1..1425069 100644
--- a/hw/syn/tools/dc/testsynth.tcl
+++ b/hw/syn/tools/dc/testsynth.tcl
@@ -77,8 +77,8 @@
set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${CLK_PIN}}] -clock ${CLK_PIN}
set_output_delay ${OUT_DEL} [all_outputs] -clock ${CLK_PIN}
-set_driving_cell -no_design_rule -lib_cell ${driving_cell} -pin X [all_inputs]
-set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs]
+set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin X [all_inputs]
+set_load [load_of ${LOAD_LIB}/${LOAD_CELL}/A] [all_outputs]
# set a nonzero critical range to be able to spot the violating paths better
# in the report
diff --git a/hw/top_earlgrey/syn/constraints.sdc b/hw/top_earlgrey/syn/constraints.sdc
index 8a682c0..a7cb5a2 100644
--- a/hw/top_earlgrey/syn/constraints.sdc
+++ b/hw/top_earlgrey/syn/constraints.sdc
@@ -90,7 +90,7 @@
set IO_TCK 40.0
set_ideal_network ${IO_CLK_PIN}
-create_clock -name IO_CLK -period ${IO_TCK} [get_ports ${IO_CLK_PIN}]
+create_clock -name IO_CLK -period ${IO_TCK} [get_ports ${IO_CLK_PIN}]
set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} [get_clocks IO_CLK]
# TODO: generated clock
@@ -186,8 +186,8 @@
#####################
# attach load and drivers to IOs to get a more realistic estimate
-set_driving_cell -no_design_rule -lib_cell ${driving_cell} -pin X [all_inputs]
-set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs]
+set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin X [all_inputs]
+set_load [load_of ${LOAD_LIB}/${LOAD_CELL}/A] [all_outputs]
# set a nonzero critical range to be able to spot the violating paths better
# in the report
