commit 5ddcc73c40e48726689f363d6e65401e1287449e
author Cindy Chen <chencindy@google.com> Fri Dec 06 14:08:50 2019 -0800
committer cindychip <cindy.chen0316@gmail.com> Fri Dec 06 14:54:06 2019 -0800
tree a08dc6f8e971d3c04deb4c98655f1859ca757ddc
parent ccef8272d863abb423883f83330d34cdc156107a

[fpv/tcl] Fix tcl file compile error

Fix tcl fix compile error

Signed-off-by: Cindy Chen <chencindy@google.com>

util/reggen/fpv_csr.sv.tpl

diff --git a/util/reggen/fpv_csr.sv.tpl b/util/reggen/fpv_csr.sv.tpl
index 8fdfa27..8b41de9 100644
--- a/util/reggen/fpv_csr.sv.tpl
+++ b/util/reggen/fpv_csr.sv.tpl
@@ -188,7 +188,7 @@
   `ASSERT(${reg_name}_rd_A, ${rd_prperty}(${reg_msb}, ${reg_offset}, ${reg_qs_path}), clk_i, !rst_ni)
       % elif reg_flat.get_n_bits(["d"]):
   `ASSERT(${reg_name}_rd_A, ${rd_prperty}(${reg_msb}, ${reg_offset}, ${reg_d_path}), clk_i, !rst_ni)
-      % elif reg_flat.get_n_bits(["q"]) and (r.ishomog or (not r.ishomog) and r.get_field_flat[0].get_n_bits(["q"])>0):
+      % elif reg_flat.get_n_bits(["q"]) and (r.ishomog or ((not r.ishomog) and r.get_fields_flat()[0].get_n_bits(["q"]))):
   `ASSERT(${reg_name}_rd_A, ${rd_prperty}(${reg_msb}, ${reg_offset}, ${reg_q_path}), clk_i, !rst_ni)
       % endif
     % endif