[rv_timer/dv] Added generic task for intr test
1. cip_base_vseq: Added task to check intr test register functionality
2. rv_timer_scoreboard: Enhancement for intr test register
3. rv_timer_env_pkg: Fixed glint errors
4. *_csr_vseq.sv: Renamed to *_common_vseq.sv
5. Makefile, *.tpl, *_vseq_list: Added intr test and renamed
IP_csr_vseq to IP_commong_vseq
6. rv_timer_vseq_list: Removed intr seq
7. uart_intr_testmode_vseq, uart_vseq_list: Removed intr seq
8. *_base_vseq: Removed body from IP base seq
diff --git a/hw/dv/sv/cip_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/cip_base_vseq.sv
index 860b41b..5460ec4 100644
--- a/hw/dv/sv/cip_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/cip_base_vseq.sv
@@ -69,10 +69,11 @@
// scope: for top level, specify which ip / sub module's interrupt to clear
// common task
- local function uvm_reg get_interrupt_csr(string csr_name,
- string suffix = "",
- int indices[$] = {},
- uvm_reg_block scope = null);
+ local function dv_base_reg get_interrupt_csr(string csr_name,
+ string suffix = "",
+ int indices[$] = {},
+ uvm_reg_block scope = null);
+ uvm_reg csr;
if (indices.size() != 0) begin
foreach (indices[i]) begin
suffix = {suffix, (i == 0) ? "" : "_", $sformatf("%0d", i)};
@@ -81,10 +82,11 @@
end
// check within scope first, if supplied
if (scope != null) begin
- get_interrupt_csr = scope.get_reg_by_name(csr_name);
+ csr = scope.get_reg_by_name(csr_name);
end else begin
- get_interrupt_csr = ral.get_reg_by_name(csr_name);
+ csr = ral.get_reg_by_name(csr_name);
end
+ `downcast(get_interrupt_csr, csr)
`DV_CHECK_NE_FATAL(get_interrupt_csr, null)
endfunction
@@ -139,6 +141,105 @@
end
endtask
- // TODO add test sequence for intr_test
+ // wrapper task to call common test or csr tests
+ virtual task run_common_vseq_wrapper(int num_times = 1);
+ string test_type;
+ void'($value$plusargs("run_%0s", test_type));
+ // check which test type
+ case (test_type)
+ "intr_test": run_intr_test_vseq(num_times);
+ default : run_csr_vseq_wrapper(num_times);
+ endcase
+ endtask
+
+ // generic task to check interrupt test reg functionality
+ virtual task run_intr_test_vseq(int num_times = 1);
+ uvm_reg all_csrs[$];
+ dv_base_reg intr_test_csrs[$];
+ dv_base_reg intr_state_csrs[$];
+ dv_base_reg intr_enable_csrs[$];
+ bit [TL_DW-1:0] exp_intr_state[$];
+ int test_index[$];
+
+ // Get all interrupt test/state/enable registers
+ ral.get_registers(all_csrs);
+ foreach (all_csrs[i]) begin
+ string csr_name = all_csrs[i].get_name();
+ if (!uvm_re_match("intr_test*", csr_name)) begin
+ test_index.push_back(intr_test_csrs.size());
+ intr_test_csrs.push_back(get_interrupt_csr(csr_name));
+ end
+ else if (!uvm_re_match("intr_enable*", csr_name)) begin
+ intr_enable_csrs.push_back(get_interrupt_csr(csr_name));
+ end
+ else if (!uvm_re_match("intr_state*", csr_name)) begin
+ intr_state_csrs.push_back(get_interrupt_csr(csr_name));
+ //Place holder for expected intr state value
+ exp_intr_state.push_back(0);
+ end
+ end
+ all_csrs.delete();
+
+ // check intr test, enable and state queue sizes are equal
+ `DV_CHECK_EQ_FATAL(intr_enable_csrs.size(), intr_test_csrs.size())
+ `DV_CHECK_EQ_FATAL(intr_state_csrs.size(), intr_test_csrs.size())
+
+ for (int trans = 1; trans <= num_times; trans++) begin
+ bit [TL_DW-1:0] num_used_bits;
+ bit [TL_DW-1:0] intr_enable_val[$];
+ `uvm_info(`gfn, $sformatf("Running intr test iteration %0d/%0d", trans, num_times), UVM_LOW)
+ // Random Write to all intr enable registers
+ test_index.shuffle();
+ foreach (test_index[i]) begin
+ bit [TL_DW-1:0] wr_data;
+ wr_data = $urandom_range(1, ((1 << intr_enable_csrs[test_index[i]].get_n_used_bits()) - 1));
+ intr_enable_val.insert(test_index[i], wr_data);
+ csr_wr(.csr(intr_enable_csrs[test_index[i]]), .value(wr_data));
+ end
+
+ // Random write to all interrupt test reg
+ test_index.shuffle();
+ foreach (test_index[i]) begin
+ bit [TL_DW-1:0] wr_data;
+ wr_data = $urandom_range(1, ((1 << intr_test_csrs[test_index[i]].get_n_used_bits()) - 1));
+ // Add wr_data to expected state queue
+ exp_intr_state[test_index[i]] |= wr_data;
+ csr_wr(.csr(intr_test_csrs[test_index[i]]), .value(wr_data));
+ end
+
+ // Read all intr state
+ test_index.shuffle();
+ foreach (test_index[i]) begin
+ bit [TL_DW-1:0] dut_intr_state;
+ `uvm_info(`gtn, $sformatf("Verifying %0s", intr_test_csrs[test_index[i]].get_full_name()),
+ UVM_LOW)
+ csr_rd(.ptr(intr_state_csrs[test_index[i]]), .value(dut_intr_state));
+ `DV_CHECK_EQ(dut_intr_state, exp_intr_state[test_index[i]])
+ end
+
+ // check interrupt pins
+ foreach (intr_test_csrs[i]) begin
+ bit [TL_DW-1:0] exp_intr_pin;
+ exp_intr_pin = exp_intr_state[i] & intr_enable_val[i];
+ for (int j = 0; j < intr_test_csrs[i].get_n_used_bits(); j++) begin
+ bit act_intr_pin_val = cfg.intr_vif.sample_pin(j + num_used_bits);
+ `DV_CHECK_CASE_EQ(act_intr_pin_val, exp_intr_pin[j], $sformatf(
+ "exp_intr_state: %0h, en_intr: %0h", exp_intr_state[i], intr_enable_val[i]))
+ end
+ num_used_bits += intr_test_csrs[i].get_n_used_bits();
+ end
+
+ // clear random bits of intr state
+ test_index.shuffle();
+ foreach (test_index[i]) begin
+ if ($urandom_range(0, 1)) begin
+ bit [TL_DW-1:0] wr_data;
+ wr_data = $urandom_range((1 << intr_state_csrs[test_index[i]].get_n_used_bits()) - 1);
+ exp_intr_state[test_index[i]] &= (~wr_data);
+ csr_wr(.csr(intr_state_csrs[test_index[i]]), .value(wr_data));
+ end
+ end
+ end
+ endtask
endclass
diff --git a/hw/ip/gpio/dv/Makefile b/hw/ip/gpio/dv/Makefile
index 92e9d5b..bea2b89 100644
--- a/hw/ip/gpio/dv/Makefile
+++ b/hw/ip/gpio/dv/Makefile
@@ -35,26 +35,31 @@
RUN_OPTS += +active_high_pullup=0
endif
+ifeq (${TEST_NAME},gpio_intr_test)
+ UVM_TEST_SEQ = gpio_common_vseq
+ RUN_OPTS += +run_intr_test
+endif
+
ifeq (${TEST_NAME},gpio_csr_hw_reset)
- UVM_TEST_SEQ = gpio_csr_vseq
+ UVM_TEST_SEQ = gpio_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},gpio_csr_rw)
- UVM_TEST_SEQ = gpio_csr_vseq
+ UVM_TEST_SEQ = gpio_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},gpio_csr_bit_bash)
- UVM_TEST_SEQ = gpio_csr_vseq
+ UVM_TEST_SEQ = gpio_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},gpio_csr_aliasing)
- UVM_TEST_SEQ = gpio_csr_vseq
+ UVM_TEST_SEQ = gpio_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv
index 14d7ebc..9696a05 100644
--- a/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv
+++ b/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv
@@ -22,10 +22,6 @@
super.pre_start();
endtask
- task body();
- `uvm_fatal(`gtn, "Need to override this when you extend from this class!")
- endtask : body
-
virtual task dut_shutdown();
// TODO(sriyerg): nothing to do yet
endtask
diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_csr_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_common_vseq.sv
similarity index 91%
rename from hw/ip/gpio/dv/env/seq_lib/gpio_csr_vseq.sv
rename to hw/ip/gpio/dv/env/seq_lib/gpio_common_vseq.sv
index cb65e90..b83fd80 100644
--- a/hw/ip/gpio/dv/env/seq_lib/gpio_csr_vseq.sv
+++ b/hw/ip/gpio/dv/env/seq_lib/gpio_common_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class gpio_csr_vseq extends gpio_base_vseq;
- `uvm_object_utils(gpio_csr_vseq)
+class gpio_common_vseq extends gpio_base_vseq;
+ `uvm_object_utils(gpio_common_vseq)
`uvm_object_new
constraint num_trans_c {
@@ -11,7 +11,7 @@
}
virtual task body();
- run_csr_vseq_wrapper(num_trans);
+ run_common_vseq_wrapper(num_trans);
endtask : body
// function to add csr exclusions of the given type using the csr_excl_item item
diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_vseq_list.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_vseq_list.sv
index 18ca7a5..3d58bc4 100644
--- a/hw/ip/gpio/dv/env/seq_lib/gpio_vseq_list.sv
+++ b/hw/ip/gpio/dv/env/seq_lib/gpio_vseq_list.sv
@@ -4,7 +4,7 @@
`include "gpio_base_vseq.sv"
`include "gpio_sanity_vseq.sv"
-`include "gpio_csr_vseq.sv"
+`include "gpio_common_vseq.sv"
`include "gpio_random_dout_din_vseq.sv"
`include "gpio_dout_din_regs_random_rw_vseq.sv"
`include "gpio_intr_rand_pgm_vseq.sv"
diff --git a/hw/ip/hmac/dv/Makefile b/hw/ip/hmac/dv/Makefile
index 9aabaa8..17de602 100644
--- a/hw/ip/hmac/dv/Makefile
+++ b/hw/ip/hmac/dv/Makefile
@@ -44,26 +44,31 @@
RUN_OPTS += +nist_vectors_dir=${DV_DIR}/../../../dv/sv/nist_vectors/
endif
+ifeq (${TEST_NAME},hmac_intr_test)
+ UVM_TEST_SEQ = hmac_common_vseq
+ RUN_OPTS += +run_intr_test
+endif
+
ifeq (${TEST_NAME},hmac_csr_hw_reset)
- UVM_TEST_SEQ = hmac_csr_vseq
+ UVM_TEST_SEQ = hmac_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},hmac_csr_rw)
- UVM_TEST_SEQ = hmac_csr_vseq
+ UVM_TEST_SEQ = hmac_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},hmac_csr_bit_bash)
- UVM_TEST_SEQ = hmac_csr_vseq
+ UVM_TEST_SEQ = hmac_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},hmac_csr_aliasing)
- UVM_TEST_SEQ = hmac_csr_vseq
+ UVM_TEST_SEQ = hmac_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index a26e491..b3688ba 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -34,10 +34,6 @@
solve wr_size before wr_mask;
}
- task body();
- `uvm_fatal(`gtn, "Need to override this when you extend from this class!")
- endtask : body
-
virtual task dut_init(string reset_kind = "HARD");
super.dut_init(reset_kind);
if (do_hmac_init) hmac_init();
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_csr_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_common_vseq.sv
similarity index 93%
rename from hw/ip/hmac/dv/env/seq_lib/hmac_csr_vseq.sv
rename to hw/ip/hmac/dv/env/seq_lib/hmac_common_vseq.sv
index f739572..2292273 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_csr_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_common_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class hmac_csr_vseq extends hmac_base_vseq;
- `uvm_object_utils(hmac_csr_vseq)
+class hmac_common_vseq extends hmac_base_vseq;
+ `uvm_object_utils(hmac_common_vseq)
`uvm_object_new
constraint num_trans_c {
@@ -16,7 +16,7 @@
endtask
virtual task body();
- run_csr_vseq_wrapper(num_trans);
+ run_common_vseq_wrapper(num_trans);
endtask : body
// function to add csr exclusions of the given type using the csr_excl_item item
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
index 97e901c..c3a2fd1 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
@@ -7,4 +7,4 @@
`include "hmac_long_msg_vseq.sv"
`include "hmac_nist_vectors_vseq.sv"
`include "hmac_back_pressure_vseq.sv"
-`include "hmac_csr_vseq.sv"
+`include "hmac_common_vseq.sv"
diff --git a/hw/ip/rv_timer/dv/Makefile b/hw/ip/rv_timer/dv/Makefile
index aaadb25..ed34125 100644
--- a/hw/ip/rv_timer/dv/Makefile
+++ b/hw/ip/rv_timer/dv/Makefile
@@ -44,26 +44,31 @@
UVM_TEST_SEQ = rv_timer_random_reset_vseq
endif
+ifeq (${TEST_NAME},rv_timer_intr_test)
+ UVM_TEST_SEQ = rv_timer_common_vseq
+ RUN_OPTS += +run_intr_test
+endif
+
ifeq (${TEST_NAME},rv_timer_csr_hw_reset)
- UVM_TEST_SEQ = rv_timer_csr_vseq
+ UVM_TEST_SEQ = rv_timer_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},rv_timer_csr_rw)
- UVM_TEST_SEQ = rv_timer_csr_vseq
+ UVM_TEST_SEQ = rv_timer_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},rv_timer_csr_bit_bash)
- UVM_TEST_SEQ = rv_timer_csr_vseq
+ UVM_TEST_SEQ = rv_timer_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},rv_timer_csr_aliasing)
- UVM_TEST_SEQ = rv_timer_csr_vseq
+ UVM_TEST_SEQ = rv_timer_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
diff --git a/hw/ip/rv_timer/dv/env/rv_timer_env_pkg.sv b/hw/ip/rv_timer/dv/env/rv_timer_env_pkg.sv
index 7a4feae..b512fb4 100644
--- a/hw/ip/rv_timer/dv/env/rv_timer_env_pkg.sv
+++ b/hw/ip/rv_timer/dv/env/rv_timer_env_pkg.sv
@@ -18,8 +18,8 @@
// local parameters and types
// TODO: these are currently hardcoded to 1 - this will need to change if design is modified
- parameter NUM_HARTS = 1;
- parameter NUM_TIMERS = 1;
+ parameter uint NUM_HARTS = 1;
+ parameter uint NUM_TIMERS = 1;
typedef class rv_timer_env_cfg;
typedef class rv_timer_env_cov;
diff --git a/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv b/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv
index 722b4e7..da44ed3 100644
--- a/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv
+++ b/hw/ip/rv_timer/dv/env/rv_timer_scoreboard.sv
@@ -129,11 +129,20 @@
if (csr_name == intr_state_str) begin
// Intr_state reg is W1C, update expected status with RAL mirrored val
intr_status_exp[i] = get_reg_fld_mirror_value(ral, intr_state_str);
+ break;
end
end
end
(!uvm_re_match("intr_test*", csr_name)): begin
- // TODO check it later
+ for (int i = 0; i < NUM_HARTS; i++) begin
+ string intr_test_str = $sformatf("intr_test%0d", i);
+ if (csr_name == intr_test_str) begin
+ intr_status_exp[i] = get_reg_fld_mirror_value(ral, intr_test_str);
+ // this field is WO - always returns 0
+ csr.predict(.value(0), .kind(UVM_PREDICT_WRITE));
+ break;
+ end
+ end
end
default: begin
`uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
diff --git a/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_base_vseq.sv b/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_base_vseq.sv
index 78679ae..688a378 100644
--- a/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_base_vseq.sv
+++ b/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_base_vseq.sv
@@ -38,10 +38,6 @@
super.pre_start();
endtask
- task body();
- `uvm_fatal(`gtn, "Need to override this when you extend from this class!")
- endtask : body
-
virtual task dut_init(string reset_kind = "HARD");
super.dut_init(reset_kind);
// TODO: nothing extra to do yet
diff --git a/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_csr_vseq.sv b/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_common_vseq.sv
similarity index 88%
rename from hw/ip/rv_timer/dv/env/seq_lib/rv_timer_csr_vseq.sv
rename to hw/ip/rv_timer/dv/env/seq_lib/rv_timer_common_vseq.sv
index df9b872..9e77456 100644
--- a/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_csr_vseq.sv
+++ b/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_common_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class rv_timer_csr_vseq extends rv_timer_base_vseq;
- `uvm_object_utils(rv_timer_csr_vseq)
+class rv_timer_common_vseq extends rv_timer_base_vseq;
+ `uvm_object_utils(rv_timer_common_vseq)
`uvm_object_new
constraint num_trans_c {
@@ -11,7 +11,7 @@
}
virtual task body();
- run_csr_vseq_wrapper(num_trans);
+ run_common_vseq_wrapper(num_trans);
endtask : body
// function to add csr exclusions of the given type using the csr_excl_item item
diff --git a/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_vseq_list.sv b/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_vseq_list.sv
index f905a0e..23a5077 100644
--- a/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_vseq_list.sv
+++ b/hw/ip/rv_timer/dv/env/seq_lib/rv_timer_vseq_list.sv
@@ -7,4 +7,4 @@
`include "rv_timer_random_reset_vseq.sv"
`include "rv_timer_disabled_vseq.sv"
`include "rv_timer_cfg_update_on_fly_vseq.sv"
-`include "rv_timer_csr_vseq.sv"
+`include "rv_timer_common_vseq.sv"
diff --git a/hw/ip/spi_device/dv/Makefile b/hw/ip/spi_device/dv/Makefile
index 1a5ea4d..78f11b9 100644
--- a/hw/ip/spi_device/dv/Makefile
+++ b/hw/ip/spi_device/dv/Makefile
@@ -31,35 +31,40 @@
endif
ifeq (${TEST_NAME},spi_device_csr_hw_reset)
- UVM_TEST_SEQ = spi_device_csr_vseq
+ UVM_TEST_SEQ = spi_device_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},spi_device_csr_rw)
- UVM_TEST_SEQ = spi_device_csr_vseq
+ UVM_TEST_SEQ = spi_device_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},spi_device_csr_bit_bash)
- UVM_TEST_SEQ = spi_device_csr_vseq
+ UVM_TEST_SEQ = spi_device_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},spi_device_csr_aliasing)
- UVM_TEST_SEQ = spi_device_csr_vseq
+ UVM_TEST_SEQ = spi_device_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},spi_device_csr_mem_walk)
- UVM_TEST_SEQ = spi_device_csr_vseq
+ UVM_TEST_SEQ = spi_device_common_vseq
RUN_OPTS += +csr_mem_walk
RUN_OPTS += +en_scb=0
endif
+ifeq (${TEST_NAME},spi_device_intr_test)
+ UVM_TEST_SEQ = spi_device_common_vseq
+ RUN_OPTS += +run_intr_test
+endif
+
ifeq (${TEST_NAME},spi_device_txrx)
UVM_TEST_SEQ = spi_device_txrx_vseq
endif
diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
index 1c39b99..5e3d1d3 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
@@ -35,10 +35,6 @@
`uvm_object_new
- task body();
- `uvm_fatal(`gtn, "Need to override this when you extend from this class!")
- endtask : body
-
virtual task apply_reset(string kind = "HARD");
super.apply_reset(kind);
cfg.clk_rst_vif.wait_clks(1);
diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_csr_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_common_vseq.sv
similarity index 91%
rename from hw/ip/spi_device/dv/env/seq_lib/spi_device_csr_vseq.sv
rename to hw/ip/spi_device/dv/env/seq_lib/spi_device_common_vseq.sv
index aca6aea..87733b9 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_csr_vseq.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_common_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class spi_device_csr_vseq extends spi_device_base_vseq;
- `uvm_object_utils(spi_device_csr_vseq)
+class spi_device_common_vseq extends spi_device_base_vseq;
+ `uvm_object_utils(spi_device_common_vseq)
`uvm_object_new
constraint num_trans_c {
@@ -17,7 +17,7 @@
endtask
virtual task body();
- run_csr_vseq_wrapper(num_trans);
+ run_common_vseq_wrapper(num_trans);
endtask : body
// function to add csr exclusions of the given type using the csr_excl_item item
diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_vseq_list.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_vseq_list.sv
index e76ecb8..26bdba1 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_vseq_list.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_vseq_list.sv
@@ -4,7 +4,7 @@
`include "spi_device_base_vseq.sv"
`include "spi_device_sanity_vseq.sv"
-`include "spi_device_csr_vseq.sv"
+`include "spi_device_common_vseq.sv"
`include "spi_device_txrx_vseq.sv"
`include "spi_device_fifo_full_vseq.sv"
`include "spi_device_fifo_underflow_overflow_vseq.sv"
diff --git a/hw/ip/uart/dv/Makefile b/hw/ip/uart/dv/Makefile
index b320b8c..081c108 100644
--- a/hw/ip/uart/dv/Makefile
+++ b/hw/ip/uart/dv/Makefile
@@ -49,8 +49,9 @@
UVM_TEST_SEQ = uart_fifo_reset_vseq
endif
-ifeq (${TEST_NAME},uart_intr_testmode)
- UVM_TEST_SEQ = uart_intr_testmode_vseq
+ifeq (${TEST_NAME},uart_intr_test)
+ UVM_TEST_SEQ = uart_common_vseq
+ RUN_OPTS += +run_intr_test
endif
ifeq (${TEST_NAME},uart_rx_oversample)
@@ -94,25 +95,25 @@
endif
ifeq (${TEST_NAME},uart_csr_hw_reset)
- UVM_TEST_SEQ = uart_csr_vseq
+ UVM_TEST_SEQ = uart_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},uart_csr_rw)
- UVM_TEST_SEQ = uart_csr_vseq
+ UVM_TEST_SEQ = uart_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},uart_csr_bit_bash)
- UVM_TEST_SEQ = uart_csr_vseq
+ UVM_TEST_SEQ = uart_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${TEST_NAME},uart_csr_aliasing)
- UVM_TEST_SEQ = uart_csr_vseq
+ UVM_TEST_SEQ = uart_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
diff --git a/hw/ip/uart/dv/env/seq_lib/uart_csr_vseq.sv b/hw/ip/uart/dv/env/seq_lib/uart_common_vseq.sv
similarity index 93%
rename from hw/ip/uart/dv/env/seq_lib/uart_csr_vseq.sv
rename to hw/ip/uart/dv/env/seq_lib/uart_common_vseq.sv
index e1e2211..7012c66 100644
--- a/hw/ip/uart/dv/env/seq_lib/uart_csr_vseq.sv
+++ b/hw/ip/uart/dv/env/seq_lib/uart_common_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class uart_csr_vseq extends uart_base_vseq;
- `uvm_object_utils(uart_csr_vseq)
+class uart_common_vseq extends uart_base_vseq;
+ `uvm_object_utils(uart_common_vseq)
constraint num_trans_c {
num_trans inside {[1:2]};
@@ -11,7 +11,7 @@
`uvm_object_new
virtual task body();
- run_csr_vseq_wrapper(num_trans);
+ run_common_vseq_wrapper(num_trans);
endtask : body
diff --git a/hw/ip/uart/dv/env/seq_lib/uart_intr_testmode_vseq.sv b/hw/ip/uart/dv/env/seq_lib/uart_intr_testmode_vseq.sv
deleted file mode 100644
index a6715cf..0000000
--- a/hw/ip/uart/dv/env/seq_lib/uart_intr_testmode_vseq.sv
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-class uart_intr_testmode_vseq extends uart_base_vseq;
- `uvm_object_utils(uart_intr_testmode_vseq)
-
- constraint num_trans_c {
- num_trans inside {[1:5]};
- }
-
- `uvm_object_new
-
- task body();
- bit [TL_DW-1:0] dut_intr_state;
- bit [7:0] exp_intr_state;
- bit [7:0] exp_intr_pin;
-
- for (int i = 1; i <= num_trans; i++) begin
- `DV_CHECK_RANDOMIZE_FATAL(this)
- uart_init();
-
- `DV_CHECK_STD_RANDOMIZE_FATAL(exp_intr_state)
- csr_wr(.csr(ral.intr_test), .value(exp_intr_state));
- csr_rd(.ptr(ral.intr_state), .value(dut_intr_state));
-
- exp_intr_pin = exp_intr_state & en_intr;
- `DV_CHECK_EQ(dut_intr_state, exp_intr_state)
- `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[7:0], exp_intr_pin, $sformatf(
- "exp_intr_state: %0h, en_intr: %0h", exp_intr_state, en_intr))
-
- csr_wr(.csr(ral.intr_state), .value('hff));
- `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW)
- end
- endtask : body
-
-endclass : uart_intr_testmode_vseq
diff --git a/hw/ip/uart/dv/env/seq_lib/uart_vseq_list.sv b/hw/ip/uart/dv/env/seq_lib/uart_vseq_list.sv
index eee7a3a..c39f9b9 100644
--- a/hw/ip/uart/dv/env/seq_lib/uart_vseq_list.sv
+++ b/hw/ip/uart/dv/env/seq_lib/uart_vseq_list.sv
@@ -5,11 +5,10 @@
`include "uart_base_vseq.sv"
`include "uart_tx_rx_vseq.sv"
`include "uart_sanity_vseq.sv"
-`include "uart_csr_vseq.sv"
+`include "uart_common_vseq.sv"
`include "uart_fifo_full_vseq.sv"
`include "uart_fifo_overflow_vseq.sv"
`include "uart_fifo_reset_vseq.sv"
-`include "uart_intr_testmode_vseq.sv"
`include "uart_rx_oversample_vseq.sv"
`include "uart_intr_vseq.sv"
`include "uart_noise_filter_vseq.sv"
diff --git a/util/uvmdvgen/Makefile.tpl b/util/uvmdvgen/Makefile.tpl
index cd358c8..a218f4b 100644
--- a/util/uvmdvgen/Makefile.tpl
+++ b/util/uvmdvgen/Makefile.tpl
@@ -33,33 +33,38 @@
UVM_TEST_SEQ = ${name}_sanity_vseq
endif
+ifeq (${'$'}{TEST_NAME},${name}_intr_test)
+ UVM_TEST_SEQ = ${name}_common_vseq
+ RUN_OPTS += +run_intr_test
+endif
+
ifeq (${'$'}{TEST_NAME},${name}_csr_hw_reset)
- UVM_TEST_SEQ = ${name}_csr_vseq
+ UVM_TEST_SEQ = ${name}_common_vseq
RUN_OPTS += +csr_hw_reset
RUN_OPTS += +en_scb=0
endif
ifeq (${'$'}{TEST_NAME},${name}_csr_rw)
- UVM_TEST_SEQ = ${name}_csr_vseq
+ UVM_TEST_SEQ = ${name}_common_vseq
RUN_OPTS += +csr_rw
RUN_OPTS += +en_scb=0
endif
ifeq (${'$'}{TEST_NAME},${name}_csr_bit_bash)
- UVM_TEST_SEQ = ${name}_csr_vseq
+ UVM_TEST_SEQ = ${name}_common_vseq
RUN_OPTS += +csr_bit_bash
RUN_OPTS += +en_scb=0
endif
ifeq (${'$'}{TEST_NAME},${name}_csr_aliasing)
- UVM_TEST_SEQ = ${name}_csr_vseq
+ UVM_TEST_SEQ = ${name}_common_vseq
RUN_OPTS += +csr_aliasing
RUN_OPTS += +en_scb=0
endif
${'# TODO: remove this test if there are no memories in the DUT'}
ifeq (${'$'}{TEST_NAME},${name}_mem_walk)
- UVM_TEST_SEQ = ${name}_csr_vseq
+ UVM_TEST_SEQ = ${name}_common_vseq
RUN_OPTS += +csr_mem_walk
RUN_OPTS += +en_scb=0
endif
diff --git a/util/uvmdvgen/csr_vseq.sv.tpl b/util/uvmdvgen/csr_vseq.sv.tpl
index bbdce09..7eb0eae 100644
--- a/util/uvmdvgen/csr_vseq.sv.tpl
+++ b/util/uvmdvgen/csr_vseq.sv.tpl
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class ${name}_csr_vseq extends ${name}_base_vseq;
- `uvm_object_utils(${name}_csr_vseq)
+class ${name}_common_vseq extends ${name}_base_vseq;
+ `uvm_object_utils(${name}_common_vseq)
constraint num_trans_c {
num_trans inside {[1:2]};
@@ -11,7 +11,7 @@
`uvm_object_new
virtual task body();
- run_csr_vseq_wrapper(num_trans);
+ run_common_vseq_wrapper(num_trans);
endtask : body
// function to add csr exclusions of the given type using the csr_excl_item item
diff --git a/util/uvmdvgen/gen_env.py b/util/uvmdvgen/gen_env.py
index a7b2437..577bd17 100644
--- a/util/uvmdvgen/gen_env.py
+++ b/util/uvmdvgen/gen_env.py
@@ -23,7 +23,7 @@
('env', name + '_', 'env', '.core'),
('env/seq_lib', name + '_', 'base_vseq', '.sv'),
('env/seq_lib', name + '_', 'sanity_vseq', '.sv'),
- ('env/seq_lib', name + '_', 'csr_vseq', '.sv'),
+ ('env/seq_lib', name + '_', 'common_vseq', '.sv'),
('env/seq_lib', name + '_', 'vseq_list', '.sv'),
('tb', '', 'tb', '.sv'),
('tb', name + '_', 'bind', '.sv'),
diff --git a/util/uvmdvgen/vseq_list.sv.tpl b/util/uvmdvgen/vseq_list.sv.tpl
index 18a18f9..6e30698 100644
--- a/util/uvmdvgen/vseq_list.sv.tpl
+++ b/util/uvmdvgen/vseq_list.sv.tpl
@@ -4,4 +4,4 @@
`include "${name}_base_vseq.sv"
`include "${name}_sanity_vseq.sv"
-`include "${name}_csr_vseq.sv"
+`include "${name}_common_vseq.sv"
