commit 5cddaf8f6b8f80ac8f3ce320f72e2a90375600bf
author Srikrishna Iyer <sriyer@google.com> Fri Apr 24 14:19:49 2020 -0700
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Wed Sep 30 16:09:45 2020 -0700
tree a7ceae7aecef5488e7c065ca654eb5eb51e5b893
parent ac559a08913a5db2f7b91ea823c84ddb6c89b988

[chip dv] Initial DV documentation

This PR just adds the template DV plan and testplan documents. These
are far from complete. Their contents will be updated in subsequent PRs
in stages.

Signed-off-by: Srikrishna Iyer <sriyer@google.com>

util/build_docs.py

diff --git a/util/build_docs.py b/util/build_docs.py
index ad3659a..1568045 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -96,6 +96,7 @@
         "hw/ip/uart/data/uart_testplan.hjson",
         "hw/ip/usbdev/data/usbdev_testplan.hjson",
         "hw/ip/tlul/data/tlul_testplan.hjson",
+        "hw/top_earlgrey/data/chip_testplan.hjson",
         "hw/top_earlgrey/data/standalone_sw_testplan.hjson",
         "util/dvsim/testplanner/examples/foo_testplan.hjson",
     ],