| From 4dee0573fec79c8b9a38a7e14dc7bf2fabe06551 Mon Sep 17 00:00:00 2001 |
| From: Greg Chadwick <gac@lowrisc.org> |
| Date: Mon, 20 Apr 2020 13:41:51 +0100 |
| Subject: [PATCH 5/7] Update .vmem paths with new naming |
| |
| --- |
| riscv-target/opentitan/device/rv32imc/Makefile.include | 6 +++--- |
| 1 file changed, 3 insertions(+), 3 deletions(-) |
| |
| diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include |
| index d789fe2..b929b69 100644 |
| --- a/riscv-target/opentitan/device/rv32imc/Makefile.include |
| +++ b/riscv-target/opentitan/device/rv32imc/Makefile.include |
| @@ -26,8 +26,8 @@ else |
| # Verilator can be run in parallel mode so alter log output to prepend with |
| # test name, also increase uart_timeout as with parallel runs on CI individual |
| # test execution can take greater than 60 seconds. |
| - PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \ |
| - --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem \ |
| + PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).32.vmem \ |
| + --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.32.vmem \ |
| --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \ |
| --uart_timeout 240 |
| OT_SW_TARGET = sim_verilator |
| @@ -76,4 +76,4 @@ COMPILE_TARGET += \ |
| $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \ |
| $$(RISCV_NM) $$(@) > $$(@).nm; \ |
| $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \ |
| - srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem |
| + srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).32.vmem -vmem |
| -- |
| 2.26.0 |
| |
