Update riscv_compliance to riscv/riscv-compliance@5a978cf - Switched from VMEM to ELF files when loading the verilator simulation - Non-functional: Restructured the patch queue to be topic-oriented, not a timeline. Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch index f7ae273..5b55077 100644 --- a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch +++ b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
@@ -1,7 +1,7 @@ -From 5fb77a9e75207f4a35d0b1c4ad9f0ce7faba3814 Mon Sep 17 00:00:00 2001 +From 12ff08f286e3045323375877017286afc54dcf39 Mon Sep 17 00:00:00 2001 From: Greg Chadwick <gac@lowrisc.org> Date: Wed, 15 Apr 2020 15:45:31 +0100 -Subject: [PATCH 1/7] Add configurable trap alignment and entry point to p +Subject: [PATCH 1/3] Add configurable trap alignment and entry point to p test-env --- @@ -95,5 +95,5 @@ # increment return address csrr x30, mepc -- -2.26.0 +2.26.2
diff --git a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch index 90f3533..ecd567c 100644 --- a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch +++ b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
@@ -1,18 +1,19 @@ -From 0f7688b6a865e38f365bc8584cacbe851b8d806c Mon Sep 17 00:00:00 2001 +From 3cafdf492bf9e29e9349ca44ae448b5d2359cd06 Mon Sep 17 00:00:00 2001 From: Greg Chadwick <gac@lowrisc.org> Date: Wed, 15 Apr 2020 15:44:54 +0100 -Subject: [PATCH 2/7] Add OpenTitan target +Subject: [PATCH 2/3] Add OpenTitan target --- - riscv-target/opentitan/README.md | 144 ++++++++++++++++++ + Makefile | 6 +- + riscv-target/opentitan/README.md | 160 ++++++++++++++++++ riscv-target/opentitan/compliance_io.h | 22 +++ - riscv-target/opentitan/compliance_test.h | 35 +++++ - .../opentitan/device/rv32imc/Makefile.include | 79 ++++++++++ + riscv-target/opentitan/compliance_test.h | 35 ++++ + .../opentitan/device/rv32imc/Makefile.include | 79 +++++++++ .../opentitan/device/rv32imc/isa.yaml | 49 ++++++ riscv-target/opentitan/device/rv32imc/main.c | 39 +++++ .../opentitan/device/rv32imc/platform.yaml | 10 ++ - .../opentitan/device/rv32imc/run_rvc_test.S | 85 +++++++++++ - 8 files changed, 463 insertions(+) + .../opentitan/device/rv32imc/run_rvc_test.S | 85 ++++++++++ + 9 files changed, 484 insertions(+), 1 deletion(-) create mode 100644 riscv-target/opentitan/README.md create mode 100644 riscv-target/opentitan/compliance_io.h create mode 100644 riscv-target/opentitan/compliance_test.h @@ -22,12 +23,33 @@ create mode 100644 riscv-target/opentitan/device/rv32imc/platform.yaml create mode 100644 riscv-target/opentitan/device/rv32imc/run_rvc_test.S +diff --git a/Makefile b/Makefile +index 25557c1..27433ed 100644 +--- a/Makefile ++++ b/Makefile +@@ -50,6 +50,11 @@ else + ifeq ($(RISCV_TARGET),riscvOVPsim) + JOBS ?= -j8 --max-load=4 + endif ++ ifeq ($(RISCV_TARGET),opentitan) ++ ifeq ($(OT_TARGET),verilator) ++ JOBS ?= -j4 ++ endif ++ endif + endif + + default: $(DEFAULT_TARGET) +@@ -90,4 +95,3 @@ help: + @echo "RISCV_ISA='$(RISCV_ISA_OPT)'" + @echo "RISCV_TEST='I-ADD-01'" + @echo "make all_variant // all combinations" +- diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md new file mode 100644 -index 0000000..6823fe2 +index 0000000..71baa3c --- /dev/null +++ b/riscv-target/opentitan/README.md -@@ -0,0 +1,144 @@ +@@ -0,0 +1,160 @@ + +# Overview +The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator. @@ -161,6 +183,22 @@ +$ rm -rf ./work +``` + ++## Parallel runs ++When running against the `verilator` target parallel make jobs are used (via ++passing `-j4` to make internally). Parallel runs can be disabled by passing ++`PARALLEL=0` to the `make` command or the `-j` used can be altered with the ++`JOBS` argument. ++ ++Disable parallel runs: ++```console ++$ make RISCV_ISA=rv32i PARALLEL=0 ++``` ++ ++Use a different `-j` parameter: ++```console ++$ make RISCV_ISA=rv32i JOBS=-j8 ++``` ++ +## Removed/Broken Tests +A small number of tests are not run for OpenTitan riscv_compliance as they fail +due to flaws in the compliance test suite rather than Ibex/OpenTitan itself (see @@ -243,7 +281,7 @@ +#endif diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include new file mode 100644 -index 0000000..d789fe2 +index 0000000..dba8732 --- /dev/null +++ b/riscv-target/opentitan/device/rv32imc/Makefile.include @@ -0,0 +1,79 @@ @@ -275,8 +313,8 @@ + # Verilator can be run in parallel mode so alter log output to prepend with + # test name, also increase uart_timeout as with parallel runs on CI individual + # test execution can take greater than 60 seconds. -+ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \ -+ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem \ ++ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<) \ ++ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf \ + --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \ + --uart_timeout 240 + OT_SW_TARGET = sim_verilator @@ -313,10 +351,11 @@ + -I$(OT_ROOT) \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ -+ $(DEFINES) -T$(LDSCRIPT) $$< \ ++ $(DEFINES) \ ++ -L$(OT_ROOT) -T$(LDSCRIPT) $$< \ + $(OPENTITAN)/main.c \ + $(OPENTITAN)/run_rvc_test.S \ -+ $(OT_ROOT)/sw/device/lib/irq_vectors.S \ ++ $(OT_ROOT)/sw/device/exts/common/ibex_interrupt_vectors.S \ + $(OT_ROOT)/sw/device/exts/common/flash_crt.S \ + -L$(OT_BIN)/sw/device/riscv_compliance_support \ + -l$(COMPLIANCE_LIB) \ @@ -324,8 +363,7 @@ + $$(RISCV_OBJDUMP) -SD $$(@) > $$(@).objdump; \ + $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \ + $$(RISCV_NM) $$(@) > $$(@).nm; \ -+ $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \ -+ srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem ++ $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; diff --git a/riscv-target/opentitan/device/rv32imc/isa.yaml b/riscv-target/opentitan/device/rv32imc/isa.yaml new file mode 100644 index 0000000..c526fec @@ -444,7 +482,7 @@ + address: 0x80000080 # boot address + 0x80 diff --git a/riscv-target/opentitan/device/rv32imc/run_rvc_test.S b/riscv-target/opentitan/device/rv32imc/run_rvc_test.S new file mode 100644 -index 0000000..aef6a23 +index 0000000..1b1b5c7 --- /dev/null +++ b/riscv-target/opentitan/device/rv32imc/run_rvc_test.S @@ -0,0 +1,85 @@ @@ -532,7 +570,7 @@ + lw gp, 8(t0) + + // jump to the handler from the OT library -+ j _vectors_start ++ j crt_interrupt_vector -- -2.26.0 +2.26.2
diff --git a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch index 2674337..d9439cb 100644 --- a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch +++ b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
@@ -1,7 +1,7 @@ -From e7f260fbf73b10b1990aecc7cc57a6952f730c6b Mon Sep 17 00:00:00 2001 +From 869ad7202f4551ae75440b8e34d8aa37f4b3f4cf Mon Sep 17 00:00:00 2001 From: Greg Chadwick <gac@lowrisc.org> Date: Wed, 15 Apr 2020 18:39:08 +0100 -Subject: [PATCH 3/7] Remove tests that do not pass on OpenTitan +Subject: [PATCH 3/3] Remove tests that do not pass on OpenTitan --- riscv-test-suite/rv32i/Makefrag | 7 +++++-- @@ -33,5 +33,5 @@ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) -- -2.26.0 +2.26.2
diff --git a/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch b/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch deleted file mode 100644 index d3ec6ac..0000000 --- a/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch +++ /dev/null
@@ -1,56 +0,0 @@ -From 412f4c81a5952c24c0c5977854f15ce3b87f5ae4 Mon Sep 17 00:00:00 2001 -From: Greg Chadwick <gac@lowrisc.org> -Date: Fri, 17 Apr 2020 15:02:48 +0100 -Subject: [PATCH 4/7] Enable parallel runs - ---- - Makefile | 5 +++++ - riscv-target/opentitan/README.md | 16 ++++++++++++++++ - 2 files changed, 21 insertions(+) - -diff --git a/Makefile b/Makefile -index 25557c1..1a822bd 100644 ---- a/Makefile -+++ b/Makefile -@@ -50,6 +50,11 @@ else - ifeq ($(RISCV_TARGET),riscvOVPsim) - JOBS ?= -j8 --max-load=4 - endif -+ ifeq ($(RISCV_TARGET),opentitan) -+ ifeq ($(OT_TARGET),verilator) -+ JOBS ?= -j4 -+ endif -+ endif - endif - - default: $(DEFAULT_TARGET) -diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md -index 6823fe2..71baa3c 100644 ---- a/riscv-target/opentitan/README.md -+++ b/riscv-target/opentitan/README.md -@@ -131,6 +131,22 @@ $ cd $RISCV_COMPLIANCE_REPO_BASE - $ rm -rf ./work - ``` - -+## Parallel runs -+When running against the `verilator` target parallel make jobs are used (via -+passing `-j4` to make internally). Parallel runs can be disabled by passing -+`PARALLEL=0` to the `make` command or the `-j` used can be altered with the -+`JOBS` argument. -+ -+Disable parallel runs: -+```console -+$ make RISCV_ISA=rv32i PARALLEL=0 -+``` -+ -+Use a different `-j` parameter: -+```console -+$ make RISCV_ISA=rv32i JOBS=-j8 -+``` -+ - ## Removed/Broken Tests - A small number of tests are not run for OpenTitan riscv_compliance as they fail - due to flaws in the compliance test suite rather than Ibex/OpenTitan itself (see --- -2.26.0 -
diff --git a/sw/vendor/patches/riscv_compliance/0005-Update-.vmem-paths-with-new-naming.patch b/sw/vendor/patches/riscv_compliance/0005-Update-.vmem-paths-with-new-naming.patch deleted file mode 100644 index ae05f6b..0000000 --- a/sw/vendor/patches/riscv_compliance/0005-Update-.vmem-paths-with-new-naming.patch +++ /dev/null
@@ -1,33 +0,0 @@ -From 4dee0573fec79c8b9a38a7e14dc7bf2fabe06551 Mon Sep 17 00:00:00 2001 -From: Greg Chadwick <gac@lowrisc.org> -Date: Mon, 20 Apr 2020 13:41:51 +0100 -Subject: [PATCH 5/7] Update .vmem paths with new naming - ---- - riscv-target/opentitan/device/rv32imc/Makefile.include | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include -index d789fe2..b929b69 100644 ---- a/riscv-target/opentitan/device/rv32imc/Makefile.include -+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include -@@ -26,8 +26,8 @@ else - # Verilator can be run in parallel mode so alter log output to prepend with - # test name, also increase uart_timeout as with parallel runs on CI individual - # test execution can take greater than 60 seconds. -- PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \ -- --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem \ -+ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).32.vmem \ -+ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.32.vmem \ - --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \ - --uart_timeout 240 - OT_SW_TARGET = sim_verilator -@@ -76,4 +76,4 @@ COMPILE_TARGET += \ - $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \ - $$(RISCV_NM) $$(@) > $$(@).nm; \ - $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \ -- srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem -+ srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).32.vmem -vmem --- -2.26.0 -
diff --git a/sw/vendor/patches/riscv_compliance/0006-Update-Interrupt-Interrupt-Vector-Location.patch b/sw/vendor/patches/riscv_compliance/0006-Update-Interrupt-Interrupt-Vector-Location.patch deleted file mode 100644 index 3ea2f21..0000000 --- a/sw/vendor/patches/riscv_compliance/0006-Update-Interrupt-Interrupt-Vector-Location.patch +++ /dev/null
@@ -1,37 +0,0 @@ -From 66d8a22f5d67de1c6579cac9b263722d0b6ce00c Mon Sep 17 00:00:00 2001 -From: Sam Elliott <selliott@lowrisc.org> -Date: Fri, 8 May 2020 22:09:03 +0100 -Subject: [PATCH 6/7] Update Interrupt Interrupt Vector Location - -Signed-off-by: Sam Elliott <selliott@lowrisc.org> ---- - riscv-target/opentitan/device/rv32imc/Makefile.include | 2 +- - riscv-target/opentitan/device/rv32imc/run_rvc_test.S | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include -index b929b69..41e410b 100644 ---- a/riscv-target/opentitan/device/rv32imc/Makefile.include -+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include -@@ -67,7 +67,7 @@ COMPILE_TARGET += \ - $(DEFINES) -T$(LDSCRIPT) $$< \ - $(OPENTITAN)/main.c \ - $(OPENTITAN)/run_rvc_test.S \ -- $(OT_ROOT)/sw/device/lib/irq_vectors.S \ -+ $(OT_ROOT)/sw/device/exts/common/ibex_interrupt_vectors.S \ - $(OT_ROOT)/sw/device/exts/common/flash_crt.S \ - -L$(OT_BIN)/sw/device/riscv_compliance_support \ - -l$(COMPLIANCE_LIB) \ -diff --git a/riscv-target/opentitan/device/rv32imc/run_rvc_test.S b/riscv-target/opentitan/device/rv32imc/run_rvc_test.S -index aef6a23..1b1b5c7 100644 ---- a/riscv-target/opentitan/device/rv32imc/run_rvc_test.S -+++ b/riscv-target/opentitan/device/rv32imc/run_rvc_test.S -@@ -82,4 +82,4 @@ mtvec_handler: - lw gp, 8(t0) - - // jump to the handler from the OT library -- j _vectors_start -+ j crt_interrupt_vector --- -2.26.0 -
diff --git a/sw/vendor/patches/riscv_compliance/0007-Add-Include-Path-For-OpenTitan-Linker-Script.patch b/sw/vendor/patches/riscv_compliance/0007-Add-Include-Path-For-OpenTitan-Linker-Script.patch deleted file mode 100644 index 10e05e9..0000000 --- a/sw/vendor/patches/riscv_compliance/0007-Add-Include-Path-For-OpenTitan-Linker-Script.patch +++ /dev/null
@@ -1,26 +0,0 @@ -From d41fc018e9018a44f6a70e52e4f9d4398b4e4659 Mon Sep 17 00:00:00 2001 -From: Sam Elliott <selliott@lowrisc.org> -Date: Mon, 11 May 2020 21:27:04 +0100 -Subject: [PATCH 7/7] Add Include Path For OpenTitan Linker Script - ---- - riscv-target/opentitan/device/rv32imc/Makefile.include | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include -index 41e410b..61dd819 100644 ---- a/riscv-target/opentitan/device/rv32imc/Makefile.include -+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include -@@ -64,7 +64,8 @@ COMPILE_TARGET += \ - -I$(OT_ROOT) \ - -I$(TARGETDIR)/$(RISCV_TARGET)/ \ - -I$(TARGETDIR)/$(RISCV_TARGET)/ \ -- $(DEFINES) -T$(LDSCRIPT) $$< \ -+ $(DEFINES) \ -+ -L$(OT_ROOT) -T$(LDSCRIPT) $$< \ - $(OPENTITAN)/main.c \ - $(OPENTITAN)/run_rvc_test.S \ - $(OT_ROOT)/sw/device/exts/common/ibex_interrupt_vectors.S \ --- -2.26.0 -
diff --git a/sw/vendor/riscv_compliance/Makefile b/sw/vendor/riscv_compliance/Makefile index 1a822bd..27433ed 100644 --- a/sw/vendor/riscv_compliance/Makefile +++ b/sw/vendor/riscv_compliance/Makefile
@@ -95,4 +95,3 @@ @echo "RISCV_ISA='$(RISCV_ISA_OPT)'" @echo "RISCV_TEST='I-ADD-01'" @echo "make all_variant // all combinations" -
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md index 84f3a4a..71baa3c 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
@@ -157,3 +157,4 @@ * I-MISALIGN_JMP-01 * I-MISALIGN_LDST-01 * I-FENCE.I-01 +
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_io.h b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_io.h index d5d88d4..2774158 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_io.h +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_io.h
@@ -1,22 +1,22 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// RISC-V Compliance IO Test Header File - - -#ifndef _COMPLIANCE_IO_H -#define _COMPLIANCE_IO_H - -//----------------------------------------------------------------------- -// RV IO Macros (Non functional) -//----------------------------------------------------------------------- - -#define RVTEST_IO_INIT -#define RVTEST_IO_WRITE_STR(_SP, _STR) -#define RVTEST_IO_CHECK() -#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) -#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) -#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) - -#endif // _COMPLIANCE_IO_H +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// RISC-V Compliance IO Test Header File + + +#ifndef _COMPLIANCE_IO_H +#define _COMPLIANCE_IO_H + +//----------------------------------------------------------------------- +// RV IO Macros (Non functional) +//----------------------------------------------------------------------- + +#define RVTEST_IO_INIT +#define RVTEST_IO_WRITE_STR(_SP, _STR) +#define RVTEST_IO_CHECK() +#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) +#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) +#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#endif // _COMPLIANCE_IO_H
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h index 6a889cf..978d578 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h
@@ -1,35 +1,35 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// RISC-V Compliance Test Header File - -#ifndef _COMPLIANCE_TEST_H -#define _COMPLIANCE_TEST_H - -#include "riscv_test.h" - -//----------------------------------------------------------------------- -// RV Compliance Macros -//----------------------------------------------------------------------- -#define RV_COMPLIANCE_HALT \ - j end_rvc_test; \ - -#define RV_COMPLIANCE_RV32M \ - RVTEST_RV32M \ - - -#define RV_COMPLIANCE_CODE_BEGIN \ - RVTEST_CODE_BEGIN \ - -#define RV_COMPLIANCE_CODE_END \ - RVTEST_CODE_END \ - -#define RV_COMPLIANCE_DATA_BEGIN \ - .section .data; \ - RVTEST_DATA_BEGIN \ - -#define RV_COMPLIANCE_DATA_END \ - RVTEST_DATA_END \ - -#endif +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// RISC-V Compliance Test Header File + +#ifndef _COMPLIANCE_TEST_H +#define _COMPLIANCE_TEST_H + +#include "riscv_test.h" + +//----------------------------------------------------------------------- +// RV Compliance Macros +//----------------------------------------------------------------------- +#define RV_COMPLIANCE_HALT \ + j end_rvc_test; \ + +#define RV_COMPLIANCE_RV32M \ + RVTEST_RV32M \ + + +#define RV_COMPLIANCE_CODE_BEGIN \ + RVTEST_CODE_BEGIN \ + +#define RV_COMPLIANCE_CODE_END \ + RVTEST_CODE_END \ + +#define RV_COMPLIANCE_DATA_BEGIN \ + .section .data; \ + RVTEST_DATA_BEGIN \ + +#define RV_COMPLIANCE_DATA_END \ + RVTEST_DATA_END \ + +#endif
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include index 61dd819..dba8732 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -26,8 +26,8 @@ # Verilator can be run in parallel mode so alter log output to prepend with # test name, also increase uart_timeout as with parallel runs on CI individual # test execution can take greater than 60 seconds. - PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).32.vmem \ - --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.32.vmem \ + PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<) \ + --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf \ --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \ --uart_timeout 240 OT_SW_TARGET = sim_verilator @@ -76,5 +76,4 @@ $$(RISCV_OBJDUMP) -SD $$(@) > $$(@).objdump; \ $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \ $$(RISCV_NM) $$(@) > $$(@).nm; \ - $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \ - srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).32.vmem -vmem + $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin;