[flash_ctrl/tl/dv] Add timeout argument to tl_access methods
Signed-off-by: Eitan Shapira <eitanshapira89@gmail.com>
diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
index b2076f7..a5176f8 100644
--- a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
@@ -173,6 +173,7 @@
virtual task tl_access(input bit [BUS_AW-1:0] addr,
input bit write,
inout bit [BUS_DW-1:0] data,
+ input uint tl_access_timeout_ns = default_spinwait_timeout_ns,
input bit [BUS_DBW-1:0] mask = '1,
input bit check_rsp = 1'b1,
input bit exp_err_rsp = 1'b0,
@@ -184,9 +185,9 @@
tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h,
input tl_intg_err_e tl_intg_err_type = TlIntgErrNone);
bit completed, saw_err;
- tl_access_w_abort(addr, write, data, completed, saw_err, mask, check_rsp, exp_err_rsp, exp_data,
- compare_mask, check_exp_data, blocking, instr_type, tl_sequencer_h,
- tl_intg_err_type);
+ tl_access_w_abort(addr, write, data, completed, saw_err, tl_access_timeout_ns, mask, check_rsp,
+ exp_err_rsp, exp_data, compare_mask, check_exp_data, blocking, instr_type,
+ tl_sequencer_h, tl_intg_err_type);
endtask
// this tl_access can input req_abort_pct (pertentage to enable req abort) and output status for
@@ -197,6 +198,7 @@
inout bit [BUS_DW-1:0] data,
output bit completed,
output bit saw_err,
+ input uint tl_access_timeout_ns = default_spinwait_timeout_ns,
input bit [BUS_DBW-1:0] mask = '1,
input bit check_rsp = 1'b1,
input bit exp_err_rsp = 1'b0,
@@ -211,14 +213,14 @@
cip_tl_seq_item rsp;
if (blocking) begin
- tl_access_sub(addr, write, data, completed, saw_err, rsp, mask, check_rsp,
- exp_err_rsp, exp_data, compare_mask, check_exp_data, req_abort_pct,
+ tl_access_sub(addr, write, data, completed, saw_err, rsp, tl_access_timeout_ns, mask,
+ check_rsp, exp_err_rsp, exp_data, compare_mask, check_exp_data, req_abort_pct,
instr_type, tl_sequencer_h, tl_intg_err_type);
end else begin
fork
- tl_access_sub(addr, write, data, completed, saw_err, rsp, mask, check_rsp,
- exp_err_rsp, exp_data, compare_mask, check_exp_data, req_abort_pct,
- instr_type, tl_sequencer_h, tl_intg_err_type);
+ tl_access_sub(addr, write, data, completed, saw_err, rsp, tl_access_timeout_ns, mask,
+ check_rsp, exp_err_rsp, exp_data, compare_mask, check_exp_data,
+ req_abort_pct, instr_type, tl_sequencer_h, tl_intg_err_type);
join_none
// Add #0 to ensure that this thread starts executing before any subsequent call
#0;
@@ -231,6 +233,7 @@
output bit completed,
output bit saw_err,
output cip_tl_seq_item rsp,
+ input uint tl_access_timeout_ns = default_spinwait_timeout_ns,
input bit [BUS_DBW-1:0] mask = '1,
input bit check_rsp = 1'b1,
input bit exp_err_rsp = 1'b0,
@@ -281,7 +284,9 @@
csr_utils_pkg::decrement_outstanding_access();,
// thread to check timeout
- $sformatf("Timeout waiting tl_access : addr=0x%0h", addr))
+ $sformatf("Timeout waiting tl_access : addr=0x%0h", addr),
+ // Timeout parameter
+ tl_access_timeout_ns)
endtask
// CIP spec indicates all comportable IPs will have the same standardized interrupt csrs. We can
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
index 73ff416..f28e63c 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
@@ -316,14 +316,17 @@
endtask : flash_ctrl_read
// Task to perform a direct Flash read at the specified location
+ // Used timeout is to match the longest waiting timeout possible for the host, which will happen
+ // when the host is waiting for the controller to finish bank-erase
virtual task do_direct_read(
input addr_t addr, input bit [TL_DBW-1:0] mask = get_rand_contiguous_mask(),
input bit blocking = $urandom_range(0, 1), input bit check_rdata = 0,
input data_t exp_rdata = '0, input mubi4_t instr_type = MuBi4False,
output data_4s_t rdata, input bit exp_err_rsp = 1'b0);
- tl_access(.addr(addr), .write(1'b0), .data(rdata), .mask(mask), .blocking(blocking),
- .check_exp_data(check_rdata), .exp_data(exp_rdata), .compare_mask(mask),
- .instr_type(instr_type), .exp_err_rsp(exp_err_rsp),
+ tl_access(.addr(addr), .write(1'b0), .data(rdata),
+ .tl_access_timeout_ns(cfg.seq_cfg.erase_timeout_ns), .mask(mask),
+ .blocking(blocking), .check_exp_data(check_rdata), .exp_data(exp_rdata),
+ .compare_mask(mask), .instr_type(instr_type), .exp_err_rsp(exp_err_rsp),
.tl_sequencer_h(p_sequencer.tl_sequencer_hs[cfg.flash_ral_name]));
endtask : do_direct_read
diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv b/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv
index 6814349..11ebdba 100644
--- a/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv
+++ b/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv
@@ -7,6 +7,7 @@
import uvm_pkg::*;
import top_pkg::*;
import dv_utils_pkg::*;
+ import csr_utils_pkg::*;
import dv_lib_pkg::*;
import dv_base_reg_pkg::*;
import tl_agent_pkg::*;
diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv
index 0d57069..3827287 100644
--- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv
+++ b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv
@@ -24,6 +24,7 @@
inout bit [BUS_DW-1:0] data,
output bit completed,
output bit saw_err,
+ input uint tl_access_timeout_ns = default_spinwait_timeout_ns,
input bit [BUS_DBW-1:0] mask = '1,
input bit check_rsp = 1'b1,
input bit exp_err_rsp = 1'b0,
@@ -35,9 +36,9 @@
tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h,
input tl_intg_err_e tl_intg_err_type = TlIntgErrNone,
input int req_abort_pct = 0);
- super.tl_access_w_abort(addr, write, data, completed, saw_err, mask, check_rsp, exp_err_rsp,
- exp_data, compare_mask, check_exp_data, blocking, instr_type,
- tl_sequencer_h, tl_intg_err_type, req_abort_pct);
+ super.tl_access_w_abort(addr, write, data, completed, saw_err, tl_access_timeout_ns, mask,
+ check_rsp, exp_err_rsp, exp_data, compare_mask, check_exp_data,
+ blocking, instr_type, tl_sequencer_h, tl_intg_err_type, req_abort_pct);
// If we see a write which causes an integrity error AND we've disabled the scoreboard (which
// has its own predictor), we update the predicted value of the STATUS register to be LOCKED.
