[otbn] Initial OTBN implementation skeleton
This commit is the initial OTBN toplevel file, containing
- an 32b wide instruction memory SRAM block (IMEM) of 4 kB,
- a 256b wide data memory SRAM block (DMEM) of 4 kB,
- an interrupt, alert, and register making OTBN accessible as
device from the main bus, allowing Ibex to load IMEM and DMEM, start
the operation on OTBN, and check its status.
The commit also contains a dummy for the OTBN processing core,
`otbn_core.sv`. This file doesn't do anything yet.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/meson.build b/meson.build
index c0cff77..096f037 100644
--- a/meson.build
+++ b/meson.build
@@ -113,6 +113,7 @@
hw_ip_gpio_reg_h = gen_hw_hdr.process('hw/ip/gpio/data/gpio.hjson')
hw_ip_hmac_reg_h = gen_hw_hdr.process('hw/ip/hmac/data/hmac.hjson')
hw_ip_i2c_reg_h = gen_hw_hdr.process('hw/ip/i2c/data/i2c.hjson')
+hw_ip_otbn_reg_h = gen_hw_hdr.process('hw/ip/otbn/data/otbn.hjson')
hw_ip_spi_device_reg_h = gen_hw_hdr.process('hw/ip/spi_device/data/spi_device.hjson')
hw_ip_rv_timer_reg_h = gen_hw_hdr.process('hw/ip/rv_timer/data/rv_timer.hjson')
hw_ip_uart_reg_h = gen_hw_hdr.process('hw/ip/uart/data/uart.hjson')
