[uvmdvgen] Update links in checklist template
* Use relative links when referring to an IP block.
* Update the DV Plan/Testplan links to match existing usage in IP
blocks.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/util/uvmdvgen/checklist.md.tpl b/util/uvmdvgen/checklist.md.tpl
index 3b2f917..371e534 100644
--- a/util/uvmdvgen/checklist.md.tpl
+++ b/util/uvmdvgen/checklist.md.tpl
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "hw/ip/${name}/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
<%text>## Design Checklist</%text>
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Not Started | [${name.upper()} Design Spec]({{<relref "hw/ip/${name}/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Not Started | [${name.upper()} Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Not Started |
RTL | [CLKRST_CONNECTED][] | Not Started |
RTL | [IP_TOP][] | Not Started |
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [${name.upper()} DV Plan]({{<relref "hw/ip/${name}/doc/dv_plan" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [${name.upper()} Testplan]({{<relref "hw/ip/${name}/doc/dv_plan/index.md#testplan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [${name.upper()} DV Plan]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [${name.upper()} Testplan]({{<relref "dv/index.md#testplan" >}})
Testbench | [TB_TOP_CREATED][] | Not Started |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
