commit 5b61c56258a29a56058e44a6edd50b6ed083054d
author Eunchan Kim <eunchan@opentitan.org> Fri Oct 29 16:17:36 2021 +0000
committer Eunchan Kim <eunchan@opentitan.org> Tue Nov 02 15:17:56 2021 +0000
tree 44b7866d732487b66d9440a9e51c2524f531155e
parent 3cb62ec91052a7c493771266bf856532cb0e2d5a

[spi_device] Upload Cmd/Addr FIFO status revision

In previous design, the cmdfifo, addrfifo in the spid_upload module
reports the not empty status. The status bits are connected to the
UPLOAD_STATUS CSR for SW to read and check the status.

The not empty status, however, assert one clock earlier than the actual
`rvalid` signals.

The reason is due to the SRAM read latency. The upload module adopts
SRAM FIFO interface to maintain the cmd, addr FIFOs. When the logic in
SCK domain pushes entries, the pointer is increased. This triggers the
FIFO logic in the bus clock domain fetches data from SRAM.

The pointer crosses the clock boundary. It takes usually two cycles (in
the receiver side). Then, as the read and write pointer in the bus clock
domain has a gap by 1, the FIFO not empty status is raised.

At this time, the logic just sent the read request to the SRAM. The data
is not yet read. The `rvalid` asserts when it receives data from the
SRAM.

So, if the consumer reads data at the same cycle when notempty status is
raised, it reads incorrect data.

This is not a feasible scenario in the real usage as the core takes time
to read the data from the FIFO CSR.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>