[rv_dm dv] Remove old testbench components
This commit removes the old testbench components that are up-to-date in
the newly added testbench.
There are still several defunct testbench pieces which will be removed
subsequently, as progress towards V1 is made.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/ip/rv_dm/dv_bkp/jtag_if.sv b/hw/ip/rv_dm/dv_bkp/jtag_if.sv
deleted file mode 100644
index 5386b14..0000000
--- a/hw/ip/rv_dm/dv_bkp/jtag_if.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-interface jtag_if;
- logic tck ;
- logic trst_n;
- logic tms ;
- logic tdi ;
- logic tdo ;
- logic tdo_oe;
-
- modport tb (
- output tck, trst_n,
- output tms, tdi,
- input tdo, tdo_oe
- );
-
- modport dut (
- input tck, trst_n,
- input tms, tdi,
- output tdo, tdo_oe
- );
-endinterface
diff --git a/hw/ip/rv_dm/dv_bkp/probe.tcl b/hw/ip/rv_dm/dv_bkp/probe.tcl
deleted file mode 100644
index 968eccc..0000000
--- a/hw/ip/rv_dm/dv_bkp/probe.tcl
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-database -shm -open waves.shm -default
-probe -create -shm tb -depth all -all -mem
-run
-exit
diff --git a/hw/ip/rv_dm/dv_bkp/rv_dm_sim.core b/hw/ip/rv_dm/dv_bkp/rv_dm_sim.core
deleted file mode 100644
index 5c76ac0..0000000
--- a/hw/ip/rv_dm/dv_bkp/rv_dm_sim.core
+++ /dev/null
@@ -1,26 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv:rv_dm_sim:0.1"
-description: "RV_DM DV sim target"
-filesets:
- files_rtl:
- depend:
- - lowrisc:ip:rv_dm:0.1
-
- files_dv:
- depend:
- - lowrisc:dv:rv_dm_test
- - lowrisc:dv:rv_dm_sva
- files:
- - tb.sv
- file_type: systemVerilogSource
-
-targets:
- sim:
- toplevel: tb
- filesets:
- - files_rtl
- - files_dv
- default_tool: vcs
diff --git a/hw/ip/rv_dm/dv_bkp/rv_dm_sim_cfg.hjson b/hw/ip/rv_dm/dv_bkp/rv_dm_sim_cfg.hjson
deleted file mode 100644
index 5ed3046..0000000
--- a/hw/ip/rv_dm/dv_bkp/rv_dm_sim_cfg.hjson
+++ /dev/null
@@ -1,62 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-{
- // Name of the sim cfg - typically same as the name of the DUT.
- name: rv_dm
-
- // Top level dut name (sv module).
- dut: rv_dm
-
- // Top level testbench name (sv module).
- tb: tb
-
- // Simulator used to sign off this block
- tool: vcs
-
- // Fusesoc core file used for building the file list.
- fusesoc_core: lowrisc:dv:rv_dm_sim:0.1
-
- // Testplan hjson file.
- // TODO: no testplan currently exists, need to create if DV moves forward
- testplan: "{proj_root}/hw/ip/rv_dm/data/rv_dm_testplan.hjson"
-
- // RAL spec - used to generate the RAL model.
- ral_spec: "{proj_root}/hw/ip/rv_dm/data/rv_dm.hjson"
-
- // Import additional common sim cfg files.
- import_cfgs: [// Project wide common sim cfg file
- "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
- // Common CIP test lists
- "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
- "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
- "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
- "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
- "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
-
- // Add additional tops for simulation.
- sim_tops: ["rv_dm_bind"]
-
- // Default iterations for all tests - each test entry can override this.
- reseed: 50
-
- // Default UVM test and seq class name.
- uvm_test: rv_dm_base_test
- uvm_test_seq: rv_dm_base_vseq
-
- // List of test specifications.
- tests: [
- {
- name: rv_dm_smoke
- uvm_test_seq: rv_dm_smoke_vseq
- }
- ]
-
- // List of regressions.
- regressions: [
- {
- name: smoke
- tests: ["rv_dm_smoke"]
- }
- ]
-}
diff --git a/hw/ip/rv_dm/dv_bkp/sva/rv_dm_bind.sv b/hw/ip/rv_dm/dv_bkp/sva/rv_dm_bind.sv
deleted file mode 100644
index 263f64f..0000000
--- a/hw/ip/rv_dm/dv_bkp/sva/rv_dm_bind.sv
+++ /dev/null
@@ -1,25 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module rv_dm_bind;
-
- bind rv_dm tlul_assert #(
- .EndpointType("Device")
- ) tlul_assert_device (
- .clk_i,
- .rst_ni,
- .h2d (regs_tl_d_i),
- .d2h (regs_tl_d_o)
- );
-
- bind rv_dm tlul_assert #(
- .EndpointType("Host")
- ) tlul_assert_host (
- .clk_i,
- .rst_ni,
- .h2d (sba_tl_h_o),
- .d2h (sba_tl_h_i)
- );
-
-endmodule
diff --git a/hw/ip/rv_dm/dv_bkp/sva/rv_dm_sva.core b/hw/ip/rv_dm/dv_bkp/sva/rv_dm_sva.core
deleted file mode 100644
index c361c3d..0000000
--- a/hw/ip/rv_dm/dv_bkp/sva/rv_dm_sva.core
+++ /dev/null
@@ -1,29 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv:rv_dm_sva:0.1"
-description: "RV_DM assertion modules and bind file."
-filesets:
- files_dv:
- depend:
- - lowrisc:tlul:headers
- files:
- - rv_dm_bind.sv
- file_type: systemVerilogSource
-
- files_formal:
- depend:
- - lowrisc:ip:rv_dm
-
-targets:
- default: &default_target
- filesets:
- - files_dv
-
- formal:
- <<: *default_target
- filesets:
- - files_formal
- - files_dv
- toplevel: rv_dm
diff --git a/hw/ip/rv_dm/dv_bkp/tb.sv b/hw/ip/rv_dm/dv_bkp/tb.sv
deleted file mode 100644
index 8dbcbfb..0000000
--- a/hw/ip/rv_dm/dv_bkp/tb.sv
+++ /dev/null
@@ -1,63 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-module tb;
- // dep packages
- import uvm_pkg::*;
- import dv_utils_pkg::*;
- import rv_dm_params_pkg::*;
- import rv_dm_env_pkg::*;
- import rv_dm_test_pkg::*;
-
- // macro includes
- `include "uvm_macros.svh"
- `include "dv_macros.svh"
-
- wire clk, rst_n;
- wire jtag_tdo_oe;
-
- // interfaces
- clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
- jtag_if jtag_if();
- tl_if tl_host_if(.clk(clk), .rst_n(rst_n));
- tl_if tl_device_if(.clk(clk), .rst_n(rst_n));
- rv_dm_if rv_dm_if();
-
- // dut
- rv_dm #(
- .NrHarts (rv_dm_params_pkg::NR_HARTS),
- .IdcodeValue (rv_dm_params_pkg::JTAG_ID_CODE)
- ) dut (
- .clk_i (clk ),
- .rst_ni (rst_n ),
-
- .testmode_i (rv_dm_if.testmode ),
- .ndmreset_o (rv_dm_if.ndmreset ),
- .dmactive_o (rv_dm_if.dmactive ),
- .debug_req_o (rv_dm_if.debug_req ),
- .unavailable_i(rv_dm_if.unavailable ),
-
- .tl_d_i (tl_device_if.h2d ),
- .tl_d_o (tl_device_if.d2h ),
-
- .tl_h_o (tl_host_if.h2d ),
- .tl_h_i (tl_host_if.d2h ),
-
- .jtag_req_i ({jtag_if.tck, jtag_if.tms, jtag_if.trst_n, jtag_if.tdi}),
- .jtag_rsp_o ({jtag_if.tdo, jtag_tdo_oe})
- );
-
- initial begin
- // drive clk and rst_n from clk_if
- clk_rst_if.set_active();
- uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
- uvm_config_db#(virtual rv_dm_if)::set(null, "*.env*", "rv_dm_vif", rv_dm_if);
- uvm_config_db#(virtual jtag_if)::set(null, "*.env.m_jtag_agent*", "vif", jtag_if);
- uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_host_agent*", "vif", tl_host_if);
- uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_device_agent*", "vif", tl_device_if);
- $timeformat(-12, 0, " ps", 12);
- run_test();
- end
-
-endmodule
diff --git a/hw/ip/rv_dm/dv_bkp/tests/rv_dm_base_test.sv b/hw/ip/rv_dm/dv_bkp/tests/rv_dm_base_test.sv
deleted file mode 100644
index 2c1aa0e..0000000
--- a/hw/ip/rv_dm/dv_bkp/tests/rv_dm_base_test.sv
+++ /dev/null
@@ -1,20 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-class rv_dm_base_test extends dv_base_test #(
- .ENV_T(rv_dm_env),
- .CFG_T(rv_dm_env_cfg)
- );
- `uvm_component_utils(rv_dm_base_test)
- `uvm_component_new
-
- // the base class dv_base_test creates the following instances:
- // rv_dm_env_cfg: cfg
- // rv_dm_env: env
-
- // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
- // the run_phase; as such, nothing more needs to be done
-
-endclass : rv_dm_base_test
-
diff --git a/hw/ip/rv_dm/dv_bkp/tests/rv_dm_test.core b/hw/ip/rv_dm/dv_bkp/tests/rv_dm_test.core
deleted file mode 100644
index bb7af2a..0000000
--- a/hw/ip/rv_dm/dv_bkp/tests/rv_dm_test.core
+++ /dev/null
@@ -1,19 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:dv:rv_dm_test:0.1"
-description: "RV_DM DV UVM test"
-filesets:
- files_dv:
- depend:
- - lowrisc:dv:rv_dm_env
- files:
- - rv_dm_test_pkg.sv
- - rv_dm_base_test.sv: {is_include_file: true}
- file_type: systemVerilogSource
-
-targets:
- default:
- filesets:
- - files_dv
diff --git a/hw/ip/rv_dm/dv_bkp/tests/rv_dm_test_pkg.sv b/hw/ip/rv_dm/dv_bkp/tests/rv_dm_test_pkg.sv
deleted file mode 100644
index 314cf01..0000000
--- a/hw/ip/rv_dm/dv_bkp/tests/rv_dm_test_pkg.sv
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-package rv_dm_test_pkg;
- // dep packages
- import uvm_pkg::*;
- import dv_lib_pkg::*;
- import rv_dm_env_pkg::*;
-
- // macro includes
- `include "uvm_macros.svh"
- `include "dv_macros.svh"
-
- // local types
-
- // functions
-
- // package sources
- `include "rv_dm_base_test.sv"
-
-endpackage
