commit 58a5d085bb07535b7efc233321981224c9953b9e
author Timothy Chen <timothytim@google.com> Fri Apr 10 14:18:28 2020 -0700
committer tjaychen <timothytim@google.com> Mon Apr 13 21:03:23 2020 -0700
tree fffd20cd7581093ba1117fc731069914e432afdc
parent 243438344c65692ab85fd31a670d791b687e1366

[pwrmgr] Edits for nits

Larger changes coming for cdc and others

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/pwrmgr/rtl/pwrmgr.sv

diff --git a/hw/ip/pwrmgr/rtl/pwrmgr.sv b/hw/ip/pwrmgr/rtl/pwrmgr.sv
index 1bc1a5e..26b210f 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr.sv
@@ -112,7 +112,7 @@
     .devmode_i  (1'b1)
   );
 
-  // whenever low power entry begins, clearn the hint
+  // whenever low power entry begins, wipe the hint
   assign hw2reg.control.low_power_hint.d = 1'b0;
   assign hw2reg.control.low_power_hint.de = low_power_entry;
 
@@ -212,7 +212,7 @@
   // clock domains see it.  This creates redundant syncing but keeps the time
   // scale approximately the same across all domains.
   //
-  // This also implies that these signals must be AT least 1 clk_slow pulse long
+  // This also implies that these signals must be at least 1 clk_slow pulse long
 
   prim_flop_2sync # (
     .Width(HwRstReqs + WakeUpPeris)

hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv

diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
index f2839f3..1db70ea 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
@@ -108,6 +108,10 @@
   };
 
   // peripherals to pwrmgr
+  // TODO, switch this to two logic arrays once the option to support
+  // logic during intermodule.py is in.
+  // Structs are used for now since these happen to support dangling port
+  // defaults.
   typedef struct packed {
     logic [WakeUpPeris-1:0] wakeups;
     logic [HwRstReqs-1:0] rstreqs;