[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 66e0b9b..3845514 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -380,6 +380,19 @@
top_signame: alert_handler_esc_rx
index: 0
}
+ {
+ struct: crashdump
+ type: uni
+ name: crashdump
+ act: req
+ package: rv_core_ibex_pkg
+ inst_name: rv_core_ibex
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: rv_core_ibex_crashdump
+ index: -1
+ }
]
}
]
@@ -2408,6 +2421,18 @@
index: -1
}
{
+ struct: crashdump
+ type: uni
+ name: cpu_dump
+ act: rcv
+ package: rv_core_ibex_pkg
+ inst_name: rstmgr
+ width: 1
+ default: ""
+ top_signame: rv_core_ibex_crashdump
+ index: -1
+ }
+ {
struct: rstmgr_ast_out
type: uni
name: resets_ast
@@ -5228,6 +5253,10 @@
[
lc_ctrl.pwr_lc
]
+ rv_core_ibex.crashdump:
+ [
+ rstmgr.cpu_dump
+ ]
otp_ctrl.otp_keymgr_key:
[
keymgr.otp_key
@@ -9142,6 +9171,18 @@
index: -1
}
{
+ struct: crashdump
+ type: uni
+ name: cpu_dump
+ act: rcv
+ package: rv_core_ibex_pkg
+ inst_name: rstmgr
+ width: 1
+ default: ""
+ top_signame: rv_core_ibex_crashdump
+ index: -1
+ }
+ {
struct: rstmgr_ast_out
type: uni
name: resets_ast
@@ -10605,6 +10646,19 @@
top_signame: alert_handler_esc_rx
index: 0
}
+ {
+ struct: crashdump
+ type: uni
+ name: crashdump
+ act: req
+ package: rv_core_ibex_pkg
+ inst_name: rv_core_ibex
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: rv_core_ibex_crashdump
+ index: -1
+ }
]
external:
[
@@ -11010,6 +11064,14 @@
default: ""
}
{
+ package: rv_core_ibex_pkg
+ struct: crashdump
+ signame: rv_core_ibex_crashdump
+ width: 1
+ type: uni
+ default: ""
+ }
+ {
package: otp_ctrl_pkg
struct: otp_keymgr_key
signame: otp_ctrl_otp_keymgr_key
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
index 7ed3da6..68d0689 100644
--- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
+++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -95,6 +95,13 @@
package: "alert_pkg",
},
+ { struct: "crashdump",
+ type: "uni",
+ name: "cpu_dump",
+ act: "rcv",
+ package: "rv_core_ibex_pkg",
+ },
+
// Exported resets
{ struct: "rstmgr_ast_out",
type: "uni",
@@ -204,7 +211,7 @@
{ name: "ALERT_INFO",
desc: '''
Alert dump information prior to last reset.
- Which value read is controlled by the ALERT_INFO_CTRL register.
+ Which value read is controlled by the !ALERT_INFO_CTRL register.
''',
swaccess: "ro",
hwaccess: "hwo",
@@ -213,13 +220,80 @@
{ bits: "31:0",
name: "VALUE",
desc: '''
- The current 32-bit value of alert crash dump.
+ The current 32-bit value of crash dump.
'''
resval: "0",
},
]
},
+ { name: "CPU_INFO_CTRL",
+ desc: '''
+ Cpu info dump controls.
+ ''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ hwaccess: "hrw",
+ desc: '''
+ Enable cpu dump to capture new information.
+ This field is automatically set to 0 upon system reset (even if rstmgr is not reset).
+ '''
+ resval: "0"
+ },
+ { bits: "4+IdxWidth-1:4",
+ name: "INDEX",
+ desc: '''
+ Controls which 32-bit value to read.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ { name: "CPU_INFO_ATTR",
+ desc: '''
+ Cpu info dump attributes.
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "IdxWidth-1:0",
+ name: "CNT_AVAIL",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ desc: '''
+ The number of 32-bit values contained in the cpu info dump.
+ '''
+ resval: "0",
+ tags: [// This field only reflects the status of the design, thus the
+ // default value is likely to change and not remain 0
+ "excl:CsrAllTests:CsrExclCheck"]
+ },
+ ]
+ },
+
+ { name: "CPU_INFO",
+ desc: '''
+ Cpu dump information prior to last reset.
+ Which value read is controlled by the !CPU_INFO_CTRL register.
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "VALUE",
+ desc: '''
+ The current 32-bit value of crash dump.
+ '''
+ resval: "0",
+ },
+ ]
+ },
# Templated registers for software control
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index a890f3f..7fa9c33 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -9,8 +9,6 @@
// SPDX-License-Identifier: Apache-2.0
//
// This module is the overall reset manager wrapper
-// TODO: This module is only a draft implementation that covers most of the rstmgr
-// functoinality but is incomplete
`include "prim_assert.sv"
@@ -43,6 +41,9 @@
// Interface to alert handler
input alert_pkg::alert_crashdump_t alert_dump_i,
+ // Interface to cpu crash dump
+ input rv_core_ibex_pkg::crashdump_t cpu_dump_i,
+
// dft bypass
input scan_rst_ni,
input scanmode_i,
@@ -562,6 +563,43 @@
assign hw2reg.reset_info.hw_req.d = pwr_i.rstreqs | reg2hw.reset_info.hw_req.q;
assign hw2reg.reset_info.hw_req.de = rst_hw_req;
+ ////////////////////////////////////////////////////
+ // Crash info capture //
+ ////////////////////////////////////////////////////
+
+ logic dump_capture;
+ assign dump_capture = rst_hw_req | rst_ndm | rst_low_power;
+
+ rstmgr_crash_info #(
+ .CrashDumpWidth($bits(alert_pkg::alert_crashdump_t))
+ ) u_alert_info (
+ .clk_i,
+ .rst_ni,
+ .dump_i(alert_dump_i),
+ .dump_capture_i(dump_capture & reg2hw.alert_info_ctrl.en.q),
+ .slot_sel_i(reg2hw.alert_info_ctrl.index.q),
+ .slots_cnt_o(hw2reg.alert_info_attr.d),
+ .slot_o(hw2reg.alert_info.d)
+ );
+
+ rstmgr_crash_info #(
+ .CrashDumpWidth($bits(rv_core_ibex_pkg::crashdump_t))
+ ) u_cpu_info (
+ .clk_i,
+ .rst_ni,
+ .dump_i(cpu_dump_i),
+ .dump_capture_i(dump_capture & reg2hw.cpu_info_ctrl.en.q),
+ .slot_sel_i(reg2hw.cpu_info_ctrl.index.q),
+ .slots_cnt_o(hw2reg.cpu_info_attr.d),
+ .slot_o(hw2reg.cpu_info.d)
+ );
+
+ // once dump is captured, no more information is captured until
+ // re-eanbled by software.
+ assign hw2reg.alert_info_ctrl.en.d = 1'b0;
+ assign hw2reg.alert_info_ctrl.en.de = dump_capture;
+ assign hw2reg.cpu_info_ctrl.en.d = 1'b0;
+ assign hw2reg.cpu_info_ctrl.en.de = dump_capture;
////////////////////////////////////////////////////
// Exported resets //
@@ -570,60 +608,13 @@
assign resets_ast_o.rst_ast_usbdev_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_usbdev_usb_n = resets_o.rst_usb_n;
- ////////////////////////////////////////////////////
- // Crash info capture //
- ////////////////////////////////////////////////////
- localparam int CrashRemainder = $bits(alert_pkg::alert_crashdump_t) % RdWidth > 0 ? 1 : 0;
- localparam int CrashStoreSlot = $bits(alert_pkg::alert_crashdump_t) / RdWidth +
- CrashRemainder;
- localparam int TotalWidth = CrashStoreSlot * RdWidth;
- localparam int SlotCntWidth = $clog2(CrashStoreSlot);
- logic dump_capture;
- logic [2**SlotCntWidth-1:0][RdWidth-1:0] slots;
- logic [CrashStoreSlot-1:0][RdWidth-1:0] slots_q;
-
- // capture on any legal reset request
- assign dump_capture = reg2hw.alert_info_ctrl.en.q &
- (rst_hw_req | rst_ndm | rst_low_power);
-
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
- slots_q <= '0;
- end else if (dump_capture) begin
- slots_q <= TotalWidth'(alert_dump_i);
- end
- end
-
- always_comb begin
- slots = '0;
- slots[CrashStoreSlot-1:0] = slots_q;
- end
-
- // once dump is captured, no more information is captured until
- // re-eanbled by software.
- assign hw2reg.alert_info_ctrl.en.d = 1'b0;
- assign hw2reg.alert_info_ctrl.en.de = dump_capture;
-
- // number of segments to read
- assign hw2reg.alert_info_attr.d = CrashStoreSlot;
-
- // the actual dump data
- assign hw2reg.alert_info.d = slots[reg2hw.alert_info_ctrl.index.q[SlotCntWidth-1:0]];
-
- if (SlotCntWidth < IdxWidth) begin : gen_tieoffs
- logic [IdxWidth-SlotCntWidth-1:0] unused_idx;
- assign unused_idx = reg2hw.alert_info_ctrl.index.q[IdxWidth-1:SlotCntWidth];
- end
////////////////////////////////////////////////////
// Assertions //
////////////////////////////////////////////////////
- // Make sure the crash dump isn't excessively large
- `ASSERT_INIT(CntWidth_A, SlotCntWidth <= IdxWidth)
-
// when upstream resets, downstream must also reset
// output known asserts
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
index 53ebd66..23e3068 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
@@ -31,6 +31,15 @@
} rstmgr_reg2hw_alert_info_ctrl_reg_t;
typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } index;
+ } rstmgr_reg2hw_cpu_info_ctrl_reg_t;
+
+ typedef struct packed {
logic q;
} rstmgr_reg2hw_sw_rst_regen_mreg_t;
@@ -71,6 +80,21 @@
} rstmgr_hw2reg_alert_info_reg_t;
typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } en;
+ } rstmgr_hw2reg_cpu_info_ctrl_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ } rstmgr_hw2reg_cpu_info_attr_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } rstmgr_hw2reg_cpu_info_reg_t;
+
+ typedef struct packed {
logic d;
} rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t;
@@ -79,8 +103,9 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- rstmgr_reg2hw_reset_info_reg_t reset_info; // [12:11]
- rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [10:6]
+ rstmgr_reg2hw_reset_info_reg_t reset_info; // [17:16]
+ rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [15:11]
+ rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [10:6]
rstmgr_reg2hw_sw_rst_regen_mreg_t [1:0] sw_rst_regen; // [5:4]
rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [3:0]
} rstmgr_reg2hw_t;
@@ -89,20 +114,26 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- rstmgr_hw2reg_reset_info_reg_t reset_info; // [46:40]
- rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [39:38]
- rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [37:34]
- rstmgr_hw2reg_alert_info_reg_t alert_info; // [33:2]
+ rstmgr_hw2reg_reset_info_reg_t reset_info; // [84:78]
+ rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [77:76]
+ rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [75:72]
+ rstmgr_hw2reg_alert_info_reg_t alert_info; // [71:40]
+ rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [39:38]
+ rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [37:34]
+ rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [33:2]
rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [1:0]
} rstmgr_hw2reg_t;
// Register Address
- parameter logic [4:0] RSTMGR_RESET_INFO_OFFSET = 5'h 0;
- parameter logic [4:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 5'h 4;
- parameter logic [4:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 5'h 8;
- parameter logic [4:0] RSTMGR_ALERT_INFO_OFFSET = 5'h c;
- parameter logic [4:0] RSTMGR_SW_RST_REGEN_OFFSET = 5'h 10;
- parameter logic [4:0] RSTMGR_SW_RST_CTRL_N_OFFSET = 5'h 14;
+ parameter logic [5:0] RSTMGR_RESET_INFO_OFFSET = 6'h 0;
+ parameter logic [5:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 6'h 4;
+ parameter logic [5:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 6'h 8;
+ parameter logic [5:0] RSTMGR_ALERT_INFO_OFFSET = 6'h c;
+ parameter logic [5:0] RSTMGR_CPU_INFO_CTRL_OFFSET = 6'h 10;
+ parameter logic [5:0] RSTMGR_CPU_INFO_ATTR_OFFSET = 6'h 14;
+ parameter logic [5:0] RSTMGR_CPU_INFO_OFFSET = 6'h 18;
+ parameter logic [5:0] RSTMGR_SW_RST_REGEN_OFFSET = 6'h 1c;
+ parameter logic [5:0] RSTMGR_SW_RST_CTRL_N_OFFSET = 6'h 20;
// Register Index
@@ -111,18 +142,24 @@
RSTMGR_ALERT_INFO_CTRL,
RSTMGR_ALERT_INFO_ATTR,
RSTMGR_ALERT_INFO,
+ RSTMGR_CPU_INFO_CTRL,
+ RSTMGR_CPU_INFO_ATTR,
+ RSTMGR_CPU_INFO,
RSTMGR_SW_RST_REGEN,
RSTMGR_SW_RST_CTRL_N
} rstmgr_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] RSTMGR_PERMIT [6] = '{
+ parameter logic [3:0] RSTMGR_PERMIT [9] = '{
4'b 0001, // index[0] RSTMGR_RESET_INFO
4'b 0001, // index[1] RSTMGR_ALERT_INFO_CTRL
4'b 0001, // index[2] RSTMGR_ALERT_INFO_ATTR
4'b 1111, // index[3] RSTMGR_ALERT_INFO
- 4'b 0001, // index[4] RSTMGR_SW_RST_REGEN
- 4'b 0001 // index[5] RSTMGR_SW_RST_CTRL_N
+ 4'b 0001, // index[4] RSTMGR_CPU_INFO_CTRL
+ 4'b 0001, // index[5] RSTMGR_CPU_INFO_ATTR
+ 4'b 1111, // index[6] RSTMGR_CPU_INFO
+ 4'b 0001, // index[7] RSTMGR_SW_RST_REGEN
+ 4'b 0001 // index[8] RSTMGR_SW_RST_CTRL_N
};
endpackage
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
index b972605..e9e673d 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -23,7 +23,7 @@
import rstmgr_reg_pkg::* ;
- localparam int AW = 5;
+ localparam int AW = 6;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
@@ -93,6 +93,16 @@
logic alert_info_attr_re;
logic [31:0] alert_info_qs;
logic alert_info_re;
+ logic cpu_info_ctrl_en_qs;
+ logic cpu_info_ctrl_en_wd;
+ logic cpu_info_ctrl_en_we;
+ logic [3:0] cpu_info_ctrl_index_qs;
+ logic [3:0] cpu_info_ctrl_index_wd;
+ logic cpu_info_ctrl_index_we;
+ logic [3:0] cpu_info_attr_qs;
+ logic cpu_info_attr_re;
+ logic [31:0] cpu_info_qs;
+ logic cpu_info_re;
logic sw_rst_regen_en_0_qs;
logic sw_rst_regen_en_0_wd;
logic sw_rst_regen_en_0_we;
@@ -301,6 +311,92 @@
);
+ // R[cpu_info_ctrl]: V(False)
+
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_cpu_info_ctrl_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (cpu_info_ctrl_en_we),
+ .wd (cpu_info_ctrl_en_wd),
+
+ // from internal hardware
+ .de (hw2reg.cpu_info_ctrl.en.de),
+ .d (hw2reg.cpu_info_ctrl.en.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.cpu_info_ctrl.en.q ),
+
+ // to register interface (read)
+ .qs (cpu_info_ctrl_en_qs)
+ );
+
+
+ // F[index]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SWACCESS("RW"),
+ .RESVAL (4'h0)
+ ) u_cpu_info_ctrl_index (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (cpu_info_ctrl_index_we),
+ .wd (cpu_info_ctrl_index_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.cpu_info_ctrl.index.q ),
+
+ // to register interface (read)
+ .qs (cpu_info_ctrl_index_qs)
+ );
+
+
+ // R[cpu_info_attr]: V(True)
+
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_cpu_info_attr (
+ .re (cpu_info_attr_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.cpu_info_attr.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (cpu_info_attr_qs)
+ );
+
+
+ // R[cpu_info]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_cpu_info (
+ .re (cpu_info_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.cpu_info.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (cpu_info_qs)
+ );
+
+
// Subregister 0 of Multireg sw_rst_regen
// R[sw_rst_regen]: V(False)
@@ -395,15 +491,18 @@
- logic [5:0] addr_hit;
+ logic [8:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[0] = (reg_addr == RSTMGR_RESET_INFO_OFFSET);
addr_hit[1] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET);
addr_hit[2] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET);
addr_hit[3] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET);
- addr_hit[4] = (reg_addr == RSTMGR_SW_RST_REGEN_OFFSET);
- addr_hit[5] = (reg_addr == RSTMGR_SW_RST_CTRL_N_OFFSET);
+ addr_hit[4] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET);
+ addr_hit[5] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET);
+ addr_hit[6] = (reg_addr == RSTMGR_CPU_INFO_OFFSET);
+ addr_hit[7] = (reg_addr == RSTMGR_SW_RST_REGEN_OFFSET);
+ addr_hit[8] = (reg_addr == RSTMGR_SW_RST_CTRL_N_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -417,6 +516,9 @@
if (addr_hit[3] && reg_we && (RSTMGR_PERMIT[3] != (RSTMGR_PERMIT[3] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[4] && reg_we && (RSTMGR_PERMIT[4] != (RSTMGR_PERMIT[4] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[5] && reg_we && (RSTMGR_PERMIT[5] != (RSTMGR_PERMIT[5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[6] && reg_we && (RSTMGR_PERMIT[6] != (RSTMGR_PERMIT[6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[7] && reg_we && (RSTMGR_PERMIT[7] != (RSTMGR_PERMIT[7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[8] && reg_we && (RSTMGR_PERMIT[8] != (RSTMGR_PERMIT[8] & reg_be))) wr_err = 1'b1 ;
end
assign reset_info_por_we = addr_hit[0] & reg_we & ~wr_err;
@@ -441,19 +543,29 @@
assign alert_info_re = addr_hit[3] && reg_re;
- assign sw_rst_regen_en_0_we = addr_hit[4] & reg_we & ~wr_err;
+ assign cpu_info_ctrl_en_we = addr_hit[4] & reg_we & ~wr_err;
+ assign cpu_info_ctrl_en_wd = reg_wdata[0];
+
+ assign cpu_info_ctrl_index_we = addr_hit[4] & reg_we & ~wr_err;
+ assign cpu_info_ctrl_index_wd = reg_wdata[7:4];
+
+ assign cpu_info_attr_re = addr_hit[5] && reg_re;
+
+ assign cpu_info_re = addr_hit[6] && reg_re;
+
+ assign sw_rst_regen_en_0_we = addr_hit[7] & reg_we & ~wr_err;
assign sw_rst_regen_en_0_wd = reg_wdata[0];
- assign sw_rst_regen_en_1_we = addr_hit[4] & reg_we & ~wr_err;
+ assign sw_rst_regen_en_1_we = addr_hit[7] & reg_we & ~wr_err;
assign sw_rst_regen_en_1_wd = reg_wdata[1];
- assign sw_rst_ctrl_n_val_0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign sw_rst_ctrl_n_val_0_we = addr_hit[8] & reg_we & ~wr_err;
assign sw_rst_ctrl_n_val_0_wd = reg_wdata[0];
- assign sw_rst_ctrl_n_val_0_re = addr_hit[5] && reg_re;
+ assign sw_rst_ctrl_n_val_0_re = addr_hit[8] && reg_re;
- assign sw_rst_ctrl_n_val_1_we = addr_hit[5] & reg_we & ~wr_err;
+ assign sw_rst_ctrl_n_val_1_we = addr_hit[8] & reg_we & ~wr_err;
assign sw_rst_ctrl_n_val_1_wd = reg_wdata[1];
- assign sw_rst_ctrl_n_val_1_re = addr_hit[5] && reg_re;
+ assign sw_rst_ctrl_n_val_1_re = addr_hit[8] && reg_re;
// Read data return
always_comb begin
@@ -480,11 +592,24 @@
end
addr_hit[4]: begin
+ reg_rdata_next[0] = cpu_info_ctrl_en_qs;
+ reg_rdata_next[7:4] = cpu_info_ctrl_index_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[3:0] = cpu_info_attr_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[31:0] = cpu_info_qs;
+ end
+
+ addr_hit[7]: begin
reg_rdata_next[0] = sw_rst_regen_en_0_qs;
reg_rdata_next[1] = sw_rst_regen_en_1_qs;
end
- addr_hit[5]: begin
+ addr_hit[8]: begin
reg_rdata_next[0] = sw_rst_ctrl_n_val_0_qs;
reg_rdata_next[1] = sw_rst_ctrl_n_val_1_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index ff70a6f..60505c7 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -276,6 +276,7 @@
pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_pwr_otp_rsp;
pwrmgr_pkg::pwr_lc_req_t pwrmgr_pwr_lc_req;
pwrmgr_pkg::pwr_lc_rsp_t pwrmgr_pwr_lc_rsp;
+ rv_core_ibex_pkg::crashdump_t rv_core_ibex_crashdump;
otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key;
keymgr_pkg::hw_key_req_t keymgr_kmac_key;
keymgr_pkg::kmac_data_req_t keymgr_kmac_data_req;
@@ -452,6 +453,8 @@
.esc_rx_o (alert_handler_esc_rx[0]),
// debug interface
.debug_req_i (debug_req),
+ // crash dump interface
+ .crash_dump_o (rv_core_ibex_crashdump),
// CPU control signals
.fetch_enable_i (1'b1),
.core_sleep_o (pwrmgr_pwr_cpu.core_sleeping)
@@ -999,6 +1002,7 @@
.ast_i(rstmgr_ast_i),
.cpu_i(rstmgr_cpu),
.alert_dump_i(alert_handler_crashdump),
+ .cpu_dump_i(rv_core_ibex_crashdump),
.resets_ast_o(rsts_ast_o),
.tl_i(rstmgr_tl_req),
.tl_o(rstmgr_tl_rsp),
