[dv/gpio] fix intr_test regression failure
This PR fixes intr_test failure in gpio.
The root cause is the recent change in intr_test procedure.
We used to:
1). write all interrupt related registers.
2). read all interrupt related registers, and compare the value with
mirrored vale from scb prediction.
The recent changes step 2).
Now 2). Get mirrored value from RAL, then read all interrupt registers
and compare the read value with stored mirrored value.
This change makes sense but does not work for GPIO, because GPIO
scoreboard has a cycle accurate model and it won't update intr_state
values until next TL read's address phase.
To solve this issue, we ignore the cycle accurate model and just call
csr predict right after csr write operation.
Thanks Weicai for helping out with this issue.
Signed-off-by: Cindy Chen <chencindy@opentitan.org>
diff --git a/hw/ip/gpio/dv/env/gpio_scoreboard.sv b/hw/ip/gpio/dv/env/gpio_scoreboard.sv
index e717947..9f564a4 100644
--- a/hw/ip/gpio/dv/env/gpio_scoreboard.sv
+++ b/hw/ip/gpio/dv/env/gpio_scoreboard.sv
@@ -36,6 +36,8 @@
uvm_reg_data_t masked_out_lower_mask;
uvm_reg_data_t masked_out_upper_mask;
+ string common_seq_type;
+
`uvm_component_utils(gpio_scoreboard)
`uvm_component_new
@@ -47,6 +49,7 @@
// Task: run_phase
task run_phase(uvm_phase phase);
+ void'($value$plusargs("run_%0s", common_seq_type));
super.run_phase(phase);
fork
monitor_gpio_i();
@@ -107,6 +110,14 @@
// if incoming access is a write to a valid csr, then make updates right away
if (write) begin
+ // GPIO scoreboard is cycle accurate and will only update `intr_state` mirrored value at
+ // the address phase of the next read operation.
+ // This is too late for intr_test and intr_test does not need this cycle accurate model,
+ // So we use csr predict function right after the write operations.
+ if ((common_seq_type == "intr_test") &&
+ (csr.get_name() inside {"intr_state", "intr_enable", "intr_test"})) begin
+ void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask)));
+ end
if (csr.get_name() == "intr_state") begin
// As per rtl definition of W1C, hardware must get a chance to make update
// to interrupt state first, so we need to clear interrupt only after possible
