| commit | 5757ffcb79b257601595ec7f2bc15c798584db9b | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@opentitan.org> | Mon Aug 09 14:13:58 2021 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Mon Aug 09 17:44:38 2021 -0700 |
| tree | 3ab6c0cc3e1de42a7b627490f7391b19eea1a52f | |
| parent | 90226aa89bff956ab95ea5bee5f7e4a0985018a7 [diff] |
[dv/gpio] fix intr_test regression failure This PR fixes intr_test failure in gpio. The root cause is the recent change in intr_test procedure. We used to: 1). write all interrupt related registers. 2). read all interrupt related registers, and compare the value with mirrored vale from scb prediction. The recent changes step 2). Now 2). Get mirrored value from RAL, then read all interrupt registers and compare the read value with stored mirrored value. This change makes sense but does not work for GPIO, because GPIO scoreboard has a cycle accurate model and it won't update intr_state values until next TL read's address phase. To solve this issue, we ignore the cycle accurate model and just call csr predict right after csr write operation. Thanks Weicai for helping out with this issue. Signed-off-by: Cindy Chen <chencindy@opentitan.org>
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