[DV] dv updates to enable AST integration simulation
Signed-off-by: Timothy Chen <timothytim@google.com>
[DV] updates for grabbing reset signal
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/dv/env/chip_env.sv b/hw/top_earlgrey/dv/env/chip_env.sv
index c6d91ec..0cfaccf 100644
--- a/hw/top_earlgrey/dv/env/chip_env.sv
+++ b/hw/top_earlgrey/dv/env/chip_env.sv
@@ -43,6 +43,11 @@
`uvm_fatal(`gfn, "failed to get bootstrap_vif from uvm_config_db")
end
+ if (!uvm_config_db#(virtual pins_if#(1))::get(this, "", "rst_n_mon_vif",
+ cfg.rst_n_mon_vif)) begin
+ `uvm_fatal(`gfn, "failed to get rst_n_mon_vif from uvm_config_db")
+ end
+
foreach (cfg.mem_bkdr_vifs[mem]) begin
if (!uvm_config_db#(mem_bkdr_vif)::get(this, "", $sformatf("mem_bkdr_vifs[%0s]", mem.name),
cfg.mem_bkdr_vifs[mem])) begin
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 84fce8d..e004273 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -21,6 +21,7 @@
virtual pins_if#(1) srst_n_vif;
virtual pins_if#(1) jtag_spi_n_vif;
virtual pins_if#(1) bootstrap_vif;
+ virtual pins_if#(1) rst_n_mon_vif;
// sw logger related
string sw_types[] = '{"rom", "sw"};
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv
index e4f5bec..390b358 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv
@@ -19,8 +19,7 @@
virtual task apply_reset(string kind = "HARD");
super.apply_reset(kind);
- // TODO rstmgr takes some time to release reset for IPs. Need to find a better way to know when
- // reset is released by rstmgr
+ wait (cfg.rst_n_mon_vif.pins[0] === 1);
cfg.clk_rst_vif.wait_clks(100);
endtask
diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
index 9735b74..a036f40 100644
--- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
+++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
@@ -12,6 +12,8 @@
`define RAM_MAIN_SUB_HIER `CHIP_HIER.u_ram1p_ram_main.u_mem
`define ROM_HIER `CHIP_HIER.u_rom_rom.u_prim_rom
`define FLASH_HIER `CHIP_HIER.u_flash_eflash
+`define RSTMGR_HIER `CHIP_HIER.u_rstmgr
+`define CLKMGR_HIER `CHIP_HIER.u_clkmgr
`define USBDEV_HIER `CHIP_HIER.u_usbdev
`define FLASH0_MEM_HIER `FLASH_HIER.gen_flash_banks[0].i_core.i_flash.gen_generic.u_impl_generic.u_mem
`define FLASH1_MEM_HIER `FLASH_HIER.gen_flash_banks[1].i_core.i_flash.gen_generic.u_impl_generic.u_mem
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index 06d1a4d..8f9fede 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -44,6 +44,11 @@
bit stub_cpu;
+ // internal clocks and resets
+ // cpu clock cannot reference cpu_hier since cpu clocks are forced off in stub_cpu mode
+ wire cpu_clk = `CLKMGR_HIER.clocks_o.clk_proc_main;
+ wire cpu_rst_n = `CPU_HIER.rst_ni;
+
// interfaces
clk_rst_if clk_rst_if(.clk, .rst_n);
clk_rst_if usb_clk_rst_if(.clk(usb_clk), .rst_n(usb_rst_n));
@@ -51,8 +56,9 @@
pins_if #(1) srst_n_if(.pins(srst_n));
pins_if #(1) jtag_spi_n_if(.pins(jtag_spi_n));
pins_if #(1) bootstrap_if(.pins(bootstrap));
+ pins_if #(1) rst_n_mon_if(.pins(cpu_rst_n));
spi_if spi_if(.rst_n);
- tl_if cpu_d_tl_if(.clk, .rst_n);
+ tl_if cpu_d_tl_if(.clk(cpu_clk), .rst_n(cpu_rst_n));
uart_if uart_if();
jtag_if jtag_if();
@@ -167,7 +173,8 @@
initial begin
// Set clk_rst_vifs
- // drive clk and rst_n from clk_if
+ // drive rst_n from clk_if
+ // clk_rst_if references internal clock created by ast
clk_rst_if.set_active();
usb_clk_rst_if.set_active(.drive_clk_val(1'b1), .drive_rst_n_val(1'b0));
// clk_rst_if will be gotten by env and env.scoreboard (for xbar)
@@ -188,6 +195,8 @@
null, "*.env", "jtag_spi_n_vif", jtag_spi_n_if);
uvm_config_db#(virtual pins_if #(1))::set(
null, "*.env", "bootstrap_vif", bootstrap_if);
+ uvm_config_db#(virtual pins_if #(1))::set(
+ null, "*.env", "rst_n_mon_vif", rst_n_mon_if);
// Backdoors
uvm_config_db#(virtual mem_bkdr_if)::set(
