[flash_ctrl] Alert separation and local escalation
- separate fatal alerts into two categories
- standard fatal alerts
- custom fatal alerts
- allow standard fatal alerts to locally escalate and kill the flas,
but leave custom fatal alert decisions to software and alert handler.
- other documentation clarifications
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 03922b5..ddd7786 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -35,6 +35,9 @@
{ name: "recov_err",
desc: "flash recoverable errors",
},
+ { name: "fatal_std_err",
+ desc: "flash standard fatal errors"
+ },
{ name: "fatal_err",
desc: "flash fatal errors"
},
@@ -222,6 +225,9 @@
{ name: "MEM.CTRL.GLOBAL_ESC",
desc: "Global escalation causes memory to no longer be accessible."
}
+ { name: "MEM.CTRL.LOCAL_ESC",
+ desc: "A subset of fatal errors cause memory to no longer be accessible."
+ }
{ name: "MEM_DISABLE.CONFIG.MUBI",
desc: "Software control for flash disable is multibit."
}
@@ -410,7 +416,7 @@
This is a shortcut mechanism used by the software to completely
kill flash in case of emergency.
- To disable, set this field to anything other than false.
+ To disable, set this field to anything other than kMultiBitBool4False.
'''
resval: false,
tags: [// Dont touch disable, it has several side effects on the system
@@ -1592,10 +1598,53 @@
]
},
+ { name: "STD_FAULT_STATUS",
+ desc: '''
+ This register tabulates standard fault status of the flash.
+
+ These represent errors that occur in the standard structures of the design.
+ For example fsm integrity, counter integrity and tlul integrity.
+ '''
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "reg_intg_err",
+ desc: '''
+ The flash controller encountered a register integrity error.
+ '''
+ },
+ { bits: "1",
+ name: "phy_intg_err",
+ desc: '''
+ The flash memory encountered an integrity error on the host access interface.
+ '''
+ },
+ { bits: "2",
+ name: "lcmgr_err",
+ desc: '''
+ The life cycle management interface has encountered a fatal error.
+ The error is either an FSM sparse encoding error or a count error.
+ '''
+ },
+ { bits: "3",
+ name: "arb_fsm_err",
+ desc: '''
+ The arbiter fsm has encountered a sparse encoding error.
+ '''
+ },
+ { bits: "4",
+ name: "storage_err",
+ desc: '''
+ A shadow register encountered a storage error.
+ '''
+ },
+ ]
+ },
+
{ name: "FAULT_STATUS",
desc: '''
- Flash fault status register.
- This register tabulates detailed fault status of the flash.
+ This register tabulates customized fault status of the flash.
These are errors that are impossible to have been caused by software or unrecoverable
in nature.
@@ -1634,37 +1683,6 @@
'''
},
{ bits: "6",
- name: "reg_intg_err",
- desc: '''
- The flash controller encountered a register integrity error.
- '''
- },
- { bits: "7",
- name: "phy_intg_err",
- desc: '''
- The flash memory encountered a register integrity error.
- '''
- },
- { bits: "8",
- name: "lcmgr_err",
- desc: '''
- The life cycle management interface has encountered a fatal error.
- There is an error with the RMA state machine or counts.
- '''
- },
- { bits: "9",
- name: "arb_fsm_err",
- desc: '''
- The software / hardware interface has encountered a fatal error.
- '''
- },
- { bits: "10",
- name: "storage_err",
- desc: '''
- A shadow register encountered a storage fault.
- '''
- },
- { bits: "11",
name: "seed_err",
desc: '''
The seed reading process encountered an unexpected error.
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
index f6aa5d4..9557f20 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -42,6 +42,9 @@
{ name: "recov_err",
desc: "flash recoverable errors",
},
+ { name: "fatal_std_err",
+ desc: "flash standard fatal errors"
+ },
{ name: "fatal_err",
desc: "flash fatal errors"
},
@@ -229,6 +232,9 @@
{ name: "MEM.CTRL.GLOBAL_ESC",
desc: "Global escalation causes memory to no longer be accessible."
}
+ { name: "MEM.CTRL.LOCAL_ESC",
+ desc: "A subset of fatal errors cause memory to no longer be accessible."
+ }
{ name: "MEM_DISABLE.CONFIG.MUBI",
desc: "Software control for flash disable is multibit."
}
@@ -407,7 +413,7 @@
This is a shortcut mechanism used by the software to completely
kill flash in case of emergency.
- To disable, set this field to anything other than false.
+ To disable, set this field to anything other than kMultiBitBool4False.
'''
resval: false,
tags: [// Dont touch disable, it has several side effects on the system
@@ -1093,10 +1099,53 @@
]
},
+ { name: "STD_FAULT_STATUS",
+ desc: '''
+ This register tabulates standard fault status of the flash.
+
+ These represent errors that occur in the standard structures of the design.
+ For example fsm integrity, counter integrity and tlul integrity.
+ '''
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "reg_intg_err",
+ desc: '''
+ The flash controller encountered a register integrity error.
+ '''
+ },
+ { bits: "1",
+ name: "phy_intg_err",
+ desc: '''
+ The flash memory encountered an integrity error on the host access interface.
+ '''
+ },
+ { bits: "2",
+ name: "lcmgr_err",
+ desc: '''
+ The life cycle management interface has encountered a fatal error.
+ The error is either an FSM sparse encoding error or a count error.
+ '''
+ },
+ { bits: "3",
+ name: "arb_fsm_err",
+ desc: '''
+ The arbiter fsm has encountered a sparse encoding error.
+ '''
+ },
+ { bits: "4",
+ name: "storage_err",
+ desc: '''
+ A shadow register encountered a storage error.
+ '''
+ },
+ ]
+ },
+
{ name: "FAULT_STATUS",
desc: '''
- Flash fault status register.
- This register tabulates detailed fault status of the flash.
+ This register tabulates customized fault status of the flash.
These are errors that are impossible to have been caused by software or unrecoverable
in nature.
@@ -1135,37 +1184,6 @@
'''
},
{ bits: "6",
- name: "reg_intg_err",
- desc: '''
- The flash controller encountered a register integrity error.
- '''
- },
- { bits: "7",
- name: "phy_intg_err",
- desc: '''
- The flash memory encountered a register integrity error.
- '''
- },
- { bits: "8",
- name: "lcmgr_err",
- desc: '''
- The life cycle management interface has encountered a fatal error.
- There is an error with the RMA state machine or counts.
- '''
- },
- { bits: "9",
- name: "arb_fsm_err",
- desc: '''
- The software / hardware interface has encountered a fatal error.
- '''
- },
- { bits: "10",
- name: "storage_err",
- desc: '''
- A shadow register encountered a storage fault.
- '''
- },
- { bits: "11",
name: "seed_err",
desc: '''
The seed reading process encountered an unexpected error.
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index 0a4965c..6d79e2b 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -699,6 +699,9 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
+ // flash disable declaration
+ prim_mubi_pkg::mubi4_t flash_disable;
+
// tie off hardware clear path
assign hw2reg.erase_suspend.d = 1'b0;
@@ -709,6 +712,9 @@
.clk_i,
.rst_ni,
+ // disable flash through memory protection
+ .flash_disable_i(flash_disable),
+
// arbiter interface selection
.if_sel_i(if_sel),
@@ -842,16 +848,23 @@
logic fatal_err;
assign fatal_err = |reg2hw.fault_status;
+ logic fatal_std_err;
+ assign fatal_std_err = |reg2hw.std_fault_status;
+
+ lc_ctrl_pkg::lc_tx_t local_esc;
+ assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
assign alert_srcs = { fatal_err,
+ fatal_std_err,
recov_err
};
assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+ reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
};
- localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0};
+ localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b1, 1'b0};
for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
prim_alert_sender #(
.AsyncOn(AlertAsyncOn[i]),
@@ -882,10 +895,13 @@
.lc_en_o(lc_escalate_en)
);
+ lc_ctrl_pkg::lc_tx_t escalate_en;
+ // SEC_CM: MEM.CTRL.LOCAL_ESC
+ assign escalate_en = lc_ctrl_pkg::lc_tx_or_hi(dis_access, local_esc);
+
// flash functional disable
- prim_mubi_pkg::mubi4_t flash_disable;
lc_ctrl_pkg::lc_tx_t lc_disable;
- assign lc_disable = lc_ctrl_pkg::lc_tx_or(lc_escalate_en, dis_access, lc_ctrl_pkg::On);
+ assign lc_disable = lc_ctrl_pkg::lc_tx_or_hi(lc_escalate_en, escalate_en);
// Normally, faults (those registered in fault_status) should also cause flash access
// to disable. However, most errors encountered by hardware during flash access
@@ -937,29 +953,34 @@
sw_ctrl_err.phy_err;
// all hardware interface errors are considered faults
+ // There are two types of faults
+ // standard faults - things like fsm / counter / tlul integrity
+ // custom faults - things like hardware interface not working correctly
assign hw2reg.fault_status.mp_err.d = 1'b1;
assign hw2reg.fault_status.rd_err.d = 1'b1;
assign hw2reg.fault_status.prog_win_err.d = 1'b1;
assign hw2reg.fault_status.prog_type_err.d = 1'b1;
assign hw2reg.fault_status.flash_phy_err.d = 1'b1;
- assign hw2reg.fault_status.reg_intg_err.d = 1'b1;
- assign hw2reg.fault_status.phy_intg_err.d = 1'b1;
- assign hw2reg.fault_status.lcmgr_err.d = 1'b1;
- assign hw2reg.fault_status.arb_fsm_err.d = 1'b1;
- assign hw2reg.fault_status.storage_err.d = 1'b1;
assign hw2reg.fault_status.seed_err.d = 1'b1;
assign hw2reg.fault_status.mp_err.de = hw_err.mp_err;
assign hw2reg.fault_status.rd_err.de = hw_err.rd_err;
assign hw2reg.fault_status.prog_win_err.de = hw_err.prog_win_err;
assign hw2reg.fault_status.prog_type_err.de = hw_err.prog_type_err;
assign hw2reg.fault_status.flash_phy_err.de = hw_err.phy_err;
- assign hw2reg.fault_status.reg_intg_err.de = intg_err;
- assign hw2reg.fault_status.phy_intg_err.de = flash_phy_rsp.intg_err;
- assign hw2reg.fault_status.lcmgr_err.de = lcmgr_err;
- assign hw2reg.fault_status.arb_fsm_err.de = arb_fsm_err;
- assign hw2reg.fault_status.storage_err.de = storage_err;
assign hw2reg.fault_status.seed_err.de = seed_err;
+ // standard faults
+ assign hw2reg.std_fault_status.reg_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.phy_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.lcmgr_err.d = 1'b1;
+ assign hw2reg.std_fault_status.arb_fsm_err.d = 1'b1;
+ assign hw2reg.std_fault_status.storage_err.d = 1'b1;
+ assign hw2reg.std_fault_status.reg_intg_err.de = intg_err;
+ assign hw2reg.std_fault_status.phy_intg_err.de = flash_phy_rsp.intg_err;
+ assign hw2reg.std_fault_status.lcmgr_err.de = lcmgr_err;
+ assign hw2reg.std_fault_status.arb_fsm_err.de = arb_fsm_err;
+ assign hw2reg.std_fault_status.storage_err.de = storage_err;
+
// Correctable ECC count / address
for (genvar i = 0; i < NumBanks; i++) begin : gen_ecc_single_err_reg
assign hw2reg.ecc_single_err_cnt[i].de = flash_phy_rsp.ecc_single_err[i];
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson b/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson
index 4aba596..99d3fff 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson
@@ -90,6 +90,12 @@
tests: []
}
{
+ name: sec_cm_mem_ctrl_local_esc
+ desc: "Verify the countermeasure(s) MEM.CTRL.LOCAL_ESC."
+ milestone: V2S
+ tests: []
+ }
+ {
name: sec_cm_mem_disable_config_mubi
desc: "Verify the countermeasure(s) MEM_DISABLE.CONFIG.MUBI."
milestone: V2S
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
index 93c363c..84c4a4d 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
@@ -58,7 +58,7 @@
super.initialize(csr_base_addr);
shadow_update_err_status_fields[ral.err_code.update_err] = 1;
- shadow_storage_err_status_fields[ral.fault_status.storage_err] = 1;
+ shadow_storage_err_status_fields[ral.std_fault_status.storage_err] = 1;
// create the seq_cfg and call configure
seq_cfg = flash_ctrl_seq_cfg::type_id::create("seq_cfg");
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
index 1054cbd..4583987 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
@@ -23,9 +23,9 @@
`include "dv_macros.svh"
// parameters
- parameter string LIST_OF_ALERTS[] = {"recov_err", "fatal_err"};
+ parameter string LIST_OF_ALERTS[] = {"recov_err", "fatal_std_err", "fatal_err"};
- parameter uint NUM_ALERTS = 4;
+ parameter uint NUM_ALERTS = 3;
parameter uint FlashNumPages = flash_ctrl_pkg::NumBanks * flash_ctrl_pkg::PagesPerBank;
parameter uint FlashSizeBytes = FlashNumPages * flash_ctrl_pkg::WordsPerPage *
flash_ctrl_pkg::DataWidth / 8;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index ac819ca..1e98a94 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -700,6 +700,9 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
+ // flash disable declaration
+ prim_mubi_pkg::mubi4_t flash_disable;
+
// tie off hardware clear path
assign hw2reg.erase_suspend.d = 1'b0;
@@ -710,6 +713,9 @@
.clk_i,
.rst_ni,
+ // disable flash through memory protection
+ .flash_disable_i(flash_disable),
+
// arbiter interface selection
.if_sel_i(if_sel),
@@ -843,16 +849,23 @@
logic fatal_err;
assign fatal_err = |reg2hw.fault_status;
+ logic fatal_std_err;
+ assign fatal_std_err = |reg2hw.std_fault_status;
+
+ lc_ctrl_pkg::lc_tx_t local_esc;
+ assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
assign alert_srcs = { fatal_err,
+ fatal_std_err,
recov_err
};
assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+ reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
};
- localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0};
+ localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b1, 1'b0};
for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
prim_alert_sender #(
.AsyncOn(AlertAsyncOn[i]),
@@ -883,10 +896,13 @@
.lc_en_o(lc_escalate_en)
);
+ lc_ctrl_pkg::lc_tx_t escalate_en;
+ // SEC_CM: MEM.CTRL.LOCAL_ESC
+ assign escalate_en = lc_ctrl_pkg::lc_tx_or_hi(dis_access, local_esc);
+
// flash functional disable
- prim_mubi_pkg::mubi4_t flash_disable;
lc_ctrl_pkg::lc_tx_t lc_disable;
- assign lc_disable = lc_ctrl_pkg::lc_tx_or(lc_escalate_en, dis_access, lc_ctrl_pkg::On);
+ assign lc_disable = lc_ctrl_pkg::lc_tx_or_hi(lc_escalate_en, escalate_en);
// Normally, faults (those registered in fault_status) should also cause flash access
// to disable. However, most errors encountered by hardware during flash access
@@ -938,29 +954,34 @@
sw_ctrl_err.phy_err;
// all hardware interface errors are considered faults
+ // There are two types of faults
+ // standard faults - things like fsm / counter / tlul integrity
+ // custom faults - things like hardware interface not working correctly
assign hw2reg.fault_status.mp_err.d = 1'b1;
assign hw2reg.fault_status.rd_err.d = 1'b1;
assign hw2reg.fault_status.prog_win_err.d = 1'b1;
assign hw2reg.fault_status.prog_type_err.d = 1'b1;
assign hw2reg.fault_status.flash_phy_err.d = 1'b1;
- assign hw2reg.fault_status.reg_intg_err.d = 1'b1;
- assign hw2reg.fault_status.phy_intg_err.d = 1'b1;
- assign hw2reg.fault_status.lcmgr_err.d = 1'b1;
- assign hw2reg.fault_status.arb_fsm_err.d = 1'b1;
- assign hw2reg.fault_status.storage_err.d = 1'b1;
assign hw2reg.fault_status.seed_err.d = 1'b1;
assign hw2reg.fault_status.mp_err.de = hw_err.mp_err;
assign hw2reg.fault_status.rd_err.de = hw_err.rd_err;
assign hw2reg.fault_status.prog_win_err.de = hw_err.prog_win_err;
assign hw2reg.fault_status.prog_type_err.de = hw_err.prog_type_err;
assign hw2reg.fault_status.flash_phy_err.de = hw_err.phy_err;
- assign hw2reg.fault_status.reg_intg_err.de = intg_err;
- assign hw2reg.fault_status.phy_intg_err.de = flash_phy_rsp.intg_err;
- assign hw2reg.fault_status.lcmgr_err.de = lcmgr_err;
- assign hw2reg.fault_status.arb_fsm_err.de = arb_fsm_err;
- assign hw2reg.fault_status.storage_err.de = storage_err;
assign hw2reg.fault_status.seed_err.de = seed_err;
+ // standard faults
+ assign hw2reg.std_fault_status.reg_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.phy_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.lcmgr_err.d = 1'b1;
+ assign hw2reg.std_fault_status.arb_fsm_err.d = 1'b1;
+ assign hw2reg.std_fault_status.storage_err.d = 1'b1;
+ assign hw2reg.std_fault_status.reg_intg_err.de = intg_err;
+ assign hw2reg.std_fault_status.phy_intg_err.de = flash_phy_rsp.intg_err;
+ assign hw2reg.std_fault_status.lcmgr_err.de = lcmgr_err;
+ assign hw2reg.std_fault_status.arb_fsm_err.de = arb_fsm_err;
+ assign hw2reg.std_fault_status.storage_err.de = storage_err;
+
// Correctable ECC count / address
for (genvar i = 0; i < NumBanks; i++) begin : gen_ecc_single_err_reg
assign hw2reg.ecc_single_err_cnt[i].de = flash_phy_rsp.ecc_single_err[i];
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
index dcec542..b73db17 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
@@ -121,10 +121,10 @@
// Create steering logic
always_comb begin
unique case (tl_i.a_address[AW-1:0]) inside
- [384:387]: begin
+ [388:391]: begin
reg_steer = 0;
end
- [388:391]: begin
+ [392:395]: begin
reg_steer = 1;
end
default: begin
@@ -203,6 +203,7 @@
logic intr_test_corr_err_wd;
logic alert_test_we;
logic alert_test_recov_err_wd;
+ logic alert_test_fatal_std_err_wd;
logic alert_test_fatal_err_wd;
logic dis_we;
logic [3:0] dis_qs;
@@ -965,16 +966,16 @@
logic err_code_flash_phy_err_wd;
logic err_code_update_err_qs;
logic err_code_update_err_wd;
+ logic std_fault_status_reg_intg_err_qs;
+ logic std_fault_status_phy_intg_err_qs;
+ logic std_fault_status_lcmgr_err_qs;
+ logic std_fault_status_arb_fsm_err_qs;
+ logic std_fault_status_storage_err_qs;
logic fault_status_mp_err_qs;
logic fault_status_rd_err_qs;
logic fault_status_prog_win_err_qs;
logic fault_status_prog_type_err_qs;
logic fault_status_flash_phy_err_qs;
- logic fault_status_reg_intg_err_qs;
- logic fault_status_phy_intg_err_qs;
- logic fault_status_lcmgr_err_qs;
- logic fault_status_arb_fsm_err_qs;
- logic fault_status_storage_err_qs;
logic fault_status_seed_err_qs;
logic [19:0] err_addr_qs;
logic ecc_single_err_cnt_we;
@@ -1406,7 +1407,7 @@
// R[alert_test]: V(True)
logic alert_test_qe;
- logic [1:0] alert_test_flds_we;
+ logic [2:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
// F[recov_err]: 0:0
prim_subreg_ext #(
@@ -1423,7 +1424,22 @@
);
assign reg2hw.alert_test.recov_err.qe = alert_test_qe;
- // F[fatal_err]: 1:1
+ // F[fatal_std_err]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_std_err (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_std_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[1]),
+ .q (reg2hw.alert_test.fatal_std_err.q),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_std_err.qe = alert_test_qe;
+
+ // F[fatal_err]: 2:2
prim_subreg_ext #(
.DW (1)
) u_alert_test_fatal_err (
@@ -1432,7 +1448,7 @@
.wd (alert_test_fatal_err_wd),
.d ('0),
.qre (),
- .qe (alert_test_flds_we[1]),
+ .qe (alert_test_flds_we[2]),
.q (reg2hw.alert_test.fatal_err.q),
.qs ()
);
@@ -12103,6 +12119,133 @@
);
+ // R[std_fault_status]: V(False)
+ // F[reg_intg_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_reg_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.reg_intg_err.de),
+ .d (hw2reg.std_fault_status.reg_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.reg_intg_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_reg_intg_err_qs)
+ );
+
+ // F[phy_intg_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_phy_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.phy_intg_err.de),
+ .d (hw2reg.std_fault_status.phy_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.phy_intg_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_phy_intg_err_qs)
+ );
+
+ // F[lcmgr_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_lcmgr_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.lcmgr_err.de),
+ .d (hw2reg.std_fault_status.lcmgr_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.lcmgr_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_lcmgr_err_qs)
+ );
+
+ // F[arb_fsm_err]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_arb_fsm_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.arb_fsm_err.de),
+ .d (hw2reg.std_fault_status.arb_fsm_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.arb_fsm_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_arb_fsm_err_qs)
+ );
+
+ // F[storage_err]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_storage_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.storage_err.de),
+ .d (hw2reg.std_fault_status.storage_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.storage_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_storage_err_qs)
+ );
+
+
// R[fault_status]: V(False)
// F[mp_err]: 1:1
prim_subreg #(
@@ -12229,132 +12372,7 @@
.qs (fault_status_flash_phy_err_qs)
);
- // F[reg_intg_err]: 6:6
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_reg_intg_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.reg_intg_err.de),
- .d (hw2reg.fault_status.reg_intg_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.reg_intg_err.q),
-
- // to register interface (read)
- .qs (fault_status_reg_intg_err_qs)
- );
-
- // F[phy_intg_err]: 7:7
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_phy_intg_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.phy_intg_err.de),
- .d (hw2reg.fault_status.phy_intg_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.phy_intg_err.q),
-
- // to register interface (read)
- .qs (fault_status_phy_intg_err_qs)
- );
-
- // F[lcmgr_err]: 8:8
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_lcmgr_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.lcmgr_err.de),
- .d (hw2reg.fault_status.lcmgr_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.lcmgr_err.q),
-
- // to register interface (read)
- .qs (fault_status_lcmgr_err_qs)
- );
-
- // F[arb_fsm_err]: 9:9
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_arb_fsm_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.arb_fsm_err.de),
- .d (hw2reg.fault_status.arb_fsm_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.arb_fsm_err.q),
-
- // to register interface (read)
- .qs (fault_status_arb_fsm_err_qs)
- );
-
- // F[storage_err]: 10:10
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_storage_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.storage_err.de),
- .d (hw2reg.fault_status.storage_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.storage_err.q),
-
- // to register interface (read)
- .qs (fault_status_storage_err_qs)
- );
-
- // F[seed_err]: 11:11
+ // F[seed_err]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
@@ -12747,7 +12765,7 @@
- logic [95:0] addr_hit;
+ logic [96:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
@@ -12836,16 +12854,17 @@
addr_hit[83] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
addr_hit[84] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
addr_hit[85] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
- addr_hit[86] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
- addr_hit[87] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
- addr_hit[88] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
- addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
- addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
- addr_hit[91] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
- addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
- addr_hit[93] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
- addr_hit[94] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
- addr_hit[95] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+ addr_hit[86] = (reg_addr == FLASH_CTRL_STD_FAULT_STATUS_OFFSET);
+ addr_hit[87] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
+ addr_hit[88] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
+ addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
+ addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
+ addr_hit[91] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
+ addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
+ addr_hit[93] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+ addr_hit[94] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[95] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[96] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -12948,7 +12967,8 @@
(addr_hit[92] & (|(FLASH_CTRL_CORE_PERMIT[92] & ~reg_be))) |
(addr_hit[93] & (|(FLASH_CTRL_CORE_PERMIT[93] & ~reg_be))) |
(addr_hit[94] & (|(FLASH_CTRL_CORE_PERMIT[94] & ~reg_be))) |
- (addr_hit[95] & (|(FLASH_CTRL_CORE_PERMIT[95] & ~reg_be)))));
+ (addr_hit[95] & (|(FLASH_CTRL_CORE_PERMIT[95] & ~reg_be))) |
+ (addr_hit[96] & (|(FLASH_CTRL_CORE_PERMIT[96] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -12993,7 +13013,9 @@
assign alert_test_recov_err_wd = reg_wdata[0];
- assign alert_test_fatal_err_wd = reg_wdata[1];
+ assign alert_test_fatal_std_err_wd = reg_wdata[1];
+
+ assign alert_test_fatal_err_wd = reg_wdata[2];
assign dis_we = addr_hit[4] & reg_we & !reg_error;
assign dis_wd = reg_wdata[3:0];
@@ -13749,25 +13771,25 @@
assign err_code_flash_phy_err_wd = reg_wdata[5];
assign err_code_update_err_wd = reg_wdata[6];
- assign ecc_single_err_cnt_we = addr_hit[88] & reg_we & !reg_error;
+ assign ecc_single_err_cnt_we = addr_hit[89] & reg_we & !reg_error;
assign ecc_single_err_cnt_ecc_single_err_cnt_0_wd = reg_wdata[7:0];
assign ecc_single_err_cnt_ecc_single_err_cnt_1_wd = reg_wdata[15:8];
- assign phy_alert_cfg_we = addr_hit[91] & reg_we & !reg_error;
+ assign phy_alert_cfg_we = addr_hit[92] & reg_we & !reg_error;
assign phy_alert_cfg_alert_ack_wd = reg_wdata[0];
assign phy_alert_cfg_alert_trig_wd = reg_wdata[1];
- assign scratch_we = addr_hit[93] & reg_we & !reg_error;
+ assign scratch_we = addr_hit[94] & reg_we & !reg_error;
assign scratch_wd = reg_wdata[31:0];
- assign fifo_lvl_we = addr_hit[94] & reg_we & !reg_error;
+ assign fifo_lvl_we = addr_hit[95] & reg_we & !reg_error;
assign fifo_lvl_prog_wd = reg_wdata[4:0];
assign fifo_lvl_rd_wd = reg_wdata[12:8];
- assign fifo_rst_we = addr_hit[95] & reg_we & !reg_error;
+ assign fifo_rst_we = addr_hit[96] & reg_we & !reg_error;
assign fifo_rst_wd = reg_wdata[0];
@@ -13805,6 +13827,7 @@
addr_hit[3]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
end
addr_hit[4]: begin
@@ -14379,57 +14402,60 @@
end
addr_hit[86]: begin
+ reg_rdata_next[0] = std_fault_status_reg_intg_err_qs;
+ reg_rdata_next[1] = std_fault_status_phy_intg_err_qs;
+ reg_rdata_next[2] = std_fault_status_lcmgr_err_qs;
+ reg_rdata_next[3] = std_fault_status_arb_fsm_err_qs;
+ reg_rdata_next[4] = std_fault_status_storage_err_qs;
+ end
+
+ addr_hit[87]: begin
reg_rdata_next[1] = fault_status_mp_err_qs;
reg_rdata_next[2] = fault_status_rd_err_qs;
reg_rdata_next[3] = fault_status_prog_win_err_qs;
reg_rdata_next[4] = fault_status_prog_type_err_qs;
reg_rdata_next[5] = fault_status_flash_phy_err_qs;
- reg_rdata_next[6] = fault_status_reg_intg_err_qs;
- reg_rdata_next[7] = fault_status_phy_intg_err_qs;
- reg_rdata_next[8] = fault_status_lcmgr_err_qs;
- reg_rdata_next[9] = fault_status_arb_fsm_err_qs;
- reg_rdata_next[10] = fault_status_storage_err_qs;
- reg_rdata_next[11] = fault_status_seed_err_qs;
- end
-
- addr_hit[87]: begin
- reg_rdata_next[19:0] = err_addr_qs;
+ reg_rdata_next[6] = fault_status_seed_err_qs;
end
addr_hit[88]: begin
+ reg_rdata_next[19:0] = err_addr_qs;
+ end
+
+ addr_hit[89]: begin
reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
end
- addr_hit[89]: begin
+ addr_hit[90]: begin
reg_rdata_next[19:0] = ecc_single_err_addr_0_qs;
end
- addr_hit[90]: begin
+ addr_hit[91]: begin
reg_rdata_next[19:0] = ecc_single_err_addr_1_qs;
end
- addr_hit[91]: begin
+ addr_hit[92]: begin
reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
end
- addr_hit[92]: begin
+ addr_hit[93]: begin
reg_rdata_next[0] = phy_status_init_wip_qs;
reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
end
- addr_hit[93]: begin
+ addr_hit[94]: begin
reg_rdata_next[31:0] = scratch_qs;
end
- addr_hit[94]: begin
+ addr_hit[95]: begin
reg_rdata_next[4:0] = fifo_lvl_prog_qs;
reg_rdata_next[12:8] = fifo_lvl_rd_qs;
end
- addr_hit[95]: begin
+ addr_hit[96]: begin
reg_rdata_next[0] = fifo_rst_qs;
end
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
index dd68e82..f2577c7 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
@@ -177,7 +177,7 @@
end
end
- assign seed_err_o = seed_err_q;
+ assign seed_err_o = seed_err_q | seed_err_d;
// seed cnt tracks which seed round we are handling at the moment
always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -414,7 +414,7 @@
start = 1'b0;
state_d = StWait;
end else if (done_i) begin
- seed_err_d = |err_i | seed_err_q;
+ seed_err_d = |err_i;
state_d = StReadEval;
end
end // case: StReadSeeds
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index f8795b4..f216eca 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -22,7 +22,7 @@
parameter int BytesPerPage = 2048;
parameter int BytesPerBank = 524288;
parameter int unsigned ExecEn = 32'ha26a38f7;
- parameter int NumAlerts = 2;
+ parameter int NumAlerts = 3;
// Address widths within the block
parameter int CoreAw = 9;
@@ -110,6 +110,10 @@
struct packed {
logic q;
logic qe;
+ } fatal_std_err;
+ struct packed {
+ logic q;
+ logic qe;
} fatal_err;
} flash_ctrl_reg2hw_alert_test_reg_t;
@@ -484,21 +488,6 @@
typedef struct packed {
struct packed {
logic q;
- } mp_err;
- struct packed {
- logic q;
- } rd_err;
- struct packed {
- logic q;
- } prog_win_err;
- struct packed {
- logic q;
- } prog_type_err;
- struct packed {
- logic q;
- } flash_phy_err;
- struct packed {
- logic q;
} reg_intg_err;
struct packed {
logic q;
@@ -512,6 +501,24 @@
struct packed {
logic q;
} storage_err;
+ } flash_ctrl_reg2hw_std_fault_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } mp_err;
+ struct packed {
+ logic q;
+ } rd_err;
+ struct packed {
+ logic q;
+ } prog_win_err;
+ struct packed {
+ logic q;
+ } prog_type_err;
+ struct packed {
+ logic q;
+ } flash_phy_err;
struct packed {
logic q;
} seed_err;
@@ -655,26 +662,6 @@
struct packed {
logic d;
logic de;
- } mp_err;
- struct packed {
- logic d;
- logic de;
- } rd_err;
- struct packed {
- logic d;
- logic de;
- } prog_win_err;
- struct packed {
- logic d;
- logic de;
- } prog_type_err;
- struct packed {
- logic d;
- logic de;
- } flash_phy_err;
- struct packed {
- logic d;
- logic de;
} reg_intg_err;
struct packed {
logic d;
@@ -692,6 +679,29 @@
logic d;
logic de;
} storage_err;
+ } flash_ctrl_hw2reg_std_fault_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
struct packed {
logic d;
logic de;
@@ -730,10 +740,10 @@
// Register -> HW type for core interface
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [577:572]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [571:566]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [565:554]
- flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [553:550]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [579:574]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [573:568]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [567:556]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [555:550]
flash_ctrl_reg2hw_dis_reg_t dis; // [549:546]
flash_ctrl_reg2hw_exec_reg_t exec; // [545:514]
flash_ctrl_reg2hw_init_reg_t init; // [513:513]
@@ -756,7 +766,8 @@
flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t [1:0]
bank1_info2_page_cfg_shadowed; // [87:74]
flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t [1:0] mp_bank_cfg_shadowed; // [73:72]
- flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [71:61]
+ flash_ctrl_reg2hw_std_fault_status_reg_t std_fault_status; // [71:67]
+ flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [66:61]
flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [60:45]
flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
@@ -773,7 +784,8 @@
flash_ctrl_hw2reg_op_status_reg_t op_status; // [134:131]
flash_ctrl_hw2reg_status_reg_t status; // [130:121]
flash_ctrl_hw2reg_err_code_reg_t err_code; // [120:109]
- flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [108:87]
+ flash_ctrl_hw2reg_std_fault_status_reg_t std_fault_status; // [108:99]
+ flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [98:87]
flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [86:66]
flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [65:48]
flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [47:6]
@@ -867,16 +879,17 @@
parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 14c;
parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 150;
parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 154;
- parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 158;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 15c;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 160;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 164;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 168;
- parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 16c;
- parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 170;
- parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 174;
- parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 178;
- parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 17c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STD_FAULT_STATUS_OFFSET = 9'h 158;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 15c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 160;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 164;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 168;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 16c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 170;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 174;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 178;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 17c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 180;
// Reset values for hwext registers and their fields for core interface
parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h 0;
@@ -886,16 +899,17 @@
parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
- parameter logic [1:0] FLASH_CTRL_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [2:0] FLASH_CTRL_ALERT_TEST_RESVAL = 3'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
// Window parameters for core interface
- parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 180;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 184;
parameter int unsigned FLASH_CTRL_PROG_FIFO_SIZE = 'h 4;
- parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 184;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 188;
parameter int unsigned FLASH_CTRL_RD_FIFO_SIZE = 'h 4;
// Register index for core interface
@@ -986,6 +1000,7 @@
FLASH_CTRL_OP_STATUS,
FLASH_CTRL_STATUS,
FLASH_CTRL_ERR_CODE,
+ FLASH_CTRL_STD_FAULT_STATUS,
FLASH_CTRL_FAULT_STATUS,
FLASH_CTRL_ERR_ADDR,
FLASH_CTRL_ECC_SINGLE_ERR_CNT,
@@ -999,7 +1014,7 @@
} flash_ctrl_core_id_e;
// Register width information to check illegal writes for core interface
- parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [96] = '{
+ parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [97] = '{
4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
@@ -1086,16 +1101,17 @@
4'b 0001, // index[83] FLASH_CTRL_OP_STATUS
4'b 0001, // index[84] FLASH_CTRL_STATUS
4'b 0001, // index[85] FLASH_CTRL_ERR_CODE
- 4'b 0011, // index[86] FLASH_CTRL_FAULT_STATUS
- 4'b 0111, // index[87] FLASH_CTRL_ERR_ADDR
- 4'b 0011, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_CNT
- 4'b 0111, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
- 4'b 0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
- 4'b 0001, // index[91] FLASH_CTRL_PHY_ALERT_CFG
- 4'b 0001, // index[92] FLASH_CTRL_PHY_STATUS
- 4'b 1111, // index[93] FLASH_CTRL_SCRATCH
- 4'b 0011, // index[94] FLASH_CTRL_FIFO_LVL
- 4'b 0001 // index[95] FLASH_CTRL_FIFO_RST
+ 4'b 0001, // index[86] FLASH_CTRL_STD_FAULT_STATUS
+ 4'b 0001, // index[87] FLASH_CTRL_FAULT_STATUS
+ 4'b 0111, // index[88] FLASH_CTRL_ERR_ADDR
+ 4'b 0011, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+ 4'b 0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+ 4'b 0111, // index[91] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+ 4'b 0001, // index[92] FLASH_CTRL_PHY_ALERT_CFG
+ 4'b 0001, // index[93] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[94] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[95] FLASH_CTRL_FIFO_LVL
+ 4'b 0001 // index[96] FLASH_CTRL_FIFO_RST
};
endpackage
diff --git a/hw/ip/flash_ctrl/rtl/flash_mp.sv b/hw/ip/flash_ctrl/rtl/flash_mp.sv
index f0b18d3..e1ce65a 100644
--- a/hw/ip/flash_ctrl/rtl/flash_mp.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_mp.sv
@@ -11,6 +11,8 @@
input clk_i,
input rst_ni,
+ input prim_mubi_pkg::mubi4_t flash_disable_i,
+
// interface selection
input flash_sel_e if_sel_i,
@@ -184,7 +186,6 @@
assign data_ecc_en = data_en & (rd_i | prog_i) & data_region_cfg.ecc_en.q;
assign data_he_en = data_en & data_region_cfg.he_en.q;
-
assign invalid_data_txn = req_i & data_part_sel &
~(data_rd_en |
data_prog_en |
@@ -260,7 +261,10 @@
logic txn_err;
logic no_allowed_txn;
- assign no_allowed_txn = req_i & (addr_invalid | invalid_data_txn | invalid_info_txn);
+ // if flash_disable is true, transaction is always invalid
+ assign no_allowed_txn = req_i &
+ ((prim_mubi_pkg::mubi4_test_true_loose(flash_disable_i)) |
+ (addr_invalid | invalid_data_txn | invalid_info_txn));
// return done and error the next cycle
always_ff @(posedge clk_i or negedge rst_ni) begin
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 15959d7..739ae6e 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -13914,6 +13914,15 @@
lpg_idx: 16
}
{
+ name: flash_ctrl_fatal_std_err
+ width: 1
+ type: alert
+ async: "1"
+ module_name: flash_ctrl
+ lpg_name: infra_lc_0
+ lpg_idx: 16
+ }
+ {
name: flash_ctrl_fatal_err
width: 1
type: alert
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 0da408f..d246209 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -39,28 +39,29 @@
assign alert_if[32].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
assign alert_if[33].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
assign alert_if[34].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
-assign alert_if[37].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[43].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[44].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[45].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[46].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[47].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
-assign alert_if[48].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[49].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[50].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[51].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
-assign alert_if[52].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[53].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
-assign alert_if[54].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[55].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
-assign alert_if[56].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
-assign alert_if[57].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
-assign alert_if[58].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
-assign alert_if[59].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[48].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
+assign alert_if[49].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[50].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[51].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[52].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
+assign alert_if[53].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[54].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
+assign alert_if[55].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[56].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[57].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
+assign alert_if[58].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
+assign alert_if[59].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
+assign alert_if[60].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 461b588..2a7a464 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -39,6 +39,7 @@
"sensor_ctrl_fatal_alert",
"sram_ctrl_ret_aon_fatal_error",
"flash_ctrl_recov_err",
+ "flash_ctrl_fatal_std_err",
"flash_ctrl_fatal_err",
"rv_dm_fatal_fault",
"rv_plic_fatal_fault",
@@ -67,4 +68,4 @@
"rv_core_ibex_recov_hw_err"
};
-parameter uint NUM_ALERTS = 60;
+parameter uint NUM_ALERTS = 61;
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index 1b41eaf..9930132 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -41,6 +41,9 @@
{ name: "recov_err",
desc: "flash recoverable errors",
},
+ { name: "fatal_std_err",
+ desc: "flash standard fatal errors"
+ },
{ name: "fatal_err",
desc: "flash fatal errors"
},
@@ -228,6 +231,9 @@
{ name: "MEM.CTRL.GLOBAL_ESC",
desc: "Global escalation causes memory to no longer be accessible."
}
+ { name: "MEM.CTRL.LOCAL_ESC",
+ desc: "A subset of fatal errors cause memory to no longer be accessible."
+ }
{ name: "MEM_DISABLE.CONFIG.MUBI",
desc: "Software control for flash disable is multibit."
}
@@ -416,7 +422,7 @@
This is a shortcut mechanism used by the software to completely
kill flash in case of emergency.
- To disable, set this field to anything other than false.
+ To disable, set this field to anything other than kMultiBitBool4False.
'''
resval: false,
tags: [// Dont touch disable, it has several side effects on the system
@@ -1598,10 +1604,53 @@
]
},
+ { name: "STD_FAULT_STATUS",
+ desc: '''
+ This register tabulates standard fault status of the flash.
+
+ These represent errors that occur in the standard structures of the design.
+ For example fsm integrity, counter integrity and tlul integrity.
+ '''
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "reg_intg_err",
+ desc: '''
+ The flash controller encountered a register integrity error.
+ '''
+ },
+ { bits: "1",
+ name: "phy_intg_err",
+ desc: '''
+ The flash memory encountered an integrity error on the host access interface.
+ '''
+ },
+ { bits: "2",
+ name: "lcmgr_err",
+ desc: '''
+ The life cycle management interface has encountered a fatal error.
+ The error is either an FSM sparse encoding error or a count error.
+ '''
+ },
+ { bits: "3",
+ name: "arb_fsm_err",
+ desc: '''
+ The arbiter fsm has encountered a sparse encoding error.
+ '''
+ },
+ { bits: "4",
+ name: "storage_err",
+ desc: '''
+ A shadow register encountered a storage error.
+ '''
+ },
+ ]
+ },
+
{ name: "FAULT_STATUS",
desc: '''
- Flash fault status register.
- This register tabulates detailed fault status of the flash.
+ This register tabulates customized fault status of the flash.
These are errors that are impossible to have been caused by software or unrecoverable
in nature.
@@ -1640,37 +1689,6 @@
'''
},
{ bits: "6",
- name: "reg_intg_err",
- desc: '''
- The flash controller encountered a register integrity error.
- '''
- },
- { bits: "7",
- name: "phy_intg_err",
- desc: '''
- The flash memory encountered a register integrity error.
- '''
- },
- { bits: "8",
- name: "lcmgr_err",
- desc: '''
- The life cycle management interface has encountered a fatal error.
- There is an error with the RMA state machine or counts.
- '''
- },
- { bits: "9",
- name: "arb_fsm_err",
- desc: '''
- The software / hardware interface has encountered a fatal error.
- '''
- },
- { bits: "10",
- name: "storage_err",
- desc: '''
- A shadow register encountered a storage fault.
- '''
- },
- { bits: "11",
name: "seed_err",
desc: '''
The seed reading process encountered an unexpected error.
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
index 4aba596..99d3fff 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
@@ -90,6 +90,12 @@
tests: []
}
{
+ name: sec_cm_mem_ctrl_local_esc
+ desc: "Verify the countermeasure(s) MEM.CTRL.LOCAL_ESC."
+ milestone: V2S
+ tests: []
+ }
+ {
name: sec_cm_mem_disable_config_mubi
desc: "Verify the countermeasure(s) MEM_DISABLE.CONFIG.MUBI."
milestone: V2S
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index c15fa4a..cfe6a5d 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -706,6 +706,9 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
+ // flash disable declaration
+ prim_mubi_pkg::mubi4_t flash_disable;
+
// tie off hardware clear path
assign hw2reg.erase_suspend.d = 1'b0;
@@ -716,6 +719,9 @@
.clk_i,
.rst_ni,
+ // disable flash through memory protection
+ .flash_disable_i(flash_disable),
+
// arbiter interface selection
.if_sel_i(if_sel),
@@ -849,16 +855,23 @@
logic fatal_err;
assign fatal_err = |reg2hw.fault_status;
+ logic fatal_std_err;
+ assign fatal_std_err = |reg2hw.std_fault_status;
+
+ lc_ctrl_pkg::lc_tx_t local_esc;
+ assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
assign alert_srcs = { fatal_err,
+ fatal_std_err,
recov_err
};
assign alert_tests = { reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+ reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
};
- localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b0};
+ localparam logic [NumAlerts-1:0] IsFatal = {1'b1, 1'b1, 1'b0};
for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
prim_alert_sender #(
.AsyncOn(AlertAsyncOn[i]),
@@ -889,10 +902,13 @@
.lc_en_o(lc_escalate_en)
);
+ lc_ctrl_pkg::lc_tx_t escalate_en;
+ // SEC_CM: MEM.CTRL.LOCAL_ESC
+ assign escalate_en = lc_ctrl_pkg::lc_tx_or_hi(dis_access, local_esc);
+
// flash functional disable
- prim_mubi_pkg::mubi4_t flash_disable;
lc_ctrl_pkg::lc_tx_t lc_disable;
- assign lc_disable = lc_ctrl_pkg::lc_tx_or(lc_escalate_en, dis_access, lc_ctrl_pkg::On);
+ assign lc_disable = lc_ctrl_pkg::lc_tx_or_hi(lc_escalate_en, escalate_en);
// Normally, faults (those registered in fault_status) should also cause flash access
// to disable. However, most errors encountered by hardware during flash access
@@ -944,29 +960,34 @@
sw_ctrl_err.phy_err;
// all hardware interface errors are considered faults
+ // There are two types of faults
+ // standard faults - things like fsm / counter / tlul integrity
+ // custom faults - things like hardware interface not working correctly
assign hw2reg.fault_status.mp_err.d = 1'b1;
assign hw2reg.fault_status.rd_err.d = 1'b1;
assign hw2reg.fault_status.prog_win_err.d = 1'b1;
assign hw2reg.fault_status.prog_type_err.d = 1'b1;
assign hw2reg.fault_status.flash_phy_err.d = 1'b1;
- assign hw2reg.fault_status.reg_intg_err.d = 1'b1;
- assign hw2reg.fault_status.phy_intg_err.d = 1'b1;
- assign hw2reg.fault_status.lcmgr_err.d = 1'b1;
- assign hw2reg.fault_status.arb_fsm_err.d = 1'b1;
- assign hw2reg.fault_status.storage_err.d = 1'b1;
assign hw2reg.fault_status.seed_err.d = 1'b1;
assign hw2reg.fault_status.mp_err.de = hw_err.mp_err;
assign hw2reg.fault_status.rd_err.de = hw_err.rd_err;
assign hw2reg.fault_status.prog_win_err.de = hw_err.prog_win_err;
assign hw2reg.fault_status.prog_type_err.de = hw_err.prog_type_err;
assign hw2reg.fault_status.flash_phy_err.de = hw_err.phy_err;
- assign hw2reg.fault_status.reg_intg_err.de = intg_err;
- assign hw2reg.fault_status.phy_intg_err.de = flash_phy_rsp.intg_err;
- assign hw2reg.fault_status.lcmgr_err.de = lcmgr_err;
- assign hw2reg.fault_status.arb_fsm_err.de = arb_fsm_err;
- assign hw2reg.fault_status.storage_err.de = storage_err;
assign hw2reg.fault_status.seed_err.de = seed_err;
+ // standard faults
+ assign hw2reg.std_fault_status.reg_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.phy_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.lcmgr_err.d = 1'b1;
+ assign hw2reg.std_fault_status.arb_fsm_err.d = 1'b1;
+ assign hw2reg.std_fault_status.storage_err.d = 1'b1;
+ assign hw2reg.std_fault_status.reg_intg_err.de = intg_err;
+ assign hw2reg.std_fault_status.phy_intg_err.de = flash_phy_rsp.intg_err;
+ assign hw2reg.std_fault_status.lcmgr_err.de = lcmgr_err;
+ assign hw2reg.std_fault_status.arb_fsm_err.de = arb_fsm_err;
+ assign hw2reg.std_fault_status.storage_err.de = storage_err;
+
// Correctable ECC count / address
for (genvar i = 0; i < NumBanks; i++) begin : gen_ecc_single_err_reg
assign hw2reg.ecc_single_err_cnt[i].de = flash_phy_rsp.ecc_single_err[i];
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
index dcec542..b73db17 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
@@ -121,10 +121,10 @@
// Create steering logic
always_comb begin
unique case (tl_i.a_address[AW-1:0]) inside
- [384:387]: begin
+ [388:391]: begin
reg_steer = 0;
end
- [388:391]: begin
+ [392:395]: begin
reg_steer = 1;
end
default: begin
@@ -203,6 +203,7 @@
logic intr_test_corr_err_wd;
logic alert_test_we;
logic alert_test_recov_err_wd;
+ logic alert_test_fatal_std_err_wd;
logic alert_test_fatal_err_wd;
logic dis_we;
logic [3:0] dis_qs;
@@ -965,16 +966,16 @@
logic err_code_flash_phy_err_wd;
logic err_code_update_err_qs;
logic err_code_update_err_wd;
+ logic std_fault_status_reg_intg_err_qs;
+ logic std_fault_status_phy_intg_err_qs;
+ logic std_fault_status_lcmgr_err_qs;
+ logic std_fault_status_arb_fsm_err_qs;
+ logic std_fault_status_storage_err_qs;
logic fault_status_mp_err_qs;
logic fault_status_rd_err_qs;
logic fault_status_prog_win_err_qs;
logic fault_status_prog_type_err_qs;
logic fault_status_flash_phy_err_qs;
- logic fault_status_reg_intg_err_qs;
- logic fault_status_phy_intg_err_qs;
- logic fault_status_lcmgr_err_qs;
- logic fault_status_arb_fsm_err_qs;
- logic fault_status_storage_err_qs;
logic fault_status_seed_err_qs;
logic [19:0] err_addr_qs;
logic ecc_single_err_cnt_we;
@@ -1406,7 +1407,7 @@
// R[alert_test]: V(True)
logic alert_test_qe;
- logic [1:0] alert_test_flds_we;
+ logic [2:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
// F[recov_err]: 0:0
prim_subreg_ext #(
@@ -1423,7 +1424,22 @@
);
assign reg2hw.alert_test.recov_err.qe = alert_test_qe;
- // F[fatal_err]: 1:1
+ // F[fatal_std_err]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_std_err (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_std_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[1]),
+ .q (reg2hw.alert_test.fatal_std_err.q),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_std_err.qe = alert_test_qe;
+
+ // F[fatal_err]: 2:2
prim_subreg_ext #(
.DW (1)
) u_alert_test_fatal_err (
@@ -1432,7 +1448,7 @@
.wd (alert_test_fatal_err_wd),
.d ('0),
.qre (),
- .qe (alert_test_flds_we[1]),
+ .qe (alert_test_flds_we[2]),
.q (reg2hw.alert_test.fatal_err.q),
.qs ()
);
@@ -12103,6 +12119,133 @@
);
+ // R[std_fault_status]: V(False)
+ // F[reg_intg_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_reg_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.reg_intg_err.de),
+ .d (hw2reg.std_fault_status.reg_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.reg_intg_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_reg_intg_err_qs)
+ );
+
+ // F[phy_intg_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_phy_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.phy_intg_err.de),
+ .d (hw2reg.std_fault_status.phy_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.phy_intg_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_phy_intg_err_qs)
+ );
+
+ // F[lcmgr_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_lcmgr_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.lcmgr_err.de),
+ .d (hw2reg.std_fault_status.lcmgr_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.lcmgr_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_lcmgr_err_qs)
+ );
+
+ // F[arb_fsm_err]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_arb_fsm_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.arb_fsm_err.de),
+ .d (hw2reg.std_fault_status.arb_fsm_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.arb_fsm_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_arb_fsm_err_qs)
+ );
+
+ // F[storage_err]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_storage_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.storage_err.de),
+ .d (hw2reg.std_fault_status.storage_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.storage_err.q),
+
+ // to register interface (read)
+ .qs (std_fault_status_storage_err_qs)
+ );
+
+
// R[fault_status]: V(False)
// F[mp_err]: 1:1
prim_subreg #(
@@ -12229,132 +12372,7 @@
.qs (fault_status_flash_phy_err_qs)
);
- // F[reg_intg_err]: 6:6
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_reg_intg_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.reg_intg_err.de),
- .d (hw2reg.fault_status.reg_intg_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.reg_intg_err.q),
-
- // to register interface (read)
- .qs (fault_status_reg_intg_err_qs)
- );
-
- // F[phy_intg_err]: 7:7
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_phy_intg_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.phy_intg_err.de),
- .d (hw2reg.fault_status.phy_intg_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.phy_intg_err.q),
-
- // to register interface (read)
- .qs (fault_status_phy_intg_err_qs)
- );
-
- // F[lcmgr_err]: 8:8
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_lcmgr_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.lcmgr_err.de),
- .d (hw2reg.fault_status.lcmgr_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.lcmgr_err.q),
-
- // to register interface (read)
- .qs (fault_status_lcmgr_err_qs)
- );
-
- // F[arb_fsm_err]: 9:9
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_arb_fsm_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.arb_fsm_err.de),
- .d (hw2reg.fault_status.arb_fsm_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.arb_fsm_err.q),
-
- // to register interface (read)
- .qs (fault_status_arb_fsm_err_qs)
- );
-
- // F[storage_err]: 10:10
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRO),
- .RESVAL (1'h0)
- ) u_fault_status_storage_err (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (1'b0),
- .wd ('0),
-
- // from internal hardware
- .de (hw2reg.fault_status.storage_err.de),
- .d (hw2reg.fault_status.storage_err.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.fault_status.storage_err.q),
-
- // to register interface (read)
- .qs (fault_status_storage_err_qs)
- );
-
- // F[seed_err]: 11:11
+ // F[seed_err]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
@@ -12747,7 +12765,7 @@
- logic [95:0] addr_hit;
+ logic [96:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
@@ -12836,16 +12854,17 @@
addr_hit[83] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
addr_hit[84] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
addr_hit[85] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
- addr_hit[86] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
- addr_hit[87] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
- addr_hit[88] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
- addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
- addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
- addr_hit[91] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
- addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
- addr_hit[93] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
- addr_hit[94] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
- addr_hit[95] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+ addr_hit[86] = (reg_addr == FLASH_CTRL_STD_FAULT_STATUS_OFFSET);
+ addr_hit[87] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
+ addr_hit[88] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
+ addr_hit[89] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
+ addr_hit[90] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
+ addr_hit[91] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
+ addr_hit[92] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
+ addr_hit[93] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+ addr_hit[94] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[95] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[96] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -12948,7 +12967,8 @@
(addr_hit[92] & (|(FLASH_CTRL_CORE_PERMIT[92] & ~reg_be))) |
(addr_hit[93] & (|(FLASH_CTRL_CORE_PERMIT[93] & ~reg_be))) |
(addr_hit[94] & (|(FLASH_CTRL_CORE_PERMIT[94] & ~reg_be))) |
- (addr_hit[95] & (|(FLASH_CTRL_CORE_PERMIT[95] & ~reg_be)))));
+ (addr_hit[95] & (|(FLASH_CTRL_CORE_PERMIT[95] & ~reg_be))) |
+ (addr_hit[96] & (|(FLASH_CTRL_CORE_PERMIT[96] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -12993,7 +13013,9 @@
assign alert_test_recov_err_wd = reg_wdata[0];
- assign alert_test_fatal_err_wd = reg_wdata[1];
+ assign alert_test_fatal_std_err_wd = reg_wdata[1];
+
+ assign alert_test_fatal_err_wd = reg_wdata[2];
assign dis_we = addr_hit[4] & reg_we & !reg_error;
assign dis_wd = reg_wdata[3:0];
@@ -13749,25 +13771,25 @@
assign err_code_flash_phy_err_wd = reg_wdata[5];
assign err_code_update_err_wd = reg_wdata[6];
- assign ecc_single_err_cnt_we = addr_hit[88] & reg_we & !reg_error;
+ assign ecc_single_err_cnt_we = addr_hit[89] & reg_we & !reg_error;
assign ecc_single_err_cnt_ecc_single_err_cnt_0_wd = reg_wdata[7:0];
assign ecc_single_err_cnt_ecc_single_err_cnt_1_wd = reg_wdata[15:8];
- assign phy_alert_cfg_we = addr_hit[91] & reg_we & !reg_error;
+ assign phy_alert_cfg_we = addr_hit[92] & reg_we & !reg_error;
assign phy_alert_cfg_alert_ack_wd = reg_wdata[0];
assign phy_alert_cfg_alert_trig_wd = reg_wdata[1];
- assign scratch_we = addr_hit[93] & reg_we & !reg_error;
+ assign scratch_we = addr_hit[94] & reg_we & !reg_error;
assign scratch_wd = reg_wdata[31:0];
- assign fifo_lvl_we = addr_hit[94] & reg_we & !reg_error;
+ assign fifo_lvl_we = addr_hit[95] & reg_we & !reg_error;
assign fifo_lvl_prog_wd = reg_wdata[4:0];
assign fifo_lvl_rd_wd = reg_wdata[12:8];
- assign fifo_rst_we = addr_hit[95] & reg_we & !reg_error;
+ assign fifo_rst_we = addr_hit[96] & reg_we & !reg_error;
assign fifo_rst_wd = reg_wdata[0];
@@ -13805,6 +13827,7 @@
addr_hit[3]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
end
addr_hit[4]: begin
@@ -14379,57 +14402,60 @@
end
addr_hit[86]: begin
+ reg_rdata_next[0] = std_fault_status_reg_intg_err_qs;
+ reg_rdata_next[1] = std_fault_status_phy_intg_err_qs;
+ reg_rdata_next[2] = std_fault_status_lcmgr_err_qs;
+ reg_rdata_next[3] = std_fault_status_arb_fsm_err_qs;
+ reg_rdata_next[4] = std_fault_status_storage_err_qs;
+ end
+
+ addr_hit[87]: begin
reg_rdata_next[1] = fault_status_mp_err_qs;
reg_rdata_next[2] = fault_status_rd_err_qs;
reg_rdata_next[3] = fault_status_prog_win_err_qs;
reg_rdata_next[4] = fault_status_prog_type_err_qs;
reg_rdata_next[5] = fault_status_flash_phy_err_qs;
- reg_rdata_next[6] = fault_status_reg_intg_err_qs;
- reg_rdata_next[7] = fault_status_phy_intg_err_qs;
- reg_rdata_next[8] = fault_status_lcmgr_err_qs;
- reg_rdata_next[9] = fault_status_arb_fsm_err_qs;
- reg_rdata_next[10] = fault_status_storage_err_qs;
- reg_rdata_next[11] = fault_status_seed_err_qs;
- end
-
- addr_hit[87]: begin
- reg_rdata_next[19:0] = err_addr_qs;
+ reg_rdata_next[6] = fault_status_seed_err_qs;
end
addr_hit[88]: begin
+ reg_rdata_next[19:0] = err_addr_qs;
+ end
+
+ addr_hit[89]: begin
reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
end
- addr_hit[89]: begin
+ addr_hit[90]: begin
reg_rdata_next[19:0] = ecc_single_err_addr_0_qs;
end
- addr_hit[90]: begin
+ addr_hit[91]: begin
reg_rdata_next[19:0] = ecc_single_err_addr_1_qs;
end
- addr_hit[91]: begin
+ addr_hit[92]: begin
reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
end
- addr_hit[92]: begin
+ addr_hit[93]: begin
reg_rdata_next[0] = phy_status_init_wip_qs;
reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
end
- addr_hit[93]: begin
+ addr_hit[94]: begin
reg_rdata_next[31:0] = scratch_qs;
end
- addr_hit[94]: begin
+ addr_hit[95]: begin
reg_rdata_next[4:0] = fifo_lvl_prog_qs;
reg_rdata_next[12:8] = fifo_lvl_rd_qs;
end
- addr_hit[95]: begin
+ addr_hit[96]: begin
reg_rdata_next[0] = fifo_rst_qs;
end
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
index 51775b7..688e7b2 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -22,7 +22,7 @@
parameter int BytesPerPage = 2048;
parameter int BytesPerBank = 524288;
parameter int unsigned ExecEn = 32'ha26a38f7;
- parameter int NumAlerts = 2;
+ parameter int NumAlerts = 3;
// Address widths within the block
parameter int CoreAw = 9;
@@ -110,6 +110,10 @@
struct packed {
logic q;
logic qe;
+ } fatal_std_err;
+ struct packed {
+ logic q;
+ logic qe;
} fatal_err;
} flash_ctrl_reg2hw_alert_test_reg_t;
@@ -484,21 +488,6 @@
typedef struct packed {
struct packed {
logic q;
- } mp_err;
- struct packed {
- logic q;
- } rd_err;
- struct packed {
- logic q;
- } prog_win_err;
- struct packed {
- logic q;
- } prog_type_err;
- struct packed {
- logic q;
- } flash_phy_err;
- struct packed {
- logic q;
} reg_intg_err;
struct packed {
logic q;
@@ -512,6 +501,24 @@
struct packed {
logic q;
} storage_err;
+ } flash_ctrl_reg2hw_std_fault_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } mp_err;
+ struct packed {
+ logic q;
+ } rd_err;
+ struct packed {
+ logic q;
+ } prog_win_err;
+ struct packed {
+ logic q;
+ } prog_type_err;
+ struct packed {
+ logic q;
+ } flash_phy_err;
struct packed {
logic q;
} seed_err;
@@ -655,26 +662,6 @@
struct packed {
logic d;
logic de;
- } mp_err;
- struct packed {
- logic d;
- logic de;
- } rd_err;
- struct packed {
- logic d;
- logic de;
- } prog_win_err;
- struct packed {
- logic d;
- logic de;
- } prog_type_err;
- struct packed {
- logic d;
- logic de;
- } flash_phy_err;
- struct packed {
- logic d;
- logic de;
} reg_intg_err;
struct packed {
logic d;
@@ -692,6 +679,29 @@
logic d;
logic de;
} storage_err;
+ } flash_ctrl_hw2reg_std_fault_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } flash_phy_err;
struct packed {
logic d;
logic de;
@@ -730,10 +740,10 @@
// Register -> HW type for core interface
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [577:572]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [571:566]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [565:554]
- flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [553:550]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [579:574]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [573:568]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [567:556]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [555:550]
flash_ctrl_reg2hw_dis_reg_t dis; // [549:546]
flash_ctrl_reg2hw_exec_reg_t exec; // [545:514]
flash_ctrl_reg2hw_init_reg_t init; // [513:513]
@@ -756,7 +766,8 @@
flash_ctrl_reg2hw_bank1_info2_page_cfg_shadowed_mreg_t [1:0]
bank1_info2_page_cfg_shadowed; // [87:74]
flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t [1:0] mp_bank_cfg_shadowed; // [73:72]
- flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [71:61]
+ flash_ctrl_reg2hw_std_fault_status_reg_t std_fault_status; // [71:67]
+ flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [66:61]
flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [60:45]
flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
@@ -773,7 +784,8 @@
flash_ctrl_hw2reg_op_status_reg_t op_status; // [134:131]
flash_ctrl_hw2reg_status_reg_t status; // [130:121]
flash_ctrl_hw2reg_err_code_reg_t err_code; // [120:109]
- flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [108:87]
+ flash_ctrl_hw2reg_std_fault_status_reg_t std_fault_status; // [108:99]
+ flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [98:87]
flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [86:66]
flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [65:48]
flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [47:6]
@@ -867,16 +879,17 @@
parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 14c;
parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 150;
parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 154;
- parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 158;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 15c;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 160;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 164;
- parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 168;
- parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 16c;
- parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 170;
- parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 174;
- parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 178;
- parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 17c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STD_FAULT_STATUS_OFFSET = 9'h 158;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 15c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 160;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 164;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 168;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 16c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 170;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 174;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 178;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 17c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 180;
// Reset values for hwext registers and their fields for core interface
parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h 0;
@@ -886,16 +899,17 @@
parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
- parameter logic [1:0] FLASH_CTRL_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [2:0] FLASH_CTRL_ALERT_TEST_RESVAL = 3'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
// Window parameters for core interface
- parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 180;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 184;
parameter int unsigned FLASH_CTRL_PROG_FIFO_SIZE = 'h 4;
- parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 184;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 188;
parameter int unsigned FLASH_CTRL_RD_FIFO_SIZE = 'h 4;
// Register index for core interface
@@ -986,6 +1000,7 @@
FLASH_CTRL_OP_STATUS,
FLASH_CTRL_STATUS,
FLASH_CTRL_ERR_CODE,
+ FLASH_CTRL_STD_FAULT_STATUS,
FLASH_CTRL_FAULT_STATUS,
FLASH_CTRL_ERR_ADDR,
FLASH_CTRL_ECC_SINGLE_ERR_CNT,
@@ -999,7 +1014,7 @@
} flash_ctrl_core_id_e;
// Register width information to check illegal writes for core interface
- parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [96] = '{
+ parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [97] = '{
4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
@@ -1086,16 +1101,17 @@
4'b 0001, // index[83] FLASH_CTRL_OP_STATUS
4'b 0001, // index[84] FLASH_CTRL_STATUS
4'b 0001, // index[85] FLASH_CTRL_ERR_CODE
- 4'b 0011, // index[86] FLASH_CTRL_FAULT_STATUS
- 4'b 0111, // index[87] FLASH_CTRL_ERR_ADDR
- 4'b 0011, // index[88] FLASH_CTRL_ECC_SINGLE_ERR_CNT
- 4'b 0111, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
- 4'b 0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
- 4'b 0001, // index[91] FLASH_CTRL_PHY_ALERT_CFG
- 4'b 0001, // index[92] FLASH_CTRL_PHY_STATUS
- 4'b 1111, // index[93] FLASH_CTRL_SCRATCH
- 4'b 0011, // index[94] FLASH_CTRL_FIFO_LVL
- 4'b 0001 // index[95] FLASH_CTRL_FIFO_RST
+ 4'b 0001, // index[86] FLASH_CTRL_STD_FAULT_STATUS
+ 4'b 0001, // index[87] FLASH_CTRL_FAULT_STATUS
+ 4'b 0111, // index[88] FLASH_CTRL_ERR_ADDR
+ 4'b 0011, // index[89] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+ 4'b 0111, // index[90] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+ 4'b 0111, // index[91] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+ 4'b 0001, // index[92] FLASH_CTRL_PHY_ALERT_CFG
+ 4'b 0001, // index[93] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[94] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[95] FLASH_CTRL_FIFO_LVL
+ 4'b 0001 // index[96] FLASH_CTRL_FIFO_RST
};
endpackage
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
index 925e309..12082e0 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -33,7 +33,7 @@
{ name: "NAlerts",
desc: "Number of alert channels.",
type: "int",
- default: "60",
+ default: "61",
local: "true"
},
{ name: "NLpg",
@@ -82,6 +82,7 @@
5'd16,
5'd16,
5'd16,
+ 5'd16,
5'd11,
5'd15,
5'd15,
@@ -198,6 +199,7 @@
1'b1,
1'b1,
1'b1,
+ 1'b1,
1'b1
}
'''
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
index f745625..7f34867 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
@@ -5,7 +5,7 @@
instance_name: top_earlgrey_alert_handler
param_values:
{
- n_alerts: 60
+ n_alerts: 61
esc_cnt_dw: 32
accu_cnt_dw: 16
async_on:
@@ -70,6 +70,7 @@
1'b1
1'b1
1'b1
+ 1'b1
]
n_classes: 4
n_lpg: 20
@@ -111,6 +112,7 @@
5'd16
5'd16
5'd16
+ 5'd16
5'd17
5'd18
5'd18
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
index 3989fbc..46cd96a 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
@@ -7,7 +7,7 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 60;
+ parameter int NAlerts = 61;
parameter int NLpg = 20;
parameter int NLpgWidth = 5;
parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = {
@@ -38,6 +38,7 @@
5'd16,
5'd16,
5'd16,
+ 5'd16,
5'd11,
5'd15,
5'd15,
@@ -134,6 +135,7 @@
1'b1,
1'b1,
1'b1,
+ 1'b1,
1'b1
};
parameter int N_CLASSES = 4;
@@ -763,15 +765,15 @@
// Register -> HW type
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [1136:1133]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1132:1129]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [1128:1121]
- alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1120:1105]
- alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1104:1104]
- alert_handler_reg2hw_alert_regwen_mreg_t [59:0] alert_regwen; // [1103:1044]
- alert_handler_reg2hw_alert_en_shadowed_mreg_t [59:0] alert_en_shadowed; // [1043:984]
- alert_handler_reg2hw_alert_class_shadowed_mreg_t [59:0] alert_class_shadowed; // [983:864]
- alert_handler_reg2hw_alert_cause_mreg_t [59:0] alert_cause; // [863:804]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [1141:1138]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1137:1134]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [1133:1126]
+ alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1125:1110]
+ alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1109:1109]
+ alert_handler_reg2hw_alert_regwen_mreg_t [60:0] alert_regwen; // [1108:1048]
+ alert_handler_reg2hw_alert_en_shadowed_mreg_t [60:0] alert_en_shadowed; // [1047:987]
+ alert_handler_reg2hw_alert_class_shadowed_mreg_t [60:0] alert_class_shadowed; // [986:865]
+ alert_handler_reg2hw_alert_cause_mreg_t [60:0] alert_cause; // [864:804]
alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797]
alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0]
loc_alert_class_shadowed; // [796:783]
@@ -824,8 +826,8 @@
// HW -> register type
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [353:346]
- alert_handler_hw2reg_alert_cause_mreg_t [59:0] alert_cause; // [345:226]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [355:348]
+ alert_handler_hw2reg_alert_cause_mreg_t [60:0] alert_cause; // [347:226]
alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212]
alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -912,270 +914,274 @@
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_59_OFFSET = 11'h 104;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 108;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 10c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 110;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 114;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 118;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 11c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 120;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 124;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 128;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 12c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 130;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 134;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 138;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 13c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 140;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 144;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 148;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 14c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 150;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 154;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 158;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 15c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 160;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 164;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 168;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 16c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 170;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 174;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 178;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 17c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 180;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 184;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 188;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 18c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 190;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 194;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 198;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 19c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 1f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 1f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 1f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 1fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 200;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 204;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 208;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 20c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 210;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 214;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 218;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 21c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 220;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 224;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 228;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 22c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 230;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 234;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 238;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 23c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 240;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 244;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 248;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 24c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 250;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 254;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 258;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 25c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 260;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 264;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 268;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 26c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 270;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 274;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 278;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 27c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 280;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 284;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 288;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 28c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 290;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 294;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 298;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 29c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 2e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 2e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 2e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 2ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 2f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 2f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 2f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 2fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 300;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 304;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 308;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 30c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 310;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 314;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 318;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 31c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 320;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 324;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 328;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 32c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 330;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 334;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 338;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 33c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 340;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 344;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 348;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 34c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 350;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 354;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 358;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 35c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 360;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 364;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 368;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 36c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 370;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 374;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 378;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 37c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 380;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 384;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 388;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 38c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 390;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 394;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 398;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 39c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 3d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 3d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 3d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 3dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 3e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 3e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 3e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 3ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 3f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 3f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 3f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 3fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 400;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 404;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 408;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 40c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 410;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 414;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 418;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 41c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 420;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 424;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 428;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 42c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 430;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 434;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 438;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 43c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 440;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 444;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 448;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 44c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 450;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 454;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 458;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 45c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 460;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 464;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 468;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 46c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 470;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 474;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 478;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 47c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 480;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 484;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 488;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 48c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 490;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 494;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 498;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 49c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 4e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 4ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 4f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 4f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 4f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 4fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 500;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 504;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 508;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 50c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 510;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 514;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 518;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 51c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 520;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 524;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 10c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 110;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 114;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 118;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 11c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 120;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 124;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 128;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 12c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 130;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 134;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 138;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 13c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 140;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 144;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 148;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 14c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 150;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 154;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 158;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 15c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 160;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 164;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 168;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 16c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 170;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 174;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 178;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 17c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 180;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 184;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 188;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 18c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 190;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 194;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 198;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 19c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 1f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 1f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 1fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 200;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 204;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 208;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 20c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 210;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 214;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 218;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 21c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 220;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 224;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 228;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 22c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 230;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 234;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 238;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 23c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 240;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 244;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 248;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 24c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 250;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 254;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 258;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 25c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 260;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 264;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 268;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 26c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 270;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 274;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 278;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 27c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 280;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 284;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 288;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 28c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 290;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 294;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 298;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 29c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 2a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 2a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 2a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 2ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 2e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 2ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 2f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 2f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 2f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 2fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 300;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 304;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 308;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 30c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 310;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 314;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 318;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 31c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 320;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 324;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 328;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 32c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 330;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 334;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 338;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 33c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 340;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 344;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 348;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 34c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 350;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 354;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 358;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 35c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 360;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 364;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 368;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 36c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 370;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 374;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 378;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 37c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 380;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 384;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 388;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 38c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 390;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 394;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 398;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 39c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 3dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 3e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 3e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 3e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 3ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 3f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 3f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 3f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 3fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 400;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 404;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 408;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 40c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 410;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 414;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 418;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 41c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 420;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 424;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 428;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 42c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 430;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 434;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 438;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 43c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 440;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 444;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 448;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 44c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 450;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 454;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 458;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 45c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 460;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 464;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 468;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 46c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 470;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 474;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 478;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 47c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 480;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 484;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 488;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 48c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 490;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 494;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 498;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 49c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 4f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 4fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 500;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 504;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 508;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 50c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 510;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 514;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 518;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 51c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 520;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 524;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 528;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 52c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 530;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 534;
// Reset values for hwext registers and their fields
parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -1264,6 +1270,7 @@
ALERT_HANDLER_ALERT_REGWEN_57,
ALERT_HANDLER_ALERT_REGWEN_58,
ALERT_HANDLER_ALERT_REGWEN_59,
+ ALERT_HANDLER_ALERT_REGWEN_60,
ALERT_HANDLER_ALERT_EN_SHADOWED_0,
ALERT_HANDLER_ALERT_EN_SHADOWED_1,
ALERT_HANDLER_ALERT_EN_SHADOWED_2,
@@ -1324,6 +1331,7 @@
ALERT_HANDLER_ALERT_EN_SHADOWED_57,
ALERT_HANDLER_ALERT_EN_SHADOWED_58,
ALERT_HANDLER_ALERT_EN_SHADOWED_59,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_60,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_0,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_1,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_2,
@@ -1384,6 +1392,7 @@
ALERT_HANDLER_ALERT_CLASS_SHADOWED_57,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_58,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_59,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_60,
ALERT_HANDLER_ALERT_CAUSE_0,
ALERT_HANDLER_ALERT_CAUSE_1,
ALERT_HANDLER_ALERT_CAUSE_2,
@@ -1444,6 +1453,7 @@
ALERT_HANDLER_ALERT_CAUSE_57,
ALERT_HANDLER_ALERT_CAUSE_58,
ALERT_HANDLER_ALERT_CAUSE_59,
+ ALERT_HANDLER_ALERT_CAUSE_60,
ALERT_HANDLER_LOC_ALERT_REGWEN_0,
ALERT_HANDLER_LOC_ALERT_REGWEN_1,
ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1531,7 +1541,7 @@
} alert_handler_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ALERT_HANDLER_PERMIT [330] = '{
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [334] = '{
4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
@@ -1598,270 +1608,274 @@
4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57
4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58
4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_REGWEN_59
- 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_SHADOWED_0
- 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_SHADOWED_1
- 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_SHADOWED_2
- 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_3
- 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_4
- 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_5
- 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_6
- 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_7
- 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_8
- 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_9
- 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_10
- 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_11
- 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_12
- 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_13
- 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_14
- 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_15
- 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_16
- 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_17
- 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_18
- 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_19
- 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_20
- 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_21
- 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_22
- 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_23
- 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_24
- 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_25
- 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_26
- 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_27
- 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_28
- 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_29
- 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_30
- 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_31
- 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_32
- 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_33
- 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_34
- 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_35
- 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_36
- 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_37
- 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_38
- 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_39
- 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_40
- 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_41
- 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_42
- 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_43
- 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_44
- 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_45
- 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_46
- 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_47
- 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_48
- 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_49
- 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_50
- 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_51
- 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_52
- 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_53
- 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_54
- 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_55
- 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_56
- 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_57
- 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_58
- 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_59
- 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
- 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
- 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
- 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
- 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
- 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
- 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
- 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
- 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
- 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
- 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
- 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
- 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
- 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
- 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
- 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
- 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
- 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
- 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
- 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
- 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
- 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
- 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
- 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
- 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
- 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
- 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
- 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
- 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
- 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
- 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
- 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
- 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
- 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
- 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
- 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
- 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
- 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
- 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
- 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
- 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
- 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
- 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
- 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
- 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
- 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
- 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
- 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
- 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
- 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
- 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
- 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
- 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
- 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
- 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
- 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
- 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
- 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
- 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
- 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59
- 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_0
- 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_1
- 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_2
- 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_3
- 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_4
- 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_5
- 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_6
- 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_7
- 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_8
- 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_9
- 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_10
- 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_11
- 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_12
- 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_13
- 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_14
- 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_15
- 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_16
- 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_17
- 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_18
- 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_19
- 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_20
- 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_21
- 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_22
- 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_23
- 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_24
- 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_25
- 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_26
- 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_27
- 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_28
- 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_29
- 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_30
- 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_31
- 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_32
- 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_33
- 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_34
- 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_35
- 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_36
- 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_37
- 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_38
- 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_39
- 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_40
- 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_41
- 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_42
- 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_43
- 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_44
- 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_45
- 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_46
- 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_47
- 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_48
- 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_49
- 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_50
- 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_51
- 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_52
- 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_53
- 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_54
- 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_55
- 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_56
- 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_57
- 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_58
- 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_59
- 4'b 0001, // index[246] ALERT_HANDLER_LOC_ALERT_REGWEN_0
- 4'b 0001, // index[247] ALERT_HANDLER_LOC_ALERT_REGWEN_1
- 4'b 0001, // index[248] ALERT_HANDLER_LOC_ALERT_REGWEN_2
- 4'b 0001, // index[249] ALERT_HANDLER_LOC_ALERT_REGWEN_3
- 4'b 0001, // index[250] ALERT_HANDLER_LOC_ALERT_REGWEN_4
- 4'b 0001, // index[251] ALERT_HANDLER_LOC_ALERT_REGWEN_5
- 4'b 0001, // index[252] ALERT_HANDLER_LOC_ALERT_REGWEN_6
- 4'b 0001, // index[253] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
- 4'b 0001, // index[254] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
- 4'b 0001, // index[255] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
- 4'b 0001, // index[256] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
- 4'b 0001, // index[257] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
- 4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
- 4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
- 4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
- 4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
- 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
- 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
- 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
- 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
- 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
- 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_CAUSE_0
- 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_CAUSE_1
- 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_CAUSE_2
- 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_CAUSE_3
- 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_CAUSE_4
- 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_CAUSE_5
- 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_CAUSE_6
- 4'b 0001, // index[274] ALERT_HANDLER_CLASSA_REGWEN
- 4'b 0011, // index[275] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
- 4'b 0001, // index[276] ALERT_HANDLER_CLASSA_CLR_REGWEN
- 4'b 0001, // index[277] ALERT_HANDLER_CLASSA_CLR_SHADOWED
- 4'b 0011, // index[278] ALERT_HANDLER_CLASSA_ACCUM_CNT
- 4'b 0011, // index[279] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[280] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[281] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[282] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[283] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[284] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[285] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[286] ALERT_HANDLER_CLASSA_ESC_CNT
- 4'b 0001, // index[287] ALERT_HANDLER_CLASSA_STATE
- 4'b 0001, // index[288] ALERT_HANDLER_CLASSB_REGWEN
- 4'b 0011, // index[289] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
- 4'b 0001, // index[290] ALERT_HANDLER_CLASSB_CLR_REGWEN
- 4'b 0001, // index[291] ALERT_HANDLER_CLASSB_CLR_SHADOWED
- 4'b 0011, // index[292] ALERT_HANDLER_CLASSB_ACCUM_CNT
- 4'b 0011, // index[293] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[294] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[295] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[296] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[297] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[298] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[299] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[300] ALERT_HANDLER_CLASSB_ESC_CNT
- 4'b 0001, // index[301] ALERT_HANDLER_CLASSB_STATE
- 4'b 0001, // index[302] ALERT_HANDLER_CLASSC_REGWEN
- 4'b 0011, // index[303] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
- 4'b 0001, // index[304] ALERT_HANDLER_CLASSC_CLR_REGWEN
- 4'b 0001, // index[305] ALERT_HANDLER_CLASSC_CLR_SHADOWED
- 4'b 0011, // index[306] ALERT_HANDLER_CLASSC_ACCUM_CNT
- 4'b 0011, // index[307] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[308] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[309] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[310] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[311] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[312] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[313] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[314] ALERT_HANDLER_CLASSC_ESC_CNT
- 4'b 0001, // index[315] ALERT_HANDLER_CLASSC_STATE
- 4'b 0001, // index[316] ALERT_HANDLER_CLASSD_REGWEN
- 4'b 0011, // index[317] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
- 4'b 0001, // index[318] ALERT_HANDLER_CLASSD_CLR_REGWEN
- 4'b 0001, // index[319] ALERT_HANDLER_CLASSD_CLR_SHADOWED
- 4'b 0011, // index[320] ALERT_HANDLER_CLASSD_ACCUM_CNT
- 4'b 0011, // index[321] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[322] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[323] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[324] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[325] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[326] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[327] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[328] ALERT_HANDLER_CLASSD_ESC_CNT
- 4'b 0001 // index[329] ALERT_HANDLER_CLASSD_STATE
+ 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60
+ 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_SHADOWED_0
+ 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_SHADOWED_1
+ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_2
+ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_3
+ 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_4
+ 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_5
+ 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_6
+ 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_7
+ 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_8
+ 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_9
+ 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_10
+ 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_11
+ 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_12
+ 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_13
+ 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_14
+ 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_15
+ 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_16
+ 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_17
+ 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_18
+ 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_19
+ 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_20
+ 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_21
+ 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_22
+ 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_23
+ 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_24
+ 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_25
+ 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_26
+ 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_27
+ 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_28
+ 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_29
+ 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_30
+ 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_31
+ 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_32
+ 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_33
+ 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_34
+ 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_35
+ 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_36
+ 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_37
+ 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_38
+ 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_39
+ 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_40
+ 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_41
+ 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_42
+ 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_43
+ 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_44
+ 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_45
+ 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_46
+ 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_47
+ 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_48
+ 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_49
+ 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_50
+ 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_51
+ 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_52
+ 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_53
+ 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_54
+ 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_55
+ 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_56
+ 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_57
+ 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_58
+ 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_59
+ 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_60
+ 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
+ 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
+ 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
+ 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
+ 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
+ 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
+ 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
+ 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
+ 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
+ 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
+ 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
+ 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
+ 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
+ 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
+ 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
+ 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
+ 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
+ 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
+ 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
+ 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
+ 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
+ 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
+ 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
+ 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
+ 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
+ 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
+ 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
+ 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
+ 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
+ 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
+ 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
+ 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
+ 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
+ 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
+ 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
+ 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
+ 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
+ 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
+ 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
+ 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
+ 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
+ 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
+ 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
+ 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
+ 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
+ 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
+ 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
+ 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
+ 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
+ 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
+ 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
+ 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
+ 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
+ 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
+ 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
+ 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
+ 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
+ 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
+ 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
+ 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59
+ 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60
+ 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_0
+ 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_1
+ 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_2
+ 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_3
+ 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_4
+ 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_5
+ 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_6
+ 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_7
+ 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_8
+ 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_9
+ 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_10
+ 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_11
+ 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_12
+ 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_13
+ 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_14
+ 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_15
+ 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_16
+ 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_17
+ 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_18
+ 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_19
+ 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_20
+ 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_21
+ 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_22
+ 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_23
+ 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_24
+ 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_25
+ 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_26
+ 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_27
+ 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_28
+ 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_29
+ 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_30
+ 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_31
+ 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_32
+ 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_33
+ 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_34
+ 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_35
+ 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_36
+ 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_37
+ 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_38
+ 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_39
+ 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_40
+ 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_41
+ 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_42
+ 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_43
+ 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_44
+ 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_45
+ 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_46
+ 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_47
+ 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_48
+ 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_49
+ 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_50
+ 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_51
+ 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_52
+ 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_53
+ 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_54
+ 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_55
+ 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_56
+ 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_57
+ 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_58
+ 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_59
+ 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_60
+ 4'b 0001, // index[250] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+ 4'b 0001, // index[251] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+ 4'b 0001, // index[252] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+ 4'b 0001, // index[253] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+ 4'b 0001, // index[254] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+ 4'b 0001, // index[255] ALERT_HANDLER_LOC_ALERT_REGWEN_5
+ 4'b 0001, // index[256] ALERT_HANDLER_LOC_ALERT_REGWEN_6
+ 4'b 0001, // index[257] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
+ 4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
+ 4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
+ 4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
+ 4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
+ 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
+ 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
+ 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
+ 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
+ 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
+ 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
+ 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
+ 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
+ 4'b 0001, // index[270] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
+ 4'b 0001, // index[271] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+ 4'b 0001, // index[272] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+ 4'b 0001, // index[273] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+ 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+ 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+ 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_CAUSE_5
+ 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_CAUSE_6
+ 4'b 0001, // index[278] ALERT_HANDLER_CLASSA_REGWEN
+ 4'b 0011, // index[279] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
+ 4'b 0001, // index[280] ALERT_HANDLER_CLASSA_CLR_REGWEN
+ 4'b 0001, // index[281] ALERT_HANDLER_CLASSA_CLR_SHADOWED
+ 4'b 0011, // index[282] ALERT_HANDLER_CLASSA_ACCUM_CNT
+ 4'b 0011, // index[283] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[284] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[285] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[286] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[287] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[288] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[289] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[290] ALERT_HANDLER_CLASSA_ESC_CNT
+ 4'b 0001, // index[291] ALERT_HANDLER_CLASSA_STATE
+ 4'b 0001, // index[292] ALERT_HANDLER_CLASSB_REGWEN
+ 4'b 0011, // index[293] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
+ 4'b 0001, // index[294] ALERT_HANDLER_CLASSB_CLR_REGWEN
+ 4'b 0001, // index[295] ALERT_HANDLER_CLASSB_CLR_SHADOWED
+ 4'b 0011, // index[296] ALERT_HANDLER_CLASSB_ACCUM_CNT
+ 4'b 0011, // index[297] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[298] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[299] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[300] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[301] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[302] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[303] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[304] ALERT_HANDLER_CLASSB_ESC_CNT
+ 4'b 0001, // index[305] ALERT_HANDLER_CLASSB_STATE
+ 4'b 0001, // index[306] ALERT_HANDLER_CLASSC_REGWEN
+ 4'b 0011, // index[307] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
+ 4'b 0001, // index[308] ALERT_HANDLER_CLASSC_CLR_REGWEN
+ 4'b 0001, // index[309] ALERT_HANDLER_CLASSC_CLR_SHADOWED
+ 4'b 0011, // index[310] ALERT_HANDLER_CLASSC_ACCUM_CNT
+ 4'b 0011, // index[311] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[312] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[313] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[314] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[315] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[316] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[317] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[318] ALERT_HANDLER_CLASSC_ESC_CNT
+ 4'b 0001, // index[319] ALERT_HANDLER_CLASSC_STATE
+ 4'b 0001, // index[320] ALERT_HANDLER_CLASSD_REGWEN
+ 4'b 0011, // index[321] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
+ 4'b 0001, // index[322] ALERT_HANDLER_CLASSD_CLR_REGWEN
+ 4'b 0001, // index[323] ALERT_HANDLER_CLASSD_CLR_SHADOWED
+ 4'b 0011, // index[324] ALERT_HANDLER_CLASSD_ACCUM_CNT
+ 4'b 0011, // index[325] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[326] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[327] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[328] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[329] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[330] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[331] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[332] ALERT_HANDLER_CLASSD_ESC_CNT
+ 4'b 0001 // index[333] ALERT_HANDLER_CLASSD_STATE
};
endpackage
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
index a4f49a5..83b3712 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
@@ -323,6 +323,9 @@
logic alert_regwen_59_we;
logic alert_regwen_59_qs;
logic alert_regwen_59_wd;
+ logic alert_regwen_60_we;
+ logic alert_regwen_60_qs;
+ logic alert_regwen_60_wd;
logic alert_en_shadowed_0_re;
logic alert_en_shadowed_0_we;
logic alert_en_shadowed_0_qs;
@@ -563,6 +566,10 @@
logic alert_en_shadowed_59_we;
logic alert_en_shadowed_59_qs;
logic alert_en_shadowed_59_wd;
+ logic alert_en_shadowed_60_re;
+ logic alert_en_shadowed_60_we;
+ logic alert_en_shadowed_60_qs;
+ logic alert_en_shadowed_60_wd;
logic alert_class_shadowed_0_re;
logic alert_class_shadowed_0_we;
logic [1:0] alert_class_shadowed_0_qs;
@@ -803,6 +810,10 @@
logic alert_class_shadowed_59_we;
logic [1:0] alert_class_shadowed_59_qs;
logic [1:0] alert_class_shadowed_59_wd;
+ logic alert_class_shadowed_60_re;
+ logic alert_class_shadowed_60_we;
+ logic [1:0] alert_class_shadowed_60_qs;
+ logic [1:0] alert_class_shadowed_60_wd;
logic alert_cause_0_we;
logic alert_cause_0_qs;
logic alert_cause_0_wd;
@@ -983,6 +994,9 @@
logic alert_cause_59_we;
logic alert_cause_59_qs;
logic alert_cause_59_wd;
+ logic alert_cause_60_we;
+ logic alert_cause_60_qs;
+ logic alert_cause_60_wd;
logic loc_alert_regwen_0_we;
logic loc_alert_regwen_0_qs;
logic loc_alert_regwen_0_wd;
@@ -3332,6 +3346,33 @@
);
+ // Subregister 60 of Multireg alert_regwen
+ // R[alert_regwen_60]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_60_we),
+ .wd (alert_regwen_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[60].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_60_qs)
+ );
+
+
// Subregister 0 of Multireg alert_en_shadowed
// R[alert_en_shadowed_0]: V(False)
prim_subreg_shadow #(
@@ -5492,6 +5533,42 @@
);
+ // Subregister 60 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_60]: V(False)
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_60_re),
+ .we (alert_en_shadowed_60_we & alert_regwen_60_qs),
+ .wd (alert_en_shadowed_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[60].q),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_60_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.alert_en_shadowed[60].err_update),
+ .err_storage (reg2hw.alert_en_shadowed[60].err_storage)
+ );
+
+
// Subregister 0 of Multireg alert_class_shadowed
// R[alert_class_shadowed_0]: V(False)
prim_subreg_shadow #(
@@ -7652,6 +7729,42 @@
);
+ // Subregister 60 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_60]: V(False)
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_60_re),
+ .we (alert_class_shadowed_60_we & alert_regwen_60_qs),
+ .wd (alert_class_shadowed_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[60].q),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_60_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.alert_class_shadowed[60].err_update),
+ .err_storage (reg2hw.alert_class_shadowed[60].err_storage)
+ );
+
+
// Subregister 0 of Multireg alert_cause
// R[alert_cause_0]: V(False)
prim_subreg #(
@@ -9272,6 +9385,33 @@
);
+ // Subregister 60 of Multireg alert_cause
+ // R[alert_cause_60]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_60_we),
+ .wd (alert_cause_60_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[60].de),
+ .d (hw2reg.alert_cause[60].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[60].q),
+
+ // to register interface (read)
+ .qs (alert_cause_60_qs)
+ );
+
+
// Subregister 0 of Multireg loc_alert_regwen
// R[loc_alert_regwen_0]: V(False)
prim_subreg #(
@@ -13079,7 +13219,7 @@
- logic [329:0] addr_hit;
+ logic [333:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -13148,270 +13288,274 @@
addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET);
addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET);
addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_59_OFFSET);
- addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
- addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
- addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
- addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
- addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
- addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
- addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
- addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
- addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
- addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
- addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
- addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
- addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
- addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
- addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
- addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
- addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
- addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
- addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
- addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
- addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
- addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
- addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
- addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
- addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
- addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
- addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
- addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
- addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
- addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
- addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
- addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
- addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
- addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
- addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
- addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
- addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
- addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
- addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
- addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
- addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
- addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
- addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
- addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
- addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
- addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
- addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
- addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
- addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
- addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
- addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
- addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
- addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
- addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
- addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
- addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
- addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
- addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
- addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
- addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
- addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
- addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
- addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
- addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
- addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
- addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
- addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
- addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
- addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
- addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
- addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
- addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
- addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
- addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
- addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
- addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
- addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
- addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
- addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
- addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
- addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
- addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
- addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
- addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
- addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
- addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
- addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
- addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
- addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
- addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
- addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
- addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
- addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
- addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
- addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
- addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
- addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
- addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
- addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
- addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
- addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
- addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
- addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
- addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
- addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
- addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
- addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
- addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
- addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
- addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
- addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
- addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
- addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
- addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
- addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
- addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
- addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
- addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
- addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
- addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
- addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
- addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
- addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
- addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
- addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
- addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
- addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
- addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
- addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
- addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
- addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
- addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
- addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
- addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
- addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
- addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
- addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
- addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
- addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
- addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
- addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
- addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
- addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
- addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
- addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
- addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
- addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
- addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
- addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
- addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
- addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
- addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
- addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
- addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
- addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
- addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
- addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
- addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
- addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
- addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
- addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
- addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
- addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
- addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
- addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
- addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
- addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
- addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
- addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
- addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
- addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
- addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
- addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
- addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
- addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
- addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
- addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
- addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
- addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
- addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
- addr_hit[246] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
- addr_hit[247] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
- addr_hit[248] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
- addr_hit[249] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
- addr_hit[250] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
- addr_hit[251] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
- addr_hit[252] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
- addr_hit[253] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
- addr_hit[254] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
- addr_hit[255] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
- addr_hit[256] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
- addr_hit[257] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
- addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
- addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
- addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
- addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
- addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
- addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
- addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
- addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
- addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
- addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
- addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
- addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
- addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
- addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
- addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
- addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
- addr_hit[274] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
- addr_hit[275] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
- addr_hit[276] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
- addr_hit[277] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
- addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
- addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[282] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[283] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[284] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[285] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
- addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
- addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
- addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
- addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
- addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
- addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
- addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
- addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
- addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
- addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
- addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
- addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
- addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
- addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
- addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
- addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
- addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
- addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
- addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
- addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
- addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
- addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET);
+ addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
+ addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
+ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
+ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
+ addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
+ addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
+ addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
+ addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
+ addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
+ addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
+ addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
+ addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
+ addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
+ addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
+ addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
+ addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
+ addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
+ addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
+ addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
+ addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
+ addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
+ addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
+ addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
+ addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
+ addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
+ addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
+ addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
+ addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
+ addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
+ addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
+ addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
+ addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
+ addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
+ addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
+ addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
+ addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
+ addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
+ addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
+ addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
+ addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
+ addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
+ addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
+ addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
+ addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
+ addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
+ addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
+ addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
+ addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
+ addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
+ addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
+ addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
+ addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
+ addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
+ addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
+ addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
+ addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
+ addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
+ addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
+ addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
+ addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
+ addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET);
+ addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
+ addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
+ addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
+ addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
+ addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
+ addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
+ addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
+ addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
+ addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
+ addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
+ addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
+ addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
+ addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
+ addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
+ addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
+ addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
+ addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
+ addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
+ addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
+ addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
+ addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
+ addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
+ addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
+ addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
+ addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
+ addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
+ addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
+ addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
+ addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
+ addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
+ addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
+ addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
+ addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
+ addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
+ addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
+ addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
+ addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
+ addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
+ addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
+ addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
+ addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
+ addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
+ addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
+ addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
+ addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
+ addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
+ addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
+ addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
+ addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
+ addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
+ addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
+ addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
+ addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
+ addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
+ addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
+ addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
+ addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
+ addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
+ addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
+ addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
+ addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET);
+ addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+ addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+ addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+ addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+ addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+ addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+ addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+ addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+ addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+ addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+ addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+ addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+ addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+ addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+ addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+ addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+ addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+ addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+ addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+ addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+ addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+ addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+ addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+ addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+ addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+ addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+ addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+ addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+ addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+ addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+ addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+ addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+ addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+ addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+ addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+ addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+ addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+ addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+ addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+ addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+ addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+ addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+ addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+ addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+ addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+ addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+ addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+ addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+ addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
+ addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
+ addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
+ addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
+ addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
+ addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
+ addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
+ addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
+ addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
+ addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
+ addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
+ addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
+ addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET);
+ addr_hit[250] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+ addr_hit[251] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+ addr_hit[252] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+ addr_hit[253] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+ addr_hit[254] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+ addr_hit[255] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
+ addr_hit[256] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
+ addr_hit[257] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
+ addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
+ addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
+ addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
+ addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
+ addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
+ addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
+ addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
+ addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
+ addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
+ addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
+ addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
+ addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
+ addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
+ addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+ addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+ addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+ addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+ addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+ addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
+ addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
+ addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+ addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
+ addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+ addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
+ addr_hit[282] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[283] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[284] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[285] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+ addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
+ addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+ addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
+ addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+ addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
+ addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+ addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
+ addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+ addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
+ addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+ addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
+ addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -13748,7 +13892,11 @@
(addr_hit[326] & (|(ALERT_HANDLER_PERMIT[326] & ~reg_be))) |
(addr_hit[327] & (|(ALERT_HANDLER_PERMIT[327] & ~reg_be))) |
(addr_hit[328] & (|(ALERT_HANDLER_PERMIT[328] & ~reg_be))) |
- (addr_hit[329] & (|(ALERT_HANDLER_PERMIT[329] & ~reg_be)))));
+ (addr_hit[329] & (|(ALERT_HANDLER_PERMIT[329] & ~reg_be))) |
+ (addr_hit[330] & (|(ALERT_HANDLER_PERMIT[330] & ~reg_be))) |
+ (addr_hit[331] & (|(ALERT_HANDLER_PERMIT[331] & ~reg_be))) |
+ (addr_hit[332] & (|(ALERT_HANDLER_PERMIT[332] & ~reg_be))) |
+ (addr_hit[333] & (|(ALERT_HANDLER_PERMIT[333] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -13968,769 +14116,783 @@
assign alert_regwen_59_we = addr_hit[65] & reg_we & !reg_error;
assign alert_regwen_59_wd = reg_wdata[0];
- assign alert_en_shadowed_0_re = addr_hit[66] & reg_re & !reg_error;
- assign alert_en_shadowed_0_we = addr_hit[66] & reg_we & !reg_error;
+ assign alert_regwen_60_we = addr_hit[66] & reg_we & !reg_error;
+
+ assign alert_regwen_60_wd = reg_wdata[0];
+ assign alert_en_shadowed_0_re = addr_hit[67] & reg_re & !reg_error;
+ assign alert_en_shadowed_0_we = addr_hit[67] & reg_we & !reg_error;
assign alert_en_shadowed_0_wd = reg_wdata[0];
- assign alert_en_shadowed_1_re = addr_hit[67] & reg_re & !reg_error;
- assign alert_en_shadowed_1_we = addr_hit[67] & reg_we & !reg_error;
+ assign alert_en_shadowed_1_re = addr_hit[68] & reg_re & !reg_error;
+ assign alert_en_shadowed_1_we = addr_hit[68] & reg_we & !reg_error;
assign alert_en_shadowed_1_wd = reg_wdata[0];
- assign alert_en_shadowed_2_re = addr_hit[68] & reg_re & !reg_error;
- assign alert_en_shadowed_2_we = addr_hit[68] & reg_we & !reg_error;
+ assign alert_en_shadowed_2_re = addr_hit[69] & reg_re & !reg_error;
+ assign alert_en_shadowed_2_we = addr_hit[69] & reg_we & !reg_error;
assign alert_en_shadowed_2_wd = reg_wdata[0];
- assign alert_en_shadowed_3_re = addr_hit[69] & reg_re & !reg_error;
- assign alert_en_shadowed_3_we = addr_hit[69] & reg_we & !reg_error;
+ assign alert_en_shadowed_3_re = addr_hit[70] & reg_re & !reg_error;
+ assign alert_en_shadowed_3_we = addr_hit[70] & reg_we & !reg_error;
assign alert_en_shadowed_3_wd = reg_wdata[0];
- assign alert_en_shadowed_4_re = addr_hit[70] & reg_re & !reg_error;
- assign alert_en_shadowed_4_we = addr_hit[70] & reg_we & !reg_error;
+ assign alert_en_shadowed_4_re = addr_hit[71] & reg_re & !reg_error;
+ assign alert_en_shadowed_4_we = addr_hit[71] & reg_we & !reg_error;
assign alert_en_shadowed_4_wd = reg_wdata[0];
- assign alert_en_shadowed_5_re = addr_hit[71] & reg_re & !reg_error;
- assign alert_en_shadowed_5_we = addr_hit[71] & reg_we & !reg_error;
+ assign alert_en_shadowed_5_re = addr_hit[72] & reg_re & !reg_error;
+ assign alert_en_shadowed_5_we = addr_hit[72] & reg_we & !reg_error;
assign alert_en_shadowed_5_wd = reg_wdata[0];
- assign alert_en_shadowed_6_re = addr_hit[72] & reg_re & !reg_error;
- assign alert_en_shadowed_6_we = addr_hit[72] & reg_we & !reg_error;
+ assign alert_en_shadowed_6_re = addr_hit[73] & reg_re & !reg_error;
+ assign alert_en_shadowed_6_we = addr_hit[73] & reg_we & !reg_error;
assign alert_en_shadowed_6_wd = reg_wdata[0];
- assign alert_en_shadowed_7_re = addr_hit[73] & reg_re & !reg_error;
- assign alert_en_shadowed_7_we = addr_hit[73] & reg_we & !reg_error;
+ assign alert_en_shadowed_7_re = addr_hit[74] & reg_re & !reg_error;
+ assign alert_en_shadowed_7_we = addr_hit[74] & reg_we & !reg_error;
assign alert_en_shadowed_7_wd = reg_wdata[0];
- assign alert_en_shadowed_8_re = addr_hit[74] & reg_re & !reg_error;
- assign alert_en_shadowed_8_we = addr_hit[74] & reg_we & !reg_error;
+ assign alert_en_shadowed_8_re = addr_hit[75] & reg_re & !reg_error;
+ assign alert_en_shadowed_8_we = addr_hit[75] & reg_we & !reg_error;
assign alert_en_shadowed_8_wd = reg_wdata[0];
- assign alert_en_shadowed_9_re = addr_hit[75] & reg_re & !reg_error;
- assign alert_en_shadowed_9_we = addr_hit[75] & reg_we & !reg_error;
+ assign alert_en_shadowed_9_re = addr_hit[76] & reg_re & !reg_error;
+ assign alert_en_shadowed_9_we = addr_hit[76] & reg_we & !reg_error;
assign alert_en_shadowed_9_wd = reg_wdata[0];
- assign alert_en_shadowed_10_re = addr_hit[76] & reg_re & !reg_error;
- assign alert_en_shadowed_10_we = addr_hit[76] & reg_we & !reg_error;
+ assign alert_en_shadowed_10_re = addr_hit[77] & reg_re & !reg_error;
+ assign alert_en_shadowed_10_we = addr_hit[77] & reg_we & !reg_error;
assign alert_en_shadowed_10_wd = reg_wdata[0];
- assign alert_en_shadowed_11_re = addr_hit[77] & reg_re & !reg_error;
- assign alert_en_shadowed_11_we = addr_hit[77] & reg_we & !reg_error;
+ assign alert_en_shadowed_11_re = addr_hit[78] & reg_re & !reg_error;
+ assign alert_en_shadowed_11_we = addr_hit[78] & reg_we & !reg_error;
assign alert_en_shadowed_11_wd = reg_wdata[0];
- assign alert_en_shadowed_12_re = addr_hit[78] & reg_re & !reg_error;
- assign alert_en_shadowed_12_we = addr_hit[78] & reg_we & !reg_error;
+ assign alert_en_shadowed_12_re = addr_hit[79] & reg_re & !reg_error;
+ assign alert_en_shadowed_12_we = addr_hit[79] & reg_we & !reg_error;
assign alert_en_shadowed_12_wd = reg_wdata[0];
- assign alert_en_shadowed_13_re = addr_hit[79] & reg_re & !reg_error;
- assign alert_en_shadowed_13_we = addr_hit[79] & reg_we & !reg_error;
+ assign alert_en_shadowed_13_re = addr_hit[80] & reg_re & !reg_error;
+ assign alert_en_shadowed_13_we = addr_hit[80] & reg_we & !reg_error;
assign alert_en_shadowed_13_wd = reg_wdata[0];
- assign alert_en_shadowed_14_re = addr_hit[80] & reg_re & !reg_error;
- assign alert_en_shadowed_14_we = addr_hit[80] & reg_we & !reg_error;
+ assign alert_en_shadowed_14_re = addr_hit[81] & reg_re & !reg_error;
+ assign alert_en_shadowed_14_we = addr_hit[81] & reg_we & !reg_error;
assign alert_en_shadowed_14_wd = reg_wdata[0];
- assign alert_en_shadowed_15_re = addr_hit[81] & reg_re & !reg_error;
- assign alert_en_shadowed_15_we = addr_hit[81] & reg_we & !reg_error;
+ assign alert_en_shadowed_15_re = addr_hit[82] & reg_re & !reg_error;
+ assign alert_en_shadowed_15_we = addr_hit[82] & reg_we & !reg_error;
assign alert_en_shadowed_15_wd = reg_wdata[0];
- assign alert_en_shadowed_16_re = addr_hit[82] & reg_re & !reg_error;
- assign alert_en_shadowed_16_we = addr_hit[82] & reg_we & !reg_error;
+ assign alert_en_shadowed_16_re = addr_hit[83] & reg_re & !reg_error;
+ assign alert_en_shadowed_16_we = addr_hit[83] & reg_we & !reg_error;
assign alert_en_shadowed_16_wd = reg_wdata[0];
- assign alert_en_shadowed_17_re = addr_hit[83] & reg_re & !reg_error;
- assign alert_en_shadowed_17_we = addr_hit[83] & reg_we & !reg_error;
+ assign alert_en_shadowed_17_re = addr_hit[84] & reg_re & !reg_error;
+ assign alert_en_shadowed_17_we = addr_hit[84] & reg_we & !reg_error;
assign alert_en_shadowed_17_wd = reg_wdata[0];
- assign alert_en_shadowed_18_re = addr_hit[84] & reg_re & !reg_error;
- assign alert_en_shadowed_18_we = addr_hit[84] & reg_we & !reg_error;
+ assign alert_en_shadowed_18_re = addr_hit[85] & reg_re & !reg_error;
+ assign alert_en_shadowed_18_we = addr_hit[85] & reg_we & !reg_error;
assign alert_en_shadowed_18_wd = reg_wdata[0];
- assign alert_en_shadowed_19_re = addr_hit[85] & reg_re & !reg_error;
- assign alert_en_shadowed_19_we = addr_hit[85] & reg_we & !reg_error;
+ assign alert_en_shadowed_19_re = addr_hit[86] & reg_re & !reg_error;
+ assign alert_en_shadowed_19_we = addr_hit[86] & reg_we & !reg_error;
assign alert_en_shadowed_19_wd = reg_wdata[0];
- assign alert_en_shadowed_20_re = addr_hit[86] & reg_re & !reg_error;
- assign alert_en_shadowed_20_we = addr_hit[86] & reg_we & !reg_error;
+ assign alert_en_shadowed_20_re = addr_hit[87] & reg_re & !reg_error;
+ assign alert_en_shadowed_20_we = addr_hit[87] & reg_we & !reg_error;
assign alert_en_shadowed_20_wd = reg_wdata[0];
- assign alert_en_shadowed_21_re = addr_hit[87] & reg_re & !reg_error;
- assign alert_en_shadowed_21_we = addr_hit[87] & reg_we & !reg_error;
+ assign alert_en_shadowed_21_re = addr_hit[88] & reg_re & !reg_error;
+ assign alert_en_shadowed_21_we = addr_hit[88] & reg_we & !reg_error;
assign alert_en_shadowed_21_wd = reg_wdata[0];
- assign alert_en_shadowed_22_re = addr_hit[88] & reg_re & !reg_error;
- assign alert_en_shadowed_22_we = addr_hit[88] & reg_we & !reg_error;
+ assign alert_en_shadowed_22_re = addr_hit[89] & reg_re & !reg_error;
+ assign alert_en_shadowed_22_we = addr_hit[89] & reg_we & !reg_error;
assign alert_en_shadowed_22_wd = reg_wdata[0];
- assign alert_en_shadowed_23_re = addr_hit[89] & reg_re & !reg_error;
- assign alert_en_shadowed_23_we = addr_hit[89] & reg_we & !reg_error;
+ assign alert_en_shadowed_23_re = addr_hit[90] & reg_re & !reg_error;
+ assign alert_en_shadowed_23_we = addr_hit[90] & reg_we & !reg_error;
assign alert_en_shadowed_23_wd = reg_wdata[0];
- assign alert_en_shadowed_24_re = addr_hit[90] & reg_re & !reg_error;
- assign alert_en_shadowed_24_we = addr_hit[90] & reg_we & !reg_error;
+ assign alert_en_shadowed_24_re = addr_hit[91] & reg_re & !reg_error;
+ assign alert_en_shadowed_24_we = addr_hit[91] & reg_we & !reg_error;
assign alert_en_shadowed_24_wd = reg_wdata[0];
- assign alert_en_shadowed_25_re = addr_hit[91] & reg_re & !reg_error;
- assign alert_en_shadowed_25_we = addr_hit[91] & reg_we & !reg_error;
+ assign alert_en_shadowed_25_re = addr_hit[92] & reg_re & !reg_error;
+ assign alert_en_shadowed_25_we = addr_hit[92] & reg_we & !reg_error;
assign alert_en_shadowed_25_wd = reg_wdata[0];
- assign alert_en_shadowed_26_re = addr_hit[92] & reg_re & !reg_error;
- assign alert_en_shadowed_26_we = addr_hit[92] & reg_we & !reg_error;
+ assign alert_en_shadowed_26_re = addr_hit[93] & reg_re & !reg_error;
+ assign alert_en_shadowed_26_we = addr_hit[93] & reg_we & !reg_error;
assign alert_en_shadowed_26_wd = reg_wdata[0];
- assign alert_en_shadowed_27_re = addr_hit[93] & reg_re & !reg_error;
- assign alert_en_shadowed_27_we = addr_hit[93] & reg_we & !reg_error;
+ assign alert_en_shadowed_27_re = addr_hit[94] & reg_re & !reg_error;
+ assign alert_en_shadowed_27_we = addr_hit[94] & reg_we & !reg_error;
assign alert_en_shadowed_27_wd = reg_wdata[0];
- assign alert_en_shadowed_28_re = addr_hit[94] & reg_re & !reg_error;
- assign alert_en_shadowed_28_we = addr_hit[94] & reg_we & !reg_error;
+ assign alert_en_shadowed_28_re = addr_hit[95] & reg_re & !reg_error;
+ assign alert_en_shadowed_28_we = addr_hit[95] & reg_we & !reg_error;
assign alert_en_shadowed_28_wd = reg_wdata[0];
- assign alert_en_shadowed_29_re = addr_hit[95] & reg_re & !reg_error;
- assign alert_en_shadowed_29_we = addr_hit[95] & reg_we & !reg_error;
+ assign alert_en_shadowed_29_re = addr_hit[96] & reg_re & !reg_error;
+ assign alert_en_shadowed_29_we = addr_hit[96] & reg_we & !reg_error;
assign alert_en_shadowed_29_wd = reg_wdata[0];
- assign alert_en_shadowed_30_re = addr_hit[96] & reg_re & !reg_error;
- assign alert_en_shadowed_30_we = addr_hit[96] & reg_we & !reg_error;
+ assign alert_en_shadowed_30_re = addr_hit[97] & reg_re & !reg_error;
+ assign alert_en_shadowed_30_we = addr_hit[97] & reg_we & !reg_error;
assign alert_en_shadowed_30_wd = reg_wdata[0];
- assign alert_en_shadowed_31_re = addr_hit[97] & reg_re & !reg_error;
- assign alert_en_shadowed_31_we = addr_hit[97] & reg_we & !reg_error;
+ assign alert_en_shadowed_31_re = addr_hit[98] & reg_re & !reg_error;
+ assign alert_en_shadowed_31_we = addr_hit[98] & reg_we & !reg_error;
assign alert_en_shadowed_31_wd = reg_wdata[0];
- assign alert_en_shadowed_32_re = addr_hit[98] & reg_re & !reg_error;
- assign alert_en_shadowed_32_we = addr_hit[98] & reg_we & !reg_error;
+ assign alert_en_shadowed_32_re = addr_hit[99] & reg_re & !reg_error;
+ assign alert_en_shadowed_32_we = addr_hit[99] & reg_we & !reg_error;
assign alert_en_shadowed_32_wd = reg_wdata[0];
- assign alert_en_shadowed_33_re = addr_hit[99] & reg_re & !reg_error;
- assign alert_en_shadowed_33_we = addr_hit[99] & reg_we & !reg_error;
+ assign alert_en_shadowed_33_re = addr_hit[100] & reg_re & !reg_error;
+ assign alert_en_shadowed_33_we = addr_hit[100] & reg_we & !reg_error;
assign alert_en_shadowed_33_wd = reg_wdata[0];
- assign alert_en_shadowed_34_re = addr_hit[100] & reg_re & !reg_error;
- assign alert_en_shadowed_34_we = addr_hit[100] & reg_we & !reg_error;
+ assign alert_en_shadowed_34_re = addr_hit[101] & reg_re & !reg_error;
+ assign alert_en_shadowed_34_we = addr_hit[101] & reg_we & !reg_error;
assign alert_en_shadowed_34_wd = reg_wdata[0];
- assign alert_en_shadowed_35_re = addr_hit[101] & reg_re & !reg_error;
- assign alert_en_shadowed_35_we = addr_hit[101] & reg_we & !reg_error;
+ assign alert_en_shadowed_35_re = addr_hit[102] & reg_re & !reg_error;
+ assign alert_en_shadowed_35_we = addr_hit[102] & reg_we & !reg_error;
assign alert_en_shadowed_35_wd = reg_wdata[0];
- assign alert_en_shadowed_36_re = addr_hit[102] & reg_re & !reg_error;
- assign alert_en_shadowed_36_we = addr_hit[102] & reg_we & !reg_error;
+ assign alert_en_shadowed_36_re = addr_hit[103] & reg_re & !reg_error;
+ assign alert_en_shadowed_36_we = addr_hit[103] & reg_we & !reg_error;
assign alert_en_shadowed_36_wd = reg_wdata[0];
- assign alert_en_shadowed_37_re = addr_hit[103] & reg_re & !reg_error;
- assign alert_en_shadowed_37_we = addr_hit[103] & reg_we & !reg_error;
+ assign alert_en_shadowed_37_re = addr_hit[104] & reg_re & !reg_error;
+ assign alert_en_shadowed_37_we = addr_hit[104] & reg_we & !reg_error;
assign alert_en_shadowed_37_wd = reg_wdata[0];
- assign alert_en_shadowed_38_re = addr_hit[104] & reg_re & !reg_error;
- assign alert_en_shadowed_38_we = addr_hit[104] & reg_we & !reg_error;
+ assign alert_en_shadowed_38_re = addr_hit[105] & reg_re & !reg_error;
+ assign alert_en_shadowed_38_we = addr_hit[105] & reg_we & !reg_error;
assign alert_en_shadowed_38_wd = reg_wdata[0];
- assign alert_en_shadowed_39_re = addr_hit[105] & reg_re & !reg_error;
- assign alert_en_shadowed_39_we = addr_hit[105] & reg_we & !reg_error;
+ assign alert_en_shadowed_39_re = addr_hit[106] & reg_re & !reg_error;
+ assign alert_en_shadowed_39_we = addr_hit[106] & reg_we & !reg_error;
assign alert_en_shadowed_39_wd = reg_wdata[0];
- assign alert_en_shadowed_40_re = addr_hit[106] & reg_re & !reg_error;
- assign alert_en_shadowed_40_we = addr_hit[106] & reg_we & !reg_error;
+ assign alert_en_shadowed_40_re = addr_hit[107] & reg_re & !reg_error;
+ assign alert_en_shadowed_40_we = addr_hit[107] & reg_we & !reg_error;
assign alert_en_shadowed_40_wd = reg_wdata[0];
- assign alert_en_shadowed_41_re = addr_hit[107] & reg_re & !reg_error;
- assign alert_en_shadowed_41_we = addr_hit[107] & reg_we & !reg_error;
+ assign alert_en_shadowed_41_re = addr_hit[108] & reg_re & !reg_error;
+ assign alert_en_shadowed_41_we = addr_hit[108] & reg_we & !reg_error;
assign alert_en_shadowed_41_wd = reg_wdata[0];
- assign alert_en_shadowed_42_re = addr_hit[108] & reg_re & !reg_error;
- assign alert_en_shadowed_42_we = addr_hit[108] & reg_we & !reg_error;
+ assign alert_en_shadowed_42_re = addr_hit[109] & reg_re & !reg_error;
+ assign alert_en_shadowed_42_we = addr_hit[109] & reg_we & !reg_error;
assign alert_en_shadowed_42_wd = reg_wdata[0];
- assign alert_en_shadowed_43_re = addr_hit[109] & reg_re & !reg_error;
- assign alert_en_shadowed_43_we = addr_hit[109] & reg_we & !reg_error;
+ assign alert_en_shadowed_43_re = addr_hit[110] & reg_re & !reg_error;
+ assign alert_en_shadowed_43_we = addr_hit[110] & reg_we & !reg_error;
assign alert_en_shadowed_43_wd = reg_wdata[0];
- assign alert_en_shadowed_44_re = addr_hit[110] & reg_re & !reg_error;
- assign alert_en_shadowed_44_we = addr_hit[110] & reg_we & !reg_error;
+ assign alert_en_shadowed_44_re = addr_hit[111] & reg_re & !reg_error;
+ assign alert_en_shadowed_44_we = addr_hit[111] & reg_we & !reg_error;
assign alert_en_shadowed_44_wd = reg_wdata[0];
- assign alert_en_shadowed_45_re = addr_hit[111] & reg_re & !reg_error;
- assign alert_en_shadowed_45_we = addr_hit[111] & reg_we & !reg_error;
+ assign alert_en_shadowed_45_re = addr_hit[112] & reg_re & !reg_error;
+ assign alert_en_shadowed_45_we = addr_hit[112] & reg_we & !reg_error;
assign alert_en_shadowed_45_wd = reg_wdata[0];
- assign alert_en_shadowed_46_re = addr_hit[112] & reg_re & !reg_error;
- assign alert_en_shadowed_46_we = addr_hit[112] & reg_we & !reg_error;
+ assign alert_en_shadowed_46_re = addr_hit[113] & reg_re & !reg_error;
+ assign alert_en_shadowed_46_we = addr_hit[113] & reg_we & !reg_error;
assign alert_en_shadowed_46_wd = reg_wdata[0];
- assign alert_en_shadowed_47_re = addr_hit[113] & reg_re & !reg_error;
- assign alert_en_shadowed_47_we = addr_hit[113] & reg_we & !reg_error;
+ assign alert_en_shadowed_47_re = addr_hit[114] & reg_re & !reg_error;
+ assign alert_en_shadowed_47_we = addr_hit[114] & reg_we & !reg_error;
assign alert_en_shadowed_47_wd = reg_wdata[0];
- assign alert_en_shadowed_48_re = addr_hit[114] & reg_re & !reg_error;
- assign alert_en_shadowed_48_we = addr_hit[114] & reg_we & !reg_error;
+ assign alert_en_shadowed_48_re = addr_hit[115] & reg_re & !reg_error;
+ assign alert_en_shadowed_48_we = addr_hit[115] & reg_we & !reg_error;
assign alert_en_shadowed_48_wd = reg_wdata[0];
- assign alert_en_shadowed_49_re = addr_hit[115] & reg_re & !reg_error;
- assign alert_en_shadowed_49_we = addr_hit[115] & reg_we & !reg_error;
+ assign alert_en_shadowed_49_re = addr_hit[116] & reg_re & !reg_error;
+ assign alert_en_shadowed_49_we = addr_hit[116] & reg_we & !reg_error;
assign alert_en_shadowed_49_wd = reg_wdata[0];
- assign alert_en_shadowed_50_re = addr_hit[116] & reg_re & !reg_error;
- assign alert_en_shadowed_50_we = addr_hit[116] & reg_we & !reg_error;
+ assign alert_en_shadowed_50_re = addr_hit[117] & reg_re & !reg_error;
+ assign alert_en_shadowed_50_we = addr_hit[117] & reg_we & !reg_error;
assign alert_en_shadowed_50_wd = reg_wdata[0];
- assign alert_en_shadowed_51_re = addr_hit[117] & reg_re & !reg_error;
- assign alert_en_shadowed_51_we = addr_hit[117] & reg_we & !reg_error;
+ assign alert_en_shadowed_51_re = addr_hit[118] & reg_re & !reg_error;
+ assign alert_en_shadowed_51_we = addr_hit[118] & reg_we & !reg_error;
assign alert_en_shadowed_51_wd = reg_wdata[0];
- assign alert_en_shadowed_52_re = addr_hit[118] & reg_re & !reg_error;
- assign alert_en_shadowed_52_we = addr_hit[118] & reg_we & !reg_error;
+ assign alert_en_shadowed_52_re = addr_hit[119] & reg_re & !reg_error;
+ assign alert_en_shadowed_52_we = addr_hit[119] & reg_we & !reg_error;
assign alert_en_shadowed_52_wd = reg_wdata[0];
- assign alert_en_shadowed_53_re = addr_hit[119] & reg_re & !reg_error;
- assign alert_en_shadowed_53_we = addr_hit[119] & reg_we & !reg_error;
+ assign alert_en_shadowed_53_re = addr_hit[120] & reg_re & !reg_error;
+ assign alert_en_shadowed_53_we = addr_hit[120] & reg_we & !reg_error;
assign alert_en_shadowed_53_wd = reg_wdata[0];
- assign alert_en_shadowed_54_re = addr_hit[120] & reg_re & !reg_error;
- assign alert_en_shadowed_54_we = addr_hit[120] & reg_we & !reg_error;
+ assign alert_en_shadowed_54_re = addr_hit[121] & reg_re & !reg_error;
+ assign alert_en_shadowed_54_we = addr_hit[121] & reg_we & !reg_error;
assign alert_en_shadowed_54_wd = reg_wdata[0];
- assign alert_en_shadowed_55_re = addr_hit[121] & reg_re & !reg_error;
- assign alert_en_shadowed_55_we = addr_hit[121] & reg_we & !reg_error;
+ assign alert_en_shadowed_55_re = addr_hit[122] & reg_re & !reg_error;
+ assign alert_en_shadowed_55_we = addr_hit[122] & reg_we & !reg_error;
assign alert_en_shadowed_55_wd = reg_wdata[0];
- assign alert_en_shadowed_56_re = addr_hit[122] & reg_re & !reg_error;
- assign alert_en_shadowed_56_we = addr_hit[122] & reg_we & !reg_error;
+ assign alert_en_shadowed_56_re = addr_hit[123] & reg_re & !reg_error;
+ assign alert_en_shadowed_56_we = addr_hit[123] & reg_we & !reg_error;
assign alert_en_shadowed_56_wd = reg_wdata[0];
- assign alert_en_shadowed_57_re = addr_hit[123] & reg_re & !reg_error;
- assign alert_en_shadowed_57_we = addr_hit[123] & reg_we & !reg_error;
+ assign alert_en_shadowed_57_re = addr_hit[124] & reg_re & !reg_error;
+ assign alert_en_shadowed_57_we = addr_hit[124] & reg_we & !reg_error;
assign alert_en_shadowed_57_wd = reg_wdata[0];
- assign alert_en_shadowed_58_re = addr_hit[124] & reg_re & !reg_error;
- assign alert_en_shadowed_58_we = addr_hit[124] & reg_we & !reg_error;
+ assign alert_en_shadowed_58_re = addr_hit[125] & reg_re & !reg_error;
+ assign alert_en_shadowed_58_we = addr_hit[125] & reg_we & !reg_error;
assign alert_en_shadowed_58_wd = reg_wdata[0];
- assign alert_en_shadowed_59_re = addr_hit[125] & reg_re & !reg_error;
- assign alert_en_shadowed_59_we = addr_hit[125] & reg_we & !reg_error;
+ assign alert_en_shadowed_59_re = addr_hit[126] & reg_re & !reg_error;
+ assign alert_en_shadowed_59_we = addr_hit[126] & reg_we & !reg_error;
assign alert_en_shadowed_59_wd = reg_wdata[0];
- assign alert_class_shadowed_0_re = addr_hit[126] & reg_re & !reg_error;
- assign alert_class_shadowed_0_we = addr_hit[126] & reg_we & !reg_error;
+ assign alert_en_shadowed_60_re = addr_hit[127] & reg_re & !reg_error;
+ assign alert_en_shadowed_60_we = addr_hit[127] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_60_wd = reg_wdata[0];
+ assign alert_class_shadowed_0_re = addr_hit[128] & reg_re & !reg_error;
+ assign alert_class_shadowed_0_we = addr_hit[128] & reg_we & !reg_error;
assign alert_class_shadowed_0_wd = reg_wdata[1:0];
- assign alert_class_shadowed_1_re = addr_hit[127] & reg_re & !reg_error;
- assign alert_class_shadowed_1_we = addr_hit[127] & reg_we & !reg_error;
+ assign alert_class_shadowed_1_re = addr_hit[129] & reg_re & !reg_error;
+ assign alert_class_shadowed_1_we = addr_hit[129] & reg_we & !reg_error;
assign alert_class_shadowed_1_wd = reg_wdata[1:0];
- assign alert_class_shadowed_2_re = addr_hit[128] & reg_re & !reg_error;
- assign alert_class_shadowed_2_we = addr_hit[128] & reg_we & !reg_error;
+ assign alert_class_shadowed_2_re = addr_hit[130] & reg_re & !reg_error;
+ assign alert_class_shadowed_2_we = addr_hit[130] & reg_we & !reg_error;
assign alert_class_shadowed_2_wd = reg_wdata[1:0];
- assign alert_class_shadowed_3_re = addr_hit[129] & reg_re & !reg_error;
- assign alert_class_shadowed_3_we = addr_hit[129] & reg_we & !reg_error;
+ assign alert_class_shadowed_3_re = addr_hit[131] & reg_re & !reg_error;
+ assign alert_class_shadowed_3_we = addr_hit[131] & reg_we & !reg_error;
assign alert_class_shadowed_3_wd = reg_wdata[1:0];
- assign alert_class_shadowed_4_re = addr_hit[130] & reg_re & !reg_error;
- assign alert_class_shadowed_4_we = addr_hit[130] & reg_we & !reg_error;
+ assign alert_class_shadowed_4_re = addr_hit[132] & reg_re & !reg_error;
+ assign alert_class_shadowed_4_we = addr_hit[132] & reg_we & !reg_error;
assign alert_class_shadowed_4_wd = reg_wdata[1:0];
- assign alert_class_shadowed_5_re = addr_hit[131] & reg_re & !reg_error;
- assign alert_class_shadowed_5_we = addr_hit[131] & reg_we & !reg_error;
+ assign alert_class_shadowed_5_re = addr_hit[133] & reg_re & !reg_error;
+ assign alert_class_shadowed_5_we = addr_hit[133] & reg_we & !reg_error;
assign alert_class_shadowed_5_wd = reg_wdata[1:0];
- assign alert_class_shadowed_6_re = addr_hit[132] & reg_re & !reg_error;
- assign alert_class_shadowed_6_we = addr_hit[132] & reg_we & !reg_error;
+ assign alert_class_shadowed_6_re = addr_hit[134] & reg_re & !reg_error;
+ assign alert_class_shadowed_6_we = addr_hit[134] & reg_we & !reg_error;
assign alert_class_shadowed_6_wd = reg_wdata[1:0];
- assign alert_class_shadowed_7_re = addr_hit[133] & reg_re & !reg_error;
- assign alert_class_shadowed_7_we = addr_hit[133] & reg_we & !reg_error;
+ assign alert_class_shadowed_7_re = addr_hit[135] & reg_re & !reg_error;
+ assign alert_class_shadowed_7_we = addr_hit[135] & reg_we & !reg_error;
assign alert_class_shadowed_7_wd = reg_wdata[1:0];
- assign alert_class_shadowed_8_re = addr_hit[134] & reg_re & !reg_error;
- assign alert_class_shadowed_8_we = addr_hit[134] & reg_we & !reg_error;
+ assign alert_class_shadowed_8_re = addr_hit[136] & reg_re & !reg_error;
+ assign alert_class_shadowed_8_we = addr_hit[136] & reg_we & !reg_error;
assign alert_class_shadowed_8_wd = reg_wdata[1:0];
- assign alert_class_shadowed_9_re = addr_hit[135] & reg_re & !reg_error;
- assign alert_class_shadowed_9_we = addr_hit[135] & reg_we & !reg_error;
+ assign alert_class_shadowed_9_re = addr_hit[137] & reg_re & !reg_error;
+ assign alert_class_shadowed_9_we = addr_hit[137] & reg_we & !reg_error;
assign alert_class_shadowed_9_wd = reg_wdata[1:0];
- assign alert_class_shadowed_10_re = addr_hit[136] & reg_re & !reg_error;
- assign alert_class_shadowed_10_we = addr_hit[136] & reg_we & !reg_error;
+ assign alert_class_shadowed_10_re = addr_hit[138] & reg_re & !reg_error;
+ assign alert_class_shadowed_10_we = addr_hit[138] & reg_we & !reg_error;
assign alert_class_shadowed_10_wd = reg_wdata[1:0];
- assign alert_class_shadowed_11_re = addr_hit[137] & reg_re & !reg_error;
- assign alert_class_shadowed_11_we = addr_hit[137] & reg_we & !reg_error;
+ assign alert_class_shadowed_11_re = addr_hit[139] & reg_re & !reg_error;
+ assign alert_class_shadowed_11_we = addr_hit[139] & reg_we & !reg_error;
assign alert_class_shadowed_11_wd = reg_wdata[1:0];
- assign alert_class_shadowed_12_re = addr_hit[138] & reg_re & !reg_error;
- assign alert_class_shadowed_12_we = addr_hit[138] & reg_we & !reg_error;
+ assign alert_class_shadowed_12_re = addr_hit[140] & reg_re & !reg_error;
+ assign alert_class_shadowed_12_we = addr_hit[140] & reg_we & !reg_error;
assign alert_class_shadowed_12_wd = reg_wdata[1:0];
- assign alert_class_shadowed_13_re = addr_hit[139] & reg_re & !reg_error;
- assign alert_class_shadowed_13_we = addr_hit[139] & reg_we & !reg_error;
+ assign alert_class_shadowed_13_re = addr_hit[141] & reg_re & !reg_error;
+ assign alert_class_shadowed_13_we = addr_hit[141] & reg_we & !reg_error;
assign alert_class_shadowed_13_wd = reg_wdata[1:0];
- assign alert_class_shadowed_14_re = addr_hit[140] & reg_re & !reg_error;
- assign alert_class_shadowed_14_we = addr_hit[140] & reg_we & !reg_error;
+ assign alert_class_shadowed_14_re = addr_hit[142] & reg_re & !reg_error;
+ assign alert_class_shadowed_14_we = addr_hit[142] & reg_we & !reg_error;
assign alert_class_shadowed_14_wd = reg_wdata[1:0];
- assign alert_class_shadowed_15_re = addr_hit[141] & reg_re & !reg_error;
- assign alert_class_shadowed_15_we = addr_hit[141] & reg_we & !reg_error;
+ assign alert_class_shadowed_15_re = addr_hit[143] & reg_re & !reg_error;
+ assign alert_class_shadowed_15_we = addr_hit[143] & reg_we & !reg_error;
assign alert_class_shadowed_15_wd = reg_wdata[1:0];
- assign alert_class_shadowed_16_re = addr_hit[142] & reg_re & !reg_error;
- assign alert_class_shadowed_16_we = addr_hit[142] & reg_we & !reg_error;
+ assign alert_class_shadowed_16_re = addr_hit[144] & reg_re & !reg_error;
+ assign alert_class_shadowed_16_we = addr_hit[144] & reg_we & !reg_error;
assign alert_class_shadowed_16_wd = reg_wdata[1:0];
- assign alert_class_shadowed_17_re = addr_hit[143] & reg_re & !reg_error;
- assign alert_class_shadowed_17_we = addr_hit[143] & reg_we & !reg_error;
+ assign alert_class_shadowed_17_re = addr_hit[145] & reg_re & !reg_error;
+ assign alert_class_shadowed_17_we = addr_hit[145] & reg_we & !reg_error;
assign alert_class_shadowed_17_wd = reg_wdata[1:0];
- assign alert_class_shadowed_18_re = addr_hit[144] & reg_re & !reg_error;
- assign alert_class_shadowed_18_we = addr_hit[144] & reg_we & !reg_error;
+ assign alert_class_shadowed_18_re = addr_hit[146] & reg_re & !reg_error;
+ assign alert_class_shadowed_18_we = addr_hit[146] & reg_we & !reg_error;
assign alert_class_shadowed_18_wd = reg_wdata[1:0];
- assign alert_class_shadowed_19_re = addr_hit[145] & reg_re & !reg_error;
- assign alert_class_shadowed_19_we = addr_hit[145] & reg_we & !reg_error;
+ assign alert_class_shadowed_19_re = addr_hit[147] & reg_re & !reg_error;
+ assign alert_class_shadowed_19_we = addr_hit[147] & reg_we & !reg_error;
assign alert_class_shadowed_19_wd = reg_wdata[1:0];
- assign alert_class_shadowed_20_re = addr_hit[146] & reg_re & !reg_error;
- assign alert_class_shadowed_20_we = addr_hit[146] & reg_we & !reg_error;
+ assign alert_class_shadowed_20_re = addr_hit[148] & reg_re & !reg_error;
+ assign alert_class_shadowed_20_we = addr_hit[148] & reg_we & !reg_error;
assign alert_class_shadowed_20_wd = reg_wdata[1:0];
- assign alert_class_shadowed_21_re = addr_hit[147] & reg_re & !reg_error;
- assign alert_class_shadowed_21_we = addr_hit[147] & reg_we & !reg_error;
+ assign alert_class_shadowed_21_re = addr_hit[149] & reg_re & !reg_error;
+ assign alert_class_shadowed_21_we = addr_hit[149] & reg_we & !reg_error;
assign alert_class_shadowed_21_wd = reg_wdata[1:0];
- assign alert_class_shadowed_22_re = addr_hit[148] & reg_re & !reg_error;
- assign alert_class_shadowed_22_we = addr_hit[148] & reg_we & !reg_error;
+ assign alert_class_shadowed_22_re = addr_hit[150] & reg_re & !reg_error;
+ assign alert_class_shadowed_22_we = addr_hit[150] & reg_we & !reg_error;
assign alert_class_shadowed_22_wd = reg_wdata[1:0];
- assign alert_class_shadowed_23_re = addr_hit[149] & reg_re & !reg_error;
- assign alert_class_shadowed_23_we = addr_hit[149] & reg_we & !reg_error;
+ assign alert_class_shadowed_23_re = addr_hit[151] & reg_re & !reg_error;
+ assign alert_class_shadowed_23_we = addr_hit[151] & reg_we & !reg_error;
assign alert_class_shadowed_23_wd = reg_wdata[1:0];
- assign alert_class_shadowed_24_re = addr_hit[150] & reg_re & !reg_error;
- assign alert_class_shadowed_24_we = addr_hit[150] & reg_we & !reg_error;
+ assign alert_class_shadowed_24_re = addr_hit[152] & reg_re & !reg_error;
+ assign alert_class_shadowed_24_we = addr_hit[152] & reg_we & !reg_error;
assign alert_class_shadowed_24_wd = reg_wdata[1:0];
- assign alert_class_shadowed_25_re = addr_hit[151] & reg_re & !reg_error;
- assign alert_class_shadowed_25_we = addr_hit[151] & reg_we & !reg_error;
+ assign alert_class_shadowed_25_re = addr_hit[153] & reg_re & !reg_error;
+ assign alert_class_shadowed_25_we = addr_hit[153] & reg_we & !reg_error;
assign alert_class_shadowed_25_wd = reg_wdata[1:0];
- assign alert_class_shadowed_26_re = addr_hit[152] & reg_re & !reg_error;
- assign alert_class_shadowed_26_we = addr_hit[152] & reg_we & !reg_error;
+ assign alert_class_shadowed_26_re = addr_hit[154] & reg_re & !reg_error;
+ assign alert_class_shadowed_26_we = addr_hit[154] & reg_we & !reg_error;
assign alert_class_shadowed_26_wd = reg_wdata[1:0];
- assign alert_class_shadowed_27_re = addr_hit[153] & reg_re & !reg_error;
- assign alert_class_shadowed_27_we = addr_hit[153] & reg_we & !reg_error;
+ assign alert_class_shadowed_27_re = addr_hit[155] & reg_re & !reg_error;
+ assign alert_class_shadowed_27_we = addr_hit[155] & reg_we & !reg_error;
assign alert_class_shadowed_27_wd = reg_wdata[1:0];
- assign alert_class_shadowed_28_re = addr_hit[154] & reg_re & !reg_error;
- assign alert_class_shadowed_28_we = addr_hit[154] & reg_we & !reg_error;
+ assign alert_class_shadowed_28_re = addr_hit[156] & reg_re & !reg_error;
+ assign alert_class_shadowed_28_we = addr_hit[156] & reg_we & !reg_error;
assign alert_class_shadowed_28_wd = reg_wdata[1:0];
- assign alert_class_shadowed_29_re = addr_hit[155] & reg_re & !reg_error;
- assign alert_class_shadowed_29_we = addr_hit[155] & reg_we & !reg_error;
+ assign alert_class_shadowed_29_re = addr_hit[157] & reg_re & !reg_error;
+ assign alert_class_shadowed_29_we = addr_hit[157] & reg_we & !reg_error;
assign alert_class_shadowed_29_wd = reg_wdata[1:0];
- assign alert_class_shadowed_30_re = addr_hit[156] & reg_re & !reg_error;
- assign alert_class_shadowed_30_we = addr_hit[156] & reg_we & !reg_error;
+ assign alert_class_shadowed_30_re = addr_hit[158] & reg_re & !reg_error;
+ assign alert_class_shadowed_30_we = addr_hit[158] & reg_we & !reg_error;
assign alert_class_shadowed_30_wd = reg_wdata[1:0];
- assign alert_class_shadowed_31_re = addr_hit[157] & reg_re & !reg_error;
- assign alert_class_shadowed_31_we = addr_hit[157] & reg_we & !reg_error;
+ assign alert_class_shadowed_31_re = addr_hit[159] & reg_re & !reg_error;
+ assign alert_class_shadowed_31_we = addr_hit[159] & reg_we & !reg_error;
assign alert_class_shadowed_31_wd = reg_wdata[1:0];
- assign alert_class_shadowed_32_re = addr_hit[158] & reg_re & !reg_error;
- assign alert_class_shadowed_32_we = addr_hit[158] & reg_we & !reg_error;
+ assign alert_class_shadowed_32_re = addr_hit[160] & reg_re & !reg_error;
+ assign alert_class_shadowed_32_we = addr_hit[160] & reg_we & !reg_error;
assign alert_class_shadowed_32_wd = reg_wdata[1:0];
- assign alert_class_shadowed_33_re = addr_hit[159] & reg_re & !reg_error;
- assign alert_class_shadowed_33_we = addr_hit[159] & reg_we & !reg_error;
+ assign alert_class_shadowed_33_re = addr_hit[161] & reg_re & !reg_error;
+ assign alert_class_shadowed_33_we = addr_hit[161] & reg_we & !reg_error;
assign alert_class_shadowed_33_wd = reg_wdata[1:0];
- assign alert_class_shadowed_34_re = addr_hit[160] & reg_re & !reg_error;
- assign alert_class_shadowed_34_we = addr_hit[160] & reg_we & !reg_error;
+ assign alert_class_shadowed_34_re = addr_hit[162] & reg_re & !reg_error;
+ assign alert_class_shadowed_34_we = addr_hit[162] & reg_we & !reg_error;
assign alert_class_shadowed_34_wd = reg_wdata[1:0];
- assign alert_class_shadowed_35_re = addr_hit[161] & reg_re & !reg_error;
- assign alert_class_shadowed_35_we = addr_hit[161] & reg_we & !reg_error;
+ assign alert_class_shadowed_35_re = addr_hit[163] & reg_re & !reg_error;
+ assign alert_class_shadowed_35_we = addr_hit[163] & reg_we & !reg_error;
assign alert_class_shadowed_35_wd = reg_wdata[1:0];
- assign alert_class_shadowed_36_re = addr_hit[162] & reg_re & !reg_error;
- assign alert_class_shadowed_36_we = addr_hit[162] & reg_we & !reg_error;
+ assign alert_class_shadowed_36_re = addr_hit[164] & reg_re & !reg_error;
+ assign alert_class_shadowed_36_we = addr_hit[164] & reg_we & !reg_error;
assign alert_class_shadowed_36_wd = reg_wdata[1:0];
- assign alert_class_shadowed_37_re = addr_hit[163] & reg_re & !reg_error;
- assign alert_class_shadowed_37_we = addr_hit[163] & reg_we & !reg_error;
+ assign alert_class_shadowed_37_re = addr_hit[165] & reg_re & !reg_error;
+ assign alert_class_shadowed_37_we = addr_hit[165] & reg_we & !reg_error;
assign alert_class_shadowed_37_wd = reg_wdata[1:0];
- assign alert_class_shadowed_38_re = addr_hit[164] & reg_re & !reg_error;
- assign alert_class_shadowed_38_we = addr_hit[164] & reg_we & !reg_error;
+ assign alert_class_shadowed_38_re = addr_hit[166] & reg_re & !reg_error;
+ assign alert_class_shadowed_38_we = addr_hit[166] & reg_we & !reg_error;
assign alert_class_shadowed_38_wd = reg_wdata[1:0];
- assign alert_class_shadowed_39_re = addr_hit[165] & reg_re & !reg_error;
- assign alert_class_shadowed_39_we = addr_hit[165] & reg_we & !reg_error;
+ assign alert_class_shadowed_39_re = addr_hit[167] & reg_re & !reg_error;
+ assign alert_class_shadowed_39_we = addr_hit[167] & reg_we & !reg_error;
assign alert_class_shadowed_39_wd = reg_wdata[1:0];
- assign alert_class_shadowed_40_re = addr_hit[166] & reg_re & !reg_error;
- assign alert_class_shadowed_40_we = addr_hit[166] & reg_we & !reg_error;
+ assign alert_class_shadowed_40_re = addr_hit[168] & reg_re & !reg_error;
+ assign alert_class_shadowed_40_we = addr_hit[168] & reg_we & !reg_error;
assign alert_class_shadowed_40_wd = reg_wdata[1:0];
- assign alert_class_shadowed_41_re = addr_hit[167] & reg_re & !reg_error;
- assign alert_class_shadowed_41_we = addr_hit[167] & reg_we & !reg_error;
+ assign alert_class_shadowed_41_re = addr_hit[169] & reg_re & !reg_error;
+ assign alert_class_shadowed_41_we = addr_hit[169] & reg_we & !reg_error;
assign alert_class_shadowed_41_wd = reg_wdata[1:0];
- assign alert_class_shadowed_42_re = addr_hit[168] & reg_re & !reg_error;
- assign alert_class_shadowed_42_we = addr_hit[168] & reg_we & !reg_error;
+ assign alert_class_shadowed_42_re = addr_hit[170] & reg_re & !reg_error;
+ assign alert_class_shadowed_42_we = addr_hit[170] & reg_we & !reg_error;
assign alert_class_shadowed_42_wd = reg_wdata[1:0];
- assign alert_class_shadowed_43_re = addr_hit[169] & reg_re & !reg_error;
- assign alert_class_shadowed_43_we = addr_hit[169] & reg_we & !reg_error;
+ assign alert_class_shadowed_43_re = addr_hit[171] & reg_re & !reg_error;
+ assign alert_class_shadowed_43_we = addr_hit[171] & reg_we & !reg_error;
assign alert_class_shadowed_43_wd = reg_wdata[1:0];
- assign alert_class_shadowed_44_re = addr_hit[170] & reg_re & !reg_error;
- assign alert_class_shadowed_44_we = addr_hit[170] & reg_we & !reg_error;
+ assign alert_class_shadowed_44_re = addr_hit[172] & reg_re & !reg_error;
+ assign alert_class_shadowed_44_we = addr_hit[172] & reg_we & !reg_error;
assign alert_class_shadowed_44_wd = reg_wdata[1:0];
- assign alert_class_shadowed_45_re = addr_hit[171] & reg_re & !reg_error;
- assign alert_class_shadowed_45_we = addr_hit[171] & reg_we & !reg_error;
+ assign alert_class_shadowed_45_re = addr_hit[173] & reg_re & !reg_error;
+ assign alert_class_shadowed_45_we = addr_hit[173] & reg_we & !reg_error;
assign alert_class_shadowed_45_wd = reg_wdata[1:0];
- assign alert_class_shadowed_46_re = addr_hit[172] & reg_re & !reg_error;
- assign alert_class_shadowed_46_we = addr_hit[172] & reg_we & !reg_error;
+ assign alert_class_shadowed_46_re = addr_hit[174] & reg_re & !reg_error;
+ assign alert_class_shadowed_46_we = addr_hit[174] & reg_we & !reg_error;
assign alert_class_shadowed_46_wd = reg_wdata[1:0];
- assign alert_class_shadowed_47_re = addr_hit[173] & reg_re & !reg_error;
- assign alert_class_shadowed_47_we = addr_hit[173] & reg_we & !reg_error;
+ assign alert_class_shadowed_47_re = addr_hit[175] & reg_re & !reg_error;
+ assign alert_class_shadowed_47_we = addr_hit[175] & reg_we & !reg_error;
assign alert_class_shadowed_47_wd = reg_wdata[1:0];
- assign alert_class_shadowed_48_re = addr_hit[174] & reg_re & !reg_error;
- assign alert_class_shadowed_48_we = addr_hit[174] & reg_we & !reg_error;
+ assign alert_class_shadowed_48_re = addr_hit[176] & reg_re & !reg_error;
+ assign alert_class_shadowed_48_we = addr_hit[176] & reg_we & !reg_error;
assign alert_class_shadowed_48_wd = reg_wdata[1:0];
- assign alert_class_shadowed_49_re = addr_hit[175] & reg_re & !reg_error;
- assign alert_class_shadowed_49_we = addr_hit[175] & reg_we & !reg_error;
+ assign alert_class_shadowed_49_re = addr_hit[177] & reg_re & !reg_error;
+ assign alert_class_shadowed_49_we = addr_hit[177] & reg_we & !reg_error;
assign alert_class_shadowed_49_wd = reg_wdata[1:0];
- assign alert_class_shadowed_50_re = addr_hit[176] & reg_re & !reg_error;
- assign alert_class_shadowed_50_we = addr_hit[176] & reg_we & !reg_error;
+ assign alert_class_shadowed_50_re = addr_hit[178] & reg_re & !reg_error;
+ assign alert_class_shadowed_50_we = addr_hit[178] & reg_we & !reg_error;
assign alert_class_shadowed_50_wd = reg_wdata[1:0];
- assign alert_class_shadowed_51_re = addr_hit[177] & reg_re & !reg_error;
- assign alert_class_shadowed_51_we = addr_hit[177] & reg_we & !reg_error;
+ assign alert_class_shadowed_51_re = addr_hit[179] & reg_re & !reg_error;
+ assign alert_class_shadowed_51_we = addr_hit[179] & reg_we & !reg_error;
assign alert_class_shadowed_51_wd = reg_wdata[1:0];
- assign alert_class_shadowed_52_re = addr_hit[178] & reg_re & !reg_error;
- assign alert_class_shadowed_52_we = addr_hit[178] & reg_we & !reg_error;
+ assign alert_class_shadowed_52_re = addr_hit[180] & reg_re & !reg_error;
+ assign alert_class_shadowed_52_we = addr_hit[180] & reg_we & !reg_error;
assign alert_class_shadowed_52_wd = reg_wdata[1:0];
- assign alert_class_shadowed_53_re = addr_hit[179] & reg_re & !reg_error;
- assign alert_class_shadowed_53_we = addr_hit[179] & reg_we & !reg_error;
+ assign alert_class_shadowed_53_re = addr_hit[181] & reg_re & !reg_error;
+ assign alert_class_shadowed_53_we = addr_hit[181] & reg_we & !reg_error;
assign alert_class_shadowed_53_wd = reg_wdata[1:0];
- assign alert_class_shadowed_54_re = addr_hit[180] & reg_re & !reg_error;
- assign alert_class_shadowed_54_we = addr_hit[180] & reg_we & !reg_error;
+ assign alert_class_shadowed_54_re = addr_hit[182] & reg_re & !reg_error;
+ assign alert_class_shadowed_54_we = addr_hit[182] & reg_we & !reg_error;
assign alert_class_shadowed_54_wd = reg_wdata[1:0];
- assign alert_class_shadowed_55_re = addr_hit[181] & reg_re & !reg_error;
- assign alert_class_shadowed_55_we = addr_hit[181] & reg_we & !reg_error;
+ assign alert_class_shadowed_55_re = addr_hit[183] & reg_re & !reg_error;
+ assign alert_class_shadowed_55_we = addr_hit[183] & reg_we & !reg_error;
assign alert_class_shadowed_55_wd = reg_wdata[1:0];
- assign alert_class_shadowed_56_re = addr_hit[182] & reg_re & !reg_error;
- assign alert_class_shadowed_56_we = addr_hit[182] & reg_we & !reg_error;
+ assign alert_class_shadowed_56_re = addr_hit[184] & reg_re & !reg_error;
+ assign alert_class_shadowed_56_we = addr_hit[184] & reg_we & !reg_error;
assign alert_class_shadowed_56_wd = reg_wdata[1:0];
- assign alert_class_shadowed_57_re = addr_hit[183] & reg_re & !reg_error;
- assign alert_class_shadowed_57_we = addr_hit[183] & reg_we & !reg_error;
+ assign alert_class_shadowed_57_re = addr_hit[185] & reg_re & !reg_error;
+ assign alert_class_shadowed_57_we = addr_hit[185] & reg_we & !reg_error;
assign alert_class_shadowed_57_wd = reg_wdata[1:0];
- assign alert_class_shadowed_58_re = addr_hit[184] & reg_re & !reg_error;
- assign alert_class_shadowed_58_we = addr_hit[184] & reg_we & !reg_error;
+ assign alert_class_shadowed_58_re = addr_hit[186] & reg_re & !reg_error;
+ assign alert_class_shadowed_58_we = addr_hit[186] & reg_we & !reg_error;
assign alert_class_shadowed_58_wd = reg_wdata[1:0];
- assign alert_class_shadowed_59_re = addr_hit[185] & reg_re & !reg_error;
- assign alert_class_shadowed_59_we = addr_hit[185] & reg_we & !reg_error;
+ assign alert_class_shadowed_59_re = addr_hit[187] & reg_re & !reg_error;
+ assign alert_class_shadowed_59_we = addr_hit[187] & reg_we & !reg_error;
assign alert_class_shadowed_59_wd = reg_wdata[1:0];
- assign alert_cause_0_we = addr_hit[186] & reg_we & !reg_error;
+ assign alert_class_shadowed_60_re = addr_hit[188] & reg_re & !reg_error;
+ assign alert_class_shadowed_60_we = addr_hit[188] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_60_wd = reg_wdata[1:0];
+ assign alert_cause_0_we = addr_hit[189] & reg_we & !reg_error;
assign alert_cause_0_wd = reg_wdata[0];
- assign alert_cause_1_we = addr_hit[187] & reg_we & !reg_error;
+ assign alert_cause_1_we = addr_hit[190] & reg_we & !reg_error;
assign alert_cause_1_wd = reg_wdata[0];
- assign alert_cause_2_we = addr_hit[188] & reg_we & !reg_error;
+ assign alert_cause_2_we = addr_hit[191] & reg_we & !reg_error;
assign alert_cause_2_wd = reg_wdata[0];
- assign alert_cause_3_we = addr_hit[189] & reg_we & !reg_error;
+ assign alert_cause_3_we = addr_hit[192] & reg_we & !reg_error;
assign alert_cause_3_wd = reg_wdata[0];
- assign alert_cause_4_we = addr_hit[190] & reg_we & !reg_error;
+ assign alert_cause_4_we = addr_hit[193] & reg_we & !reg_error;
assign alert_cause_4_wd = reg_wdata[0];
- assign alert_cause_5_we = addr_hit[191] & reg_we & !reg_error;
+ assign alert_cause_5_we = addr_hit[194] & reg_we & !reg_error;
assign alert_cause_5_wd = reg_wdata[0];
- assign alert_cause_6_we = addr_hit[192] & reg_we & !reg_error;
+ assign alert_cause_6_we = addr_hit[195] & reg_we & !reg_error;
assign alert_cause_6_wd = reg_wdata[0];
- assign alert_cause_7_we = addr_hit[193] & reg_we & !reg_error;
+ assign alert_cause_7_we = addr_hit[196] & reg_we & !reg_error;
assign alert_cause_7_wd = reg_wdata[0];
- assign alert_cause_8_we = addr_hit[194] & reg_we & !reg_error;
+ assign alert_cause_8_we = addr_hit[197] & reg_we & !reg_error;
assign alert_cause_8_wd = reg_wdata[0];
- assign alert_cause_9_we = addr_hit[195] & reg_we & !reg_error;
+ assign alert_cause_9_we = addr_hit[198] & reg_we & !reg_error;
assign alert_cause_9_wd = reg_wdata[0];
- assign alert_cause_10_we = addr_hit[196] & reg_we & !reg_error;
+ assign alert_cause_10_we = addr_hit[199] & reg_we & !reg_error;
assign alert_cause_10_wd = reg_wdata[0];
- assign alert_cause_11_we = addr_hit[197] & reg_we & !reg_error;
+ assign alert_cause_11_we = addr_hit[200] & reg_we & !reg_error;
assign alert_cause_11_wd = reg_wdata[0];
- assign alert_cause_12_we = addr_hit[198] & reg_we & !reg_error;
+ assign alert_cause_12_we = addr_hit[201] & reg_we & !reg_error;
assign alert_cause_12_wd = reg_wdata[0];
- assign alert_cause_13_we = addr_hit[199] & reg_we & !reg_error;
+ assign alert_cause_13_we = addr_hit[202] & reg_we & !reg_error;
assign alert_cause_13_wd = reg_wdata[0];
- assign alert_cause_14_we = addr_hit[200] & reg_we & !reg_error;
+ assign alert_cause_14_we = addr_hit[203] & reg_we & !reg_error;
assign alert_cause_14_wd = reg_wdata[0];
- assign alert_cause_15_we = addr_hit[201] & reg_we & !reg_error;
+ assign alert_cause_15_we = addr_hit[204] & reg_we & !reg_error;
assign alert_cause_15_wd = reg_wdata[0];
- assign alert_cause_16_we = addr_hit[202] & reg_we & !reg_error;
+ assign alert_cause_16_we = addr_hit[205] & reg_we & !reg_error;
assign alert_cause_16_wd = reg_wdata[0];
- assign alert_cause_17_we = addr_hit[203] & reg_we & !reg_error;
+ assign alert_cause_17_we = addr_hit[206] & reg_we & !reg_error;
assign alert_cause_17_wd = reg_wdata[0];
- assign alert_cause_18_we = addr_hit[204] & reg_we & !reg_error;
+ assign alert_cause_18_we = addr_hit[207] & reg_we & !reg_error;
assign alert_cause_18_wd = reg_wdata[0];
- assign alert_cause_19_we = addr_hit[205] & reg_we & !reg_error;
+ assign alert_cause_19_we = addr_hit[208] & reg_we & !reg_error;
assign alert_cause_19_wd = reg_wdata[0];
- assign alert_cause_20_we = addr_hit[206] & reg_we & !reg_error;
+ assign alert_cause_20_we = addr_hit[209] & reg_we & !reg_error;
assign alert_cause_20_wd = reg_wdata[0];
- assign alert_cause_21_we = addr_hit[207] & reg_we & !reg_error;
+ assign alert_cause_21_we = addr_hit[210] & reg_we & !reg_error;
assign alert_cause_21_wd = reg_wdata[0];
- assign alert_cause_22_we = addr_hit[208] & reg_we & !reg_error;
+ assign alert_cause_22_we = addr_hit[211] & reg_we & !reg_error;
assign alert_cause_22_wd = reg_wdata[0];
- assign alert_cause_23_we = addr_hit[209] & reg_we & !reg_error;
+ assign alert_cause_23_we = addr_hit[212] & reg_we & !reg_error;
assign alert_cause_23_wd = reg_wdata[0];
- assign alert_cause_24_we = addr_hit[210] & reg_we & !reg_error;
+ assign alert_cause_24_we = addr_hit[213] & reg_we & !reg_error;
assign alert_cause_24_wd = reg_wdata[0];
- assign alert_cause_25_we = addr_hit[211] & reg_we & !reg_error;
+ assign alert_cause_25_we = addr_hit[214] & reg_we & !reg_error;
assign alert_cause_25_wd = reg_wdata[0];
- assign alert_cause_26_we = addr_hit[212] & reg_we & !reg_error;
+ assign alert_cause_26_we = addr_hit[215] & reg_we & !reg_error;
assign alert_cause_26_wd = reg_wdata[0];
- assign alert_cause_27_we = addr_hit[213] & reg_we & !reg_error;
+ assign alert_cause_27_we = addr_hit[216] & reg_we & !reg_error;
assign alert_cause_27_wd = reg_wdata[0];
- assign alert_cause_28_we = addr_hit[214] & reg_we & !reg_error;
+ assign alert_cause_28_we = addr_hit[217] & reg_we & !reg_error;
assign alert_cause_28_wd = reg_wdata[0];
- assign alert_cause_29_we = addr_hit[215] & reg_we & !reg_error;
+ assign alert_cause_29_we = addr_hit[218] & reg_we & !reg_error;
assign alert_cause_29_wd = reg_wdata[0];
- assign alert_cause_30_we = addr_hit[216] & reg_we & !reg_error;
+ assign alert_cause_30_we = addr_hit[219] & reg_we & !reg_error;
assign alert_cause_30_wd = reg_wdata[0];
- assign alert_cause_31_we = addr_hit[217] & reg_we & !reg_error;
+ assign alert_cause_31_we = addr_hit[220] & reg_we & !reg_error;
assign alert_cause_31_wd = reg_wdata[0];
- assign alert_cause_32_we = addr_hit[218] & reg_we & !reg_error;
+ assign alert_cause_32_we = addr_hit[221] & reg_we & !reg_error;
assign alert_cause_32_wd = reg_wdata[0];
- assign alert_cause_33_we = addr_hit[219] & reg_we & !reg_error;
+ assign alert_cause_33_we = addr_hit[222] & reg_we & !reg_error;
assign alert_cause_33_wd = reg_wdata[0];
- assign alert_cause_34_we = addr_hit[220] & reg_we & !reg_error;
+ assign alert_cause_34_we = addr_hit[223] & reg_we & !reg_error;
assign alert_cause_34_wd = reg_wdata[0];
- assign alert_cause_35_we = addr_hit[221] & reg_we & !reg_error;
+ assign alert_cause_35_we = addr_hit[224] & reg_we & !reg_error;
assign alert_cause_35_wd = reg_wdata[0];
- assign alert_cause_36_we = addr_hit[222] & reg_we & !reg_error;
+ assign alert_cause_36_we = addr_hit[225] & reg_we & !reg_error;
assign alert_cause_36_wd = reg_wdata[0];
- assign alert_cause_37_we = addr_hit[223] & reg_we & !reg_error;
+ assign alert_cause_37_we = addr_hit[226] & reg_we & !reg_error;
assign alert_cause_37_wd = reg_wdata[0];
- assign alert_cause_38_we = addr_hit[224] & reg_we & !reg_error;
+ assign alert_cause_38_we = addr_hit[227] & reg_we & !reg_error;
assign alert_cause_38_wd = reg_wdata[0];
- assign alert_cause_39_we = addr_hit[225] & reg_we & !reg_error;
+ assign alert_cause_39_we = addr_hit[228] & reg_we & !reg_error;
assign alert_cause_39_wd = reg_wdata[0];
- assign alert_cause_40_we = addr_hit[226] & reg_we & !reg_error;
+ assign alert_cause_40_we = addr_hit[229] & reg_we & !reg_error;
assign alert_cause_40_wd = reg_wdata[0];
- assign alert_cause_41_we = addr_hit[227] & reg_we & !reg_error;
+ assign alert_cause_41_we = addr_hit[230] & reg_we & !reg_error;
assign alert_cause_41_wd = reg_wdata[0];
- assign alert_cause_42_we = addr_hit[228] & reg_we & !reg_error;
+ assign alert_cause_42_we = addr_hit[231] & reg_we & !reg_error;
assign alert_cause_42_wd = reg_wdata[0];
- assign alert_cause_43_we = addr_hit[229] & reg_we & !reg_error;
+ assign alert_cause_43_we = addr_hit[232] & reg_we & !reg_error;
assign alert_cause_43_wd = reg_wdata[0];
- assign alert_cause_44_we = addr_hit[230] & reg_we & !reg_error;
+ assign alert_cause_44_we = addr_hit[233] & reg_we & !reg_error;
assign alert_cause_44_wd = reg_wdata[0];
- assign alert_cause_45_we = addr_hit[231] & reg_we & !reg_error;
+ assign alert_cause_45_we = addr_hit[234] & reg_we & !reg_error;
assign alert_cause_45_wd = reg_wdata[0];
- assign alert_cause_46_we = addr_hit[232] & reg_we & !reg_error;
+ assign alert_cause_46_we = addr_hit[235] & reg_we & !reg_error;
assign alert_cause_46_wd = reg_wdata[0];
- assign alert_cause_47_we = addr_hit[233] & reg_we & !reg_error;
+ assign alert_cause_47_we = addr_hit[236] & reg_we & !reg_error;
assign alert_cause_47_wd = reg_wdata[0];
- assign alert_cause_48_we = addr_hit[234] & reg_we & !reg_error;
+ assign alert_cause_48_we = addr_hit[237] & reg_we & !reg_error;
assign alert_cause_48_wd = reg_wdata[0];
- assign alert_cause_49_we = addr_hit[235] & reg_we & !reg_error;
+ assign alert_cause_49_we = addr_hit[238] & reg_we & !reg_error;
assign alert_cause_49_wd = reg_wdata[0];
- assign alert_cause_50_we = addr_hit[236] & reg_we & !reg_error;
+ assign alert_cause_50_we = addr_hit[239] & reg_we & !reg_error;
assign alert_cause_50_wd = reg_wdata[0];
- assign alert_cause_51_we = addr_hit[237] & reg_we & !reg_error;
+ assign alert_cause_51_we = addr_hit[240] & reg_we & !reg_error;
assign alert_cause_51_wd = reg_wdata[0];
- assign alert_cause_52_we = addr_hit[238] & reg_we & !reg_error;
+ assign alert_cause_52_we = addr_hit[241] & reg_we & !reg_error;
assign alert_cause_52_wd = reg_wdata[0];
- assign alert_cause_53_we = addr_hit[239] & reg_we & !reg_error;
+ assign alert_cause_53_we = addr_hit[242] & reg_we & !reg_error;
assign alert_cause_53_wd = reg_wdata[0];
- assign alert_cause_54_we = addr_hit[240] & reg_we & !reg_error;
+ assign alert_cause_54_we = addr_hit[243] & reg_we & !reg_error;
assign alert_cause_54_wd = reg_wdata[0];
- assign alert_cause_55_we = addr_hit[241] & reg_we & !reg_error;
+ assign alert_cause_55_we = addr_hit[244] & reg_we & !reg_error;
assign alert_cause_55_wd = reg_wdata[0];
- assign alert_cause_56_we = addr_hit[242] & reg_we & !reg_error;
+ assign alert_cause_56_we = addr_hit[245] & reg_we & !reg_error;
assign alert_cause_56_wd = reg_wdata[0];
- assign alert_cause_57_we = addr_hit[243] & reg_we & !reg_error;
+ assign alert_cause_57_we = addr_hit[246] & reg_we & !reg_error;
assign alert_cause_57_wd = reg_wdata[0];
- assign alert_cause_58_we = addr_hit[244] & reg_we & !reg_error;
+ assign alert_cause_58_we = addr_hit[247] & reg_we & !reg_error;
assign alert_cause_58_wd = reg_wdata[0];
- assign alert_cause_59_we = addr_hit[245] & reg_we & !reg_error;
+ assign alert_cause_59_we = addr_hit[248] & reg_we & !reg_error;
assign alert_cause_59_wd = reg_wdata[0];
- assign loc_alert_regwen_0_we = addr_hit[246] & reg_we & !reg_error;
+ assign alert_cause_60_we = addr_hit[249] & reg_we & !reg_error;
+
+ assign alert_cause_60_wd = reg_wdata[0];
+ assign loc_alert_regwen_0_we = addr_hit[250] & reg_we & !reg_error;
assign loc_alert_regwen_0_wd = reg_wdata[0];
- assign loc_alert_regwen_1_we = addr_hit[247] & reg_we & !reg_error;
+ assign loc_alert_regwen_1_we = addr_hit[251] & reg_we & !reg_error;
assign loc_alert_regwen_1_wd = reg_wdata[0];
- assign loc_alert_regwen_2_we = addr_hit[248] & reg_we & !reg_error;
+ assign loc_alert_regwen_2_we = addr_hit[252] & reg_we & !reg_error;
assign loc_alert_regwen_2_wd = reg_wdata[0];
- assign loc_alert_regwen_3_we = addr_hit[249] & reg_we & !reg_error;
+ assign loc_alert_regwen_3_we = addr_hit[253] & reg_we & !reg_error;
assign loc_alert_regwen_3_wd = reg_wdata[0];
- assign loc_alert_regwen_4_we = addr_hit[250] & reg_we & !reg_error;
+ assign loc_alert_regwen_4_we = addr_hit[254] & reg_we & !reg_error;
assign loc_alert_regwen_4_wd = reg_wdata[0];
- assign loc_alert_regwen_5_we = addr_hit[251] & reg_we & !reg_error;
+ assign loc_alert_regwen_5_we = addr_hit[255] & reg_we & !reg_error;
assign loc_alert_regwen_5_wd = reg_wdata[0];
- assign loc_alert_regwen_6_we = addr_hit[252] & reg_we & !reg_error;
+ assign loc_alert_regwen_6_we = addr_hit[256] & reg_we & !reg_error;
assign loc_alert_regwen_6_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_0_re = addr_hit[253] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_0_we = addr_hit[253] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_0_re = addr_hit[257] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_0_we = addr_hit[257] & reg_we & !reg_error;
assign loc_alert_en_shadowed_0_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_1_re = addr_hit[254] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_1_we = addr_hit[254] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_1_re = addr_hit[258] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_1_we = addr_hit[258] & reg_we & !reg_error;
assign loc_alert_en_shadowed_1_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_2_re = addr_hit[255] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_2_we = addr_hit[255] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_2_re = addr_hit[259] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_2_we = addr_hit[259] & reg_we & !reg_error;
assign loc_alert_en_shadowed_2_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_3_re = addr_hit[256] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_3_we = addr_hit[256] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_3_re = addr_hit[260] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_3_we = addr_hit[260] & reg_we & !reg_error;
assign loc_alert_en_shadowed_3_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_4_re = addr_hit[257] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_4_we = addr_hit[257] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_4_re = addr_hit[261] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_4_we = addr_hit[261] & reg_we & !reg_error;
assign loc_alert_en_shadowed_4_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_5_re = addr_hit[258] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_5_we = addr_hit[258] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_5_re = addr_hit[262] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_5_we = addr_hit[262] & reg_we & !reg_error;
assign loc_alert_en_shadowed_5_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_6_re = addr_hit[259] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_6_we = addr_hit[259] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_6_re = addr_hit[263] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_6_we = addr_hit[263] & reg_we & !reg_error;
assign loc_alert_en_shadowed_6_wd = reg_wdata[0];
- assign loc_alert_class_shadowed_0_re = addr_hit[260] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_0_we = addr_hit[260] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_0_re = addr_hit[264] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_0_we = addr_hit[264] & reg_we & !reg_error;
assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_1_re = addr_hit[261] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_1_we = addr_hit[261] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_1_re = addr_hit[265] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_1_we = addr_hit[265] & reg_we & !reg_error;
assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_2_re = addr_hit[262] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_2_we = addr_hit[262] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_2_re = addr_hit[266] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_2_we = addr_hit[266] & reg_we & !reg_error;
assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_3_re = addr_hit[263] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_3_we = addr_hit[263] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_3_re = addr_hit[267] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_3_we = addr_hit[267] & reg_we & !reg_error;
assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_4_re = addr_hit[264] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_4_we = addr_hit[264] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_4_re = addr_hit[268] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_4_we = addr_hit[268] & reg_we & !reg_error;
assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_5_re = addr_hit[265] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_5_we = addr_hit[265] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_5_re = addr_hit[269] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_5_we = addr_hit[269] & reg_we & !reg_error;
assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_6_re = addr_hit[266] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_6_we = addr_hit[266] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_6_re = addr_hit[270] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_6_we = addr_hit[270] & reg_we & !reg_error;
assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0];
- assign loc_alert_cause_0_we = addr_hit[267] & reg_we & !reg_error;
+ assign loc_alert_cause_0_we = addr_hit[271] & reg_we & !reg_error;
assign loc_alert_cause_0_wd = reg_wdata[0];
- assign loc_alert_cause_1_we = addr_hit[268] & reg_we & !reg_error;
+ assign loc_alert_cause_1_we = addr_hit[272] & reg_we & !reg_error;
assign loc_alert_cause_1_wd = reg_wdata[0];
- assign loc_alert_cause_2_we = addr_hit[269] & reg_we & !reg_error;
+ assign loc_alert_cause_2_we = addr_hit[273] & reg_we & !reg_error;
assign loc_alert_cause_2_wd = reg_wdata[0];
- assign loc_alert_cause_3_we = addr_hit[270] & reg_we & !reg_error;
+ assign loc_alert_cause_3_we = addr_hit[274] & reg_we & !reg_error;
assign loc_alert_cause_3_wd = reg_wdata[0];
- assign loc_alert_cause_4_we = addr_hit[271] & reg_we & !reg_error;
+ assign loc_alert_cause_4_we = addr_hit[275] & reg_we & !reg_error;
assign loc_alert_cause_4_wd = reg_wdata[0];
- assign loc_alert_cause_5_we = addr_hit[272] & reg_we & !reg_error;
+ assign loc_alert_cause_5_we = addr_hit[276] & reg_we & !reg_error;
assign loc_alert_cause_5_wd = reg_wdata[0];
- assign loc_alert_cause_6_we = addr_hit[273] & reg_we & !reg_error;
+ assign loc_alert_cause_6_we = addr_hit[277] & reg_we & !reg_error;
assign loc_alert_cause_6_wd = reg_wdata[0];
- assign classa_regwen_we = addr_hit[274] & reg_we & !reg_error;
+ assign classa_regwen_we = addr_hit[278] & reg_we & !reg_error;
assign classa_regwen_wd = reg_wdata[0];
- assign classa_ctrl_shadowed_re = addr_hit[275] & reg_re & !reg_error;
- assign classa_ctrl_shadowed_we = addr_hit[275] & reg_we & !reg_error;
+ assign classa_ctrl_shadowed_re = addr_hit[279] & reg_re & !reg_error;
+ assign classa_ctrl_shadowed_we = addr_hit[279] & reg_we & !reg_error;
assign classa_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -14751,49 +14913,49 @@
assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classa_clr_regwen_we = addr_hit[276] & reg_we & !reg_error;
+ assign classa_clr_regwen_we = addr_hit[280] & reg_we & !reg_error;
assign classa_clr_regwen_wd = reg_wdata[0];
- assign classa_clr_shadowed_re = addr_hit[277] & reg_re & !reg_error;
- assign classa_clr_shadowed_we = addr_hit[277] & reg_we & !reg_error;
+ assign classa_clr_shadowed_re = addr_hit[281] & reg_re & !reg_error;
+ assign classa_clr_shadowed_we = addr_hit[281] & reg_we & !reg_error;
assign classa_clr_shadowed_wd = reg_wdata[0];
- assign classa_accum_cnt_re = addr_hit[278] & reg_re & !reg_error;
- assign classa_accum_thresh_shadowed_re = addr_hit[279] & reg_re & !reg_error;
- assign classa_accum_thresh_shadowed_we = addr_hit[279] & reg_we & !reg_error;
+ assign classa_accum_cnt_re = addr_hit[282] & reg_re & !reg_error;
+ assign classa_accum_thresh_shadowed_re = addr_hit[283] & reg_re & !reg_error;
+ assign classa_accum_thresh_shadowed_we = addr_hit[283] & reg_we & !reg_error;
assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classa_timeout_cyc_shadowed_re = addr_hit[280] & reg_re & !reg_error;
- assign classa_timeout_cyc_shadowed_we = addr_hit[280] & reg_we & !reg_error;
+ assign classa_timeout_cyc_shadowed_re = addr_hit[284] & reg_re & !reg_error;
+ assign classa_timeout_cyc_shadowed_we = addr_hit[284] & reg_we & !reg_error;
assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_crashdump_trigger_shadowed_re = addr_hit[281] & reg_re & !reg_error;
- assign classa_crashdump_trigger_shadowed_we = addr_hit[281] & reg_we & !reg_error;
+ assign classa_crashdump_trigger_shadowed_re = addr_hit[285] & reg_re & !reg_error;
+ assign classa_crashdump_trigger_shadowed_we = addr_hit[285] & reg_we & !reg_error;
assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classa_phase0_cyc_shadowed_re = addr_hit[282] & reg_re & !reg_error;
- assign classa_phase0_cyc_shadowed_we = addr_hit[282] & reg_we & !reg_error;
+ assign classa_phase0_cyc_shadowed_re = addr_hit[286] & reg_re & !reg_error;
+ assign classa_phase0_cyc_shadowed_we = addr_hit[286] & reg_we & !reg_error;
assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_phase1_cyc_shadowed_re = addr_hit[283] & reg_re & !reg_error;
- assign classa_phase1_cyc_shadowed_we = addr_hit[283] & reg_we & !reg_error;
+ assign classa_phase1_cyc_shadowed_re = addr_hit[287] & reg_re & !reg_error;
+ assign classa_phase1_cyc_shadowed_we = addr_hit[287] & reg_we & !reg_error;
assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_phase2_cyc_shadowed_re = addr_hit[284] & reg_re & !reg_error;
- assign classa_phase2_cyc_shadowed_we = addr_hit[284] & reg_we & !reg_error;
+ assign classa_phase2_cyc_shadowed_re = addr_hit[288] & reg_re & !reg_error;
+ assign classa_phase2_cyc_shadowed_we = addr_hit[288] & reg_we & !reg_error;
assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_phase3_cyc_shadowed_re = addr_hit[285] & reg_re & !reg_error;
- assign classa_phase3_cyc_shadowed_we = addr_hit[285] & reg_we & !reg_error;
+ assign classa_phase3_cyc_shadowed_re = addr_hit[289] & reg_re & !reg_error;
+ assign classa_phase3_cyc_shadowed_we = addr_hit[289] & reg_we & !reg_error;
assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_esc_cnt_re = addr_hit[286] & reg_re & !reg_error;
- assign classa_state_re = addr_hit[287] & reg_re & !reg_error;
- assign classb_regwen_we = addr_hit[288] & reg_we & !reg_error;
+ assign classa_esc_cnt_re = addr_hit[290] & reg_re & !reg_error;
+ assign classa_state_re = addr_hit[291] & reg_re & !reg_error;
+ assign classb_regwen_we = addr_hit[292] & reg_we & !reg_error;
assign classb_regwen_wd = reg_wdata[0];
- assign classb_ctrl_shadowed_re = addr_hit[289] & reg_re & !reg_error;
- assign classb_ctrl_shadowed_we = addr_hit[289] & reg_we & !reg_error;
+ assign classb_ctrl_shadowed_re = addr_hit[293] & reg_re & !reg_error;
+ assign classb_ctrl_shadowed_we = addr_hit[293] & reg_we & !reg_error;
assign classb_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -14814,49 +14976,49 @@
assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classb_clr_regwen_we = addr_hit[290] & reg_we & !reg_error;
+ assign classb_clr_regwen_we = addr_hit[294] & reg_we & !reg_error;
assign classb_clr_regwen_wd = reg_wdata[0];
- assign classb_clr_shadowed_re = addr_hit[291] & reg_re & !reg_error;
- assign classb_clr_shadowed_we = addr_hit[291] & reg_we & !reg_error;
+ assign classb_clr_shadowed_re = addr_hit[295] & reg_re & !reg_error;
+ assign classb_clr_shadowed_we = addr_hit[295] & reg_we & !reg_error;
assign classb_clr_shadowed_wd = reg_wdata[0];
- assign classb_accum_cnt_re = addr_hit[292] & reg_re & !reg_error;
- assign classb_accum_thresh_shadowed_re = addr_hit[293] & reg_re & !reg_error;
- assign classb_accum_thresh_shadowed_we = addr_hit[293] & reg_we & !reg_error;
+ assign classb_accum_cnt_re = addr_hit[296] & reg_re & !reg_error;
+ assign classb_accum_thresh_shadowed_re = addr_hit[297] & reg_re & !reg_error;
+ assign classb_accum_thresh_shadowed_we = addr_hit[297] & reg_we & !reg_error;
assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classb_timeout_cyc_shadowed_re = addr_hit[294] & reg_re & !reg_error;
- assign classb_timeout_cyc_shadowed_we = addr_hit[294] & reg_we & !reg_error;
+ assign classb_timeout_cyc_shadowed_re = addr_hit[298] & reg_re & !reg_error;
+ assign classb_timeout_cyc_shadowed_we = addr_hit[298] & reg_we & !reg_error;
assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_crashdump_trigger_shadowed_re = addr_hit[295] & reg_re & !reg_error;
- assign classb_crashdump_trigger_shadowed_we = addr_hit[295] & reg_we & !reg_error;
+ assign classb_crashdump_trigger_shadowed_re = addr_hit[299] & reg_re & !reg_error;
+ assign classb_crashdump_trigger_shadowed_we = addr_hit[299] & reg_we & !reg_error;
assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classb_phase0_cyc_shadowed_re = addr_hit[296] & reg_re & !reg_error;
- assign classb_phase0_cyc_shadowed_we = addr_hit[296] & reg_we & !reg_error;
+ assign classb_phase0_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error;
+ assign classb_phase0_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error;
assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_phase1_cyc_shadowed_re = addr_hit[297] & reg_re & !reg_error;
- assign classb_phase1_cyc_shadowed_we = addr_hit[297] & reg_we & !reg_error;
+ assign classb_phase1_cyc_shadowed_re = addr_hit[301] & reg_re & !reg_error;
+ assign classb_phase1_cyc_shadowed_we = addr_hit[301] & reg_we & !reg_error;
assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_phase2_cyc_shadowed_re = addr_hit[298] & reg_re & !reg_error;
- assign classb_phase2_cyc_shadowed_we = addr_hit[298] & reg_we & !reg_error;
+ assign classb_phase2_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error;
+ assign classb_phase2_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error;
assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_phase3_cyc_shadowed_re = addr_hit[299] & reg_re & !reg_error;
- assign classb_phase3_cyc_shadowed_we = addr_hit[299] & reg_we & !reg_error;
+ assign classb_phase3_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error;
+ assign classb_phase3_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error;
assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_esc_cnt_re = addr_hit[300] & reg_re & !reg_error;
- assign classb_state_re = addr_hit[301] & reg_re & !reg_error;
- assign classc_regwen_we = addr_hit[302] & reg_we & !reg_error;
+ assign classb_esc_cnt_re = addr_hit[304] & reg_re & !reg_error;
+ assign classb_state_re = addr_hit[305] & reg_re & !reg_error;
+ assign classc_regwen_we = addr_hit[306] & reg_we & !reg_error;
assign classc_regwen_wd = reg_wdata[0];
- assign classc_ctrl_shadowed_re = addr_hit[303] & reg_re & !reg_error;
- assign classc_ctrl_shadowed_we = addr_hit[303] & reg_we & !reg_error;
+ assign classc_ctrl_shadowed_re = addr_hit[307] & reg_re & !reg_error;
+ assign classc_ctrl_shadowed_we = addr_hit[307] & reg_we & !reg_error;
assign classc_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -14877,49 +15039,49 @@
assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classc_clr_regwen_we = addr_hit[304] & reg_we & !reg_error;
+ assign classc_clr_regwen_we = addr_hit[308] & reg_we & !reg_error;
assign classc_clr_regwen_wd = reg_wdata[0];
- assign classc_clr_shadowed_re = addr_hit[305] & reg_re & !reg_error;
- assign classc_clr_shadowed_we = addr_hit[305] & reg_we & !reg_error;
+ assign classc_clr_shadowed_re = addr_hit[309] & reg_re & !reg_error;
+ assign classc_clr_shadowed_we = addr_hit[309] & reg_we & !reg_error;
assign classc_clr_shadowed_wd = reg_wdata[0];
- assign classc_accum_cnt_re = addr_hit[306] & reg_re & !reg_error;
- assign classc_accum_thresh_shadowed_re = addr_hit[307] & reg_re & !reg_error;
- assign classc_accum_thresh_shadowed_we = addr_hit[307] & reg_we & !reg_error;
+ assign classc_accum_cnt_re = addr_hit[310] & reg_re & !reg_error;
+ assign classc_accum_thresh_shadowed_re = addr_hit[311] & reg_re & !reg_error;
+ assign classc_accum_thresh_shadowed_we = addr_hit[311] & reg_we & !reg_error;
assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classc_timeout_cyc_shadowed_re = addr_hit[308] & reg_re & !reg_error;
- assign classc_timeout_cyc_shadowed_we = addr_hit[308] & reg_we & !reg_error;
+ assign classc_timeout_cyc_shadowed_re = addr_hit[312] & reg_re & !reg_error;
+ assign classc_timeout_cyc_shadowed_we = addr_hit[312] & reg_we & !reg_error;
assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_crashdump_trigger_shadowed_re = addr_hit[309] & reg_re & !reg_error;
- assign classc_crashdump_trigger_shadowed_we = addr_hit[309] & reg_we & !reg_error;
+ assign classc_crashdump_trigger_shadowed_re = addr_hit[313] & reg_re & !reg_error;
+ assign classc_crashdump_trigger_shadowed_we = addr_hit[313] & reg_we & !reg_error;
assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classc_phase0_cyc_shadowed_re = addr_hit[310] & reg_re & !reg_error;
- assign classc_phase0_cyc_shadowed_we = addr_hit[310] & reg_we & !reg_error;
+ assign classc_phase0_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error;
+ assign classc_phase0_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error;
assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_phase1_cyc_shadowed_re = addr_hit[311] & reg_re & !reg_error;
- assign classc_phase1_cyc_shadowed_we = addr_hit[311] & reg_we & !reg_error;
+ assign classc_phase1_cyc_shadowed_re = addr_hit[315] & reg_re & !reg_error;
+ assign classc_phase1_cyc_shadowed_we = addr_hit[315] & reg_we & !reg_error;
assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_phase2_cyc_shadowed_re = addr_hit[312] & reg_re & !reg_error;
- assign classc_phase2_cyc_shadowed_we = addr_hit[312] & reg_we & !reg_error;
+ assign classc_phase2_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error;
+ assign classc_phase2_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error;
assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_phase3_cyc_shadowed_re = addr_hit[313] & reg_re & !reg_error;
- assign classc_phase3_cyc_shadowed_we = addr_hit[313] & reg_we & !reg_error;
+ assign classc_phase3_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error;
+ assign classc_phase3_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error;
assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_esc_cnt_re = addr_hit[314] & reg_re & !reg_error;
- assign classc_state_re = addr_hit[315] & reg_re & !reg_error;
- assign classd_regwen_we = addr_hit[316] & reg_we & !reg_error;
+ assign classc_esc_cnt_re = addr_hit[318] & reg_re & !reg_error;
+ assign classc_state_re = addr_hit[319] & reg_re & !reg_error;
+ assign classd_regwen_we = addr_hit[320] & reg_we & !reg_error;
assign classd_regwen_wd = reg_wdata[0];
- assign classd_ctrl_shadowed_re = addr_hit[317] & reg_re & !reg_error;
- assign classd_ctrl_shadowed_we = addr_hit[317] & reg_we & !reg_error;
+ assign classd_ctrl_shadowed_re = addr_hit[321] & reg_re & !reg_error;
+ assign classd_ctrl_shadowed_we = addr_hit[321] & reg_we & !reg_error;
assign classd_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -14940,44 +15102,44 @@
assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classd_clr_regwen_we = addr_hit[318] & reg_we & !reg_error;
+ assign classd_clr_regwen_we = addr_hit[322] & reg_we & !reg_error;
assign classd_clr_regwen_wd = reg_wdata[0];
- assign classd_clr_shadowed_re = addr_hit[319] & reg_re & !reg_error;
- assign classd_clr_shadowed_we = addr_hit[319] & reg_we & !reg_error;
+ assign classd_clr_shadowed_re = addr_hit[323] & reg_re & !reg_error;
+ assign classd_clr_shadowed_we = addr_hit[323] & reg_we & !reg_error;
assign classd_clr_shadowed_wd = reg_wdata[0];
- assign classd_accum_cnt_re = addr_hit[320] & reg_re & !reg_error;
- assign classd_accum_thresh_shadowed_re = addr_hit[321] & reg_re & !reg_error;
- assign classd_accum_thresh_shadowed_we = addr_hit[321] & reg_we & !reg_error;
+ assign classd_accum_cnt_re = addr_hit[324] & reg_re & !reg_error;
+ assign classd_accum_thresh_shadowed_re = addr_hit[325] & reg_re & !reg_error;
+ assign classd_accum_thresh_shadowed_we = addr_hit[325] & reg_we & !reg_error;
assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classd_timeout_cyc_shadowed_re = addr_hit[322] & reg_re & !reg_error;
- assign classd_timeout_cyc_shadowed_we = addr_hit[322] & reg_we & !reg_error;
+ assign classd_timeout_cyc_shadowed_re = addr_hit[326] & reg_re & !reg_error;
+ assign classd_timeout_cyc_shadowed_we = addr_hit[326] & reg_we & !reg_error;
assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_crashdump_trigger_shadowed_re = addr_hit[323] & reg_re & !reg_error;
- assign classd_crashdump_trigger_shadowed_we = addr_hit[323] & reg_we & !reg_error;
+ assign classd_crashdump_trigger_shadowed_re = addr_hit[327] & reg_re & !reg_error;
+ assign classd_crashdump_trigger_shadowed_we = addr_hit[327] & reg_we & !reg_error;
assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classd_phase0_cyc_shadowed_re = addr_hit[324] & reg_re & !reg_error;
- assign classd_phase0_cyc_shadowed_we = addr_hit[324] & reg_we & !reg_error;
+ assign classd_phase0_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error;
+ assign classd_phase0_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error;
assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_phase1_cyc_shadowed_re = addr_hit[325] & reg_re & !reg_error;
- assign classd_phase1_cyc_shadowed_we = addr_hit[325] & reg_we & !reg_error;
+ assign classd_phase1_cyc_shadowed_re = addr_hit[329] & reg_re & !reg_error;
+ assign classd_phase1_cyc_shadowed_we = addr_hit[329] & reg_we & !reg_error;
assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_phase2_cyc_shadowed_re = addr_hit[326] & reg_re & !reg_error;
- assign classd_phase2_cyc_shadowed_we = addr_hit[326] & reg_we & !reg_error;
+ assign classd_phase2_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error;
+ assign classd_phase2_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error;
assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_phase3_cyc_shadowed_re = addr_hit[327] & reg_re & !reg_error;
- assign classd_phase3_cyc_shadowed_we = addr_hit[327] & reg_we & !reg_error;
+ assign classd_phase3_cyc_shadowed_re = addr_hit[331] & reg_re & !reg_error;
+ assign classd_phase3_cyc_shadowed_we = addr_hit[331] & reg_we & !reg_error;
assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_esc_cnt_re = addr_hit[328] & reg_re & !reg_error;
- assign classd_state_re = addr_hit[329] & reg_re & !reg_error;
+ assign classd_esc_cnt_re = addr_hit[332] & reg_re & !reg_error;
+ assign classd_state_re = addr_hit[333] & reg_re & !reg_error;
// Read data return
always_comb begin
@@ -15257,842 +15419,858 @@
end
addr_hit[66]: begin
- reg_rdata_next[0] = alert_en_shadowed_0_qs;
+ reg_rdata_next[0] = alert_regwen_60_qs;
end
addr_hit[67]: begin
- reg_rdata_next[0] = alert_en_shadowed_1_qs;
+ reg_rdata_next[0] = alert_en_shadowed_0_qs;
end
addr_hit[68]: begin
- reg_rdata_next[0] = alert_en_shadowed_2_qs;
+ reg_rdata_next[0] = alert_en_shadowed_1_qs;
end
addr_hit[69]: begin
- reg_rdata_next[0] = alert_en_shadowed_3_qs;
+ reg_rdata_next[0] = alert_en_shadowed_2_qs;
end
addr_hit[70]: begin
- reg_rdata_next[0] = alert_en_shadowed_4_qs;
+ reg_rdata_next[0] = alert_en_shadowed_3_qs;
end
addr_hit[71]: begin
- reg_rdata_next[0] = alert_en_shadowed_5_qs;
+ reg_rdata_next[0] = alert_en_shadowed_4_qs;
end
addr_hit[72]: begin
- reg_rdata_next[0] = alert_en_shadowed_6_qs;
+ reg_rdata_next[0] = alert_en_shadowed_5_qs;
end
addr_hit[73]: begin
- reg_rdata_next[0] = alert_en_shadowed_7_qs;
+ reg_rdata_next[0] = alert_en_shadowed_6_qs;
end
addr_hit[74]: begin
- reg_rdata_next[0] = alert_en_shadowed_8_qs;
+ reg_rdata_next[0] = alert_en_shadowed_7_qs;
end
addr_hit[75]: begin
- reg_rdata_next[0] = alert_en_shadowed_9_qs;
+ reg_rdata_next[0] = alert_en_shadowed_8_qs;
end
addr_hit[76]: begin
- reg_rdata_next[0] = alert_en_shadowed_10_qs;
+ reg_rdata_next[0] = alert_en_shadowed_9_qs;
end
addr_hit[77]: begin
- reg_rdata_next[0] = alert_en_shadowed_11_qs;
+ reg_rdata_next[0] = alert_en_shadowed_10_qs;
end
addr_hit[78]: begin
- reg_rdata_next[0] = alert_en_shadowed_12_qs;
+ reg_rdata_next[0] = alert_en_shadowed_11_qs;
end
addr_hit[79]: begin
- reg_rdata_next[0] = alert_en_shadowed_13_qs;
+ reg_rdata_next[0] = alert_en_shadowed_12_qs;
end
addr_hit[80]: begin
- reg_rdata_next[0] = alert_en_shadowed_14_qs;
+ reg_rdata_next[0] = alert_en_shadowed_13_qs;
end
addr_hit[81]: begin
- reg_rdata_next[0] = alert_en_shadowed_15_qs;
+ reg_rdata_next[0] = alert_en_shadowed_14_qs;
end
addr_hit[82]: begin
- reg_rdata_next[0] = alert_en_shadowed_16_qs;
+ reg_rdata_next[0] = alert_en_shadowed_15_qs;
end
addr_hit[83]: begin
- reg_rdata_next[0] = alert_en_shadowed_17_qs;
+ reg_rdata_next[0] = alert_en_shadowed_16_qs;
end
addr_hit[84]: begin
- reg_rdata_next[0] = alert_en_shadowed_18_qs;
+ reg_rdata_next[0] = alert_en_shadowed_17_qs;
end
addr_hit[85]: begin
- reg_rdata_next[0] = alert_en_shadowed_19_qs;
+ reg_rdata_next[0] = alert_en_shadowed_18_qs;
end
addr_hit[86]: begin
- reg_rdata_next[0] = alert_en_shadowed_20_qs;
+ reg_rdata_next[0] = alert_en_shadowed_19_qs;
end
addr_hit[87]: begin
- reg_rdata_next[0] = alert_en_shadowed_21_qs;
+ reg_rdata_next[0] = alert_en_shadowed_20_qs;
end
addr_hit[88]: begin
- reg_rdata_next[0] = alert_en_shadowed_22_qs;
+ reg_rdata_next[0] = alert_en_shadowed_21_qs;
end
addr_hit[89]: begin
- reg_rdata_next[0] = alert_en_shadowed_23_qs;
+ reg_rdata_next[0] = alert_en_shadowed_22_qs;
end
addr_hit[90]: begin
- reg_rdata_next[0] = alert_en_shadowed_24_qs;
+ reg_rdata_next[0] = alert_en_shadowed_23_qs;
end
addr_hit[91]: begin
- reg_rdata_next[0] = alert_en_shadowed_25_qs;
+ reg_rdata_next[0] = alert_en_shadowed_24_qs;
end
addr_hit[92]: begin
- reg_rdata_next[0] = alert_en_shadowed_26_qs;
+ reg_rdata_next[0] = alert_en_shadowed_25_qs;
end
addr_hit[93]: begin
- reg_rdata_next[0] = alert_en_shadowed_27_qs;
+ reg_rdata_next[0] = alert_en_shadowed_26_qs;
end
addr_hit[94]: begin
- reg_rdata_next[0] = alert_en_shadowed_28_qs;
+ reg_rdata_next[0] = alert_en_shadowed_27_qs;
end
addr_hit[95]: begin
- reg_rdata_next[0] = alert_en_shadowed_29_qs;
+ reg_rdata_next[0] = alert_en_shadowed_28_qs;
end
addr_hit[96]: begin
- reg_rdata_next[0] = alert_en_shadowed_30_qs;
+ reg_rdata_next[0] = alert_en_shadowed_29_qs;
end
addr_hit[97]: begin
- reg_rdata_next[0] = alert_en_shadowed_31_qs;
+ reg_rdata_next[0] = alert_en_shadowed_30_qs;
end
addr_hit[98]: begin
- reg_rdata_next[0] = alert_en_shadowed_32_qs;
+ reg_rdata_next[0] = alert_en_shadowed_31_qs;
end
addr_hit[99]: begin
- reg_rdata_next[0] = alert_en_shadowed_33_qs;
+ reg_rdata_next[0] = alert_en_shadowed_32_qs;
end
addr_hit[100]: begin
- reg_rdata_next[0] = alert_en_shadowed_34_qs;
+ reg_rdata_next[0] = alert_en_shadowed_33_qs;
end
addr_hit[101]: begin
- reg_rdata_next[0] = alert_en_shadowed_35_qs;
+ reg_rdata_next[0] = alert_en_shadowed_34_qs;
end
addr_hit[102]: begin
- reg_rdata_next[0] = alert_en_shadowed_36_qs;
+ reg_rdata_next[0] = alert_en_shadowed_35_qs;
end
addr_hit[103]: begin
- reg_rdata_next[0] = alert_en_shadowed_37_qs;
+ reg_rdata_next[0] = alert_en_shadowed_36_qs;
end
addr_hit[104]: begin
- reg_rdata_next[0] = alert_en_shadowed_38_qs;
+ reg_rdata_next[0] = alert_en_shadowed_37_qs;
end
addr_hit[105]: begin
- reg_rdata_next[0] = alert_en_shadowed_39_qs;
+ reg_rdata_next[0] = alert_en_shadowed_38_qs;
end
addr_hit[106]: begin
- reg_rdata_next[0] = alert_en_shadowed_40_qs;
+ reg_rdata_next[0] = alert_en_shadowed_39_qs;
end
addr_hit[107]: begin
- reg_rdata_next[0] = alert_en_shadowed_41_qs;
+ reg_rdata_next[0] = alert_en_shadowed_40_qs;
end
addr_hit[108]: begin
- reg_rdata_next[0] = alert_en_shadowed_42_qs;
+ reg_rdata_next[0] = alert_en_shadowed_41_qs;
end
addr_hit[109]: begin
- reg_rdata_next[0] = alert_en_shadowed_43_qs;
+ reg_rdata_next[0] = alert_en_shadowed_42_qs;
end
addr_hit[110]: begin
- reg_rdata_next[0] = alert_en_shadowed_44_qs;
+ reg_rdata_next[0] = alert_en_shadowed_43_qs;
end
addr_hit[111]: begin
- reg_rdata_next[0] = alert_en_shadowed_45_qs;
+ reg_rdata_next[0] = alert_en_shadowed_44_qs;
end
addr_hit[112]: begin
- reg_rdata_next[0] = alert_en_shadowed_46_qs;
+ reg_rdata_next[0] = alert_en_shadowed_45_qs;
end
addr_hit[113]: begin
- reg_rdata_next[0] = alert_en_shadowed_47_qs;
+ reg_rdata_next[0] = alert_en_shadowed_46_qs;
end
addr_hit[114]: begin
- reg_rdata_next[0] = alert_en_shadowed_48_qs;
+ reg_rdata_next[0] = alert_en_shadowed_47_qs;
end
addr_hit[115]: begin
- reg_rdata_next[0] = alert_en_shadowed_49_qs;
+ reg_rdata_next[0] = alert_en_shadowed_48_qs;
end
addr_hit[116]: begin
- reg_rdata_next[0] = alert_en_shadowed_50_qs;
+ reg_rdata_next[0] = alert_en_shadowed_49_qs;
end
addr_hit[117]: begin
- reg_rdata_next[0] = alert_en_shadowed_51_qs;
+ reg_rdata_next[0] = alert_en_shadowed_50_qs;
end
addr_hit[118]: begin
- reg_rdata_next[0] = alert_en_shadowed_52_qs;
+ reg_rdata_next[0] = alert_en_shadowed_51_qs;
end
addr_hit[119]: begin
- reg_rdata_next[0] = alert_en_shadowed_53_qs;
+ reg_rdata_next[0] = alert_en_shadowed_52_qs;
end
addr_hit[120]: begin
- reg_rdata_next[0] = alert_en_shadowed_54_qs;
+ reg_rdata_next[0] = alert_en_shadowed_53_qs;
end
addr_hit[121]: begin
- reg_rdata_next[0] = alert_en_shadowed_55_qs;
+ reg_rdata_next[0] = alert_en_shadowed_54_qs;
end
addr_hit[122]: begin
- reg_rdata_next[0] = alert_en_shadowed_56_qs;
+ reg_rdata_next[0] = alert_en_shadowed_55_qs;
end
addr_hit[123]: begin
- reg_rdata_next[0] = alert_en_shadowed_57_qs;
+ reg_rdata_next[0] = alert_en_shadowed_56_qs;
end
addr_hit[124]: begin
- reg_rdata_next[0] = alert_en_shadowed_58_qs;
+ reg_rdata_next[0] = alert_en_shadowed_57_qs;
end
addr_hit[125]: begin
- reg_rdata_next[0] = alert_en_shadowed_59_qs;
+ reg_rdata_next[0] = alert_en_shadowed_58_qs;
end
addr_hit[126]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
+ reg_rdata_next[0] = alert_en_shadowed_59_qs;
end
addr_hit[127]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
+ reg_rdata_next[0] = alert_en_shadowed_60_qs;
end
addr_hit[128]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
end
addr_hit[129]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
end
addr_hit[130]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
end
addr_hit[131]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
end
addr_hit[132]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
end
addr_hit[133]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
end
addr_hit[134]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
end
addr_hit[135]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
end
addr_hit[136]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
end
addr_hit[137]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
end
addr_hit[138]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
end
addr_hit[139]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
end
addr_hit[140]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
end
addr_hit[141]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
end
addr_hit[142]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
end
addr_hit[143]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
end
addr_hit[144]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
end
addr_hit[145]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
end
addr_hit[146]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
end
addr_hit[147]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
end
addr_hit[148]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
end
addr_hit[149]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
end
addr_hit[150]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
end
addr_hit[151]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
end
addr_hit[152]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
end
addr_hit[153]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
end
addr_hit[154]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
end
addr_hit[155]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
end
addr_hit[156]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
end
addr_hit[157]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
end
addr_hit[158]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
end
addr_hit[159]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
end
addr_hit[160]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
end
addr_hit[161]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
end
addr_hit[162]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
end
addr_hit[163]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
end
addr_hit[164]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
end
addr_hit[165]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
end
addr_hit[166]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
end
addr_hit[167]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
end
addr_hit[168]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
end
addr_hit[169]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
end
addr_hit[170]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
end
addr_hit[171]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
end
addr_hit[172]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
end
addr_hit[173]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
end
addr_hit[174]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
end
addr_hit[175]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
end
addr_hit[176]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
end
addr_hit[177]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
end
addr_hit[178]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
end
addr_hit[179]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
end
addr_hit[180]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
end
addr_hit[181]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
end
addr_hit[182]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
end
addr_hit[183]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
end
addr_hit[184]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
end
addr_hit[185]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
end
addr_hit[186]: begin
- reg_rdata_next[0] = alert_cause_0_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
end
addr_hit[187]: begin
- reg_rdata_next[0] = alert_cause_1_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
end
addr_hit[188]: begin
- reg_rdata_next[0] = alert_cause_2_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_60_qs;
end
addr_hit[189]: begin
- reg_rdata_next[0] = alert_cause_3_qs;
+ reg_rdata_next[0] = alert_cause_0_qs;
end
addr_hit[190]: begin
- reg_rdata_next[0] = alert_cause_4_qs;
+ reg_rdata_next[0] = alert_cause_1_qs;
end
addr_hit[191]: begin
- reg_rdata_next[0] = alert_cause_5_qs;
+ reg_rdata_next[0] = alert_cause_2_qs;
end
addr_hit[192]: begin
- reg_rdata_next[0] = alert_cause_6_qs;
+ reg_rdata_next[0] = alert_cause_3_qs;
end
addr_hit[193]: begin
- reg_rdata_next[0] = alert_cause_7_qs;
+ reg_rdata_next[0] = alert_cause_4_qs;
end
addr_hit[194]: begin
- reg_rdata_next[0] = alert_cause_8_qs;
+ reg_rdata_next[0] = alert_cause_5_qs;
end
addr_hit[195]: begin
- reg_rdata_next[0] = alert_cause_9_qs;
+ reg_rdata_next[0] = alert_cause_6_qs;
end
addr_hit[196]: begin
- reg_rdata_next[0] = alert_cause_10_qs;
+ reg_rdata_next[0] = alert_cause_7_qs;
end
addr_hit[197]: begin
- reg_rdata_next[0] = alert_cause_11_qs;
+ reg_rdata_next[0] = alert_cause_8_qs;
end
addr_hit[198]: begin
- reg_rdata_next[0] = alert_cause_12_qs;
+ reg_rdata_next[0] = alert_cause_9_qs;
end
addr_hit[199]: begin
- reg_rdata_next[0] = alert_cause_13_qs;
+ reg_rdata_next[0] = alert_cause_10_qs;
end
addr_hit[200]: begin
- reg_rdata_next[0] = alert_cause_14_qs;
+ reg_rdata_next[0] = alert_cause_11_qs;
end
addr_hit[201]: begin
- reg_rdata_next[0] = alert_cause_15_qs;
+ reg_rdata_next[0] = alert_cause_12_qs;
end
addr_hit[202]: begin
- reg_rdata_next[0] = alert_cause_16_qs;
+ reg_rdata_next[0] = alert_cause_13_qs;
end
addr_hit[203]: begin
- reg_rdata_next[0] = alert_cause_17_qs;
+ reg_rdata_next[0] = alert_cause_14_qs;
end
addr_hit[204]: begin
- reg_rdata_next[0] = alert_cause_18_qs;
+ reg_rdata_next[0] = alert_cause_15_qs;
end
addr_hit[205]: begin
- reg_rdata_next[0] = alert_cause_19_qs;
+ reg_rdata_next[0] = alert_cause_16_qs;
end
addr_hit[206]: begin
- reg_rdata_next[0] = alert_cause_20_qs;
+ reg_rdata_next[0] = alert_cause_17_qs;
end
addr_hit[207]: begin
- reg_rdata_next[0] = alert_cause_21_qs;
+ reg_rdata_next[0] = alert_cause_18_qs;
end
addr_hit[208]: begin
- reg_rdata_next[0] = alert_cause_22_qs;
+ reg_rdata_next[0] = alert_cause_19_qs;
end
addr_hit[209]: begin
- reg_rdata_next[0] = alert_cause_23_qs;
+ reg_rdata_next[0] = alert_cause_20_qs;
end
addr_hit[210]: begin
- reg_rdata_next[0] = alert_cause_24_qs;
+ reg_rdata_next[0] = alert_cause_21_qs;
end
addr_hit[211]: begin
- reg_rdata_next[0] = alert_cause_25_qs;
+ reg_rdata_next[0] = alert_cause_22_qs;
end
addr_hit[212]: begin
- reg_rdata_next[0] = alert_cause_26_qs;
+ reg_rdata_next[0] = alert_cause_23_qs;
end
addr_hit[213]: begin
- reg_rdata_next[0] = alert_cause_27_qs;
+ reg_rdata_next[0] = alert_cause_24_qs;
end
addr_hit[214]: begin
- reg_rdata_next[0] = alert_cause_28_qs;
+ reg_rdata_next[0] = alert_cause_25_qs;
end
addr_hit[215]: begin
- reg_rdata_next[0] = alert_cause_29_qs;
+ reg_rdata_next[0] = alert_cause_26_qs;
end
addr_hit[216]: begin
- reg_rdata_next[0] = alert_cause_30_qs;
+ reg_rdata_next[0] = alert_cause_27_qs;
end
addr_hit[217]: begin
- reg_rdata_next[0] = alert_cause_31_qs;
+ reg_rdata_next[0] = alert_cause_28_qs;
end
addr_hit[218]: begin
- reg_rdata_next[0] = alert_cause_32_qs;
+ reg_rdata_next[0] = alert_cause_29_qs;
end
addr_hit[219]: begin
- reg_rdata_next[0] = alert_cause_33_qs;
+ reg_rdata_next[0] = alert_cause_30_qs;
end
addr_hit[220]: begin
- reg_rdata_next[0] = alert_cause_34_qs;
+ reg_rdata_next[0] = alert_cause_31_qs;
end
addr_hit[221]: begin
- reg_rdata_next[0] = alert_cause_35_qs;
+ reg_rdata_next[0] = alert_cause_32_qs;
end
addr_hit[222]: begin
- reg_rdata_next[0] = alert_cause_36_qs;
+ reg_rdata_next[0] = alert_cause_33_qs;
end
addr_hit[223]: begin
- reg_rdata_next[0] = alert_cause_37_qs;
+ reg_rdata_next[0] = alert_cause_34_qs;
end
addr_hit[224]: begin
- reg_rdata_next[0] = alert_cause_38_qs;
+ reg_rdata_next[0] = alert_cause_35_qs;
end
addr_hit[225]: begin
- reg_rdata_next[0] = alert_cause_39_qs;
+ reg_rdata_next[0] = alert_cause_36_qs;
end
addr_hit[226]: begin
- reg_rdata_next[0] = alert_cause_40_qs;
+ reg_rdata_next[0] = alert_cause_37_qs;
end
addr_hit[227]: begin
- reg_rdata_next[0] = alert_cause_41_qs;
+ reg_rdata_next[0] = alert_cause_38_qs;
end
addr_hit[228]: begin
- reg_rdata_next[0] = alert_cause_42_qs;
+ reg_rdata_next[0] = alert_cause_39_qs;
end
addr_hit[229]: begin
- reg_rdata_next[0] = alert_cause_43_qs;
+ reg_rdata_next[0] = alert_cause_40_qs;
end
addr_hit[230]: begin
- reg_rdata_next[0] = alert_cause_44_qs;
+ reg_rdata_next[0] = alert_cause_41_qs;
end
addr_hit[231]: begin
- reg_rdata_next[0] = alert_cause_45_qs;
+ reg_rdata_next[0] = alert_cause_42_qs;
end
addr_hit[232]: begin
- reg_rdata_next[0] = alert_cause_46_qs;
+ reg_rdata_next[0] = alert_cause_43_qs;
end
addr_hit[233]: begin
- reg_rdata_next[0] = alert_cause_47_qs;
+ reg_rdata_next[0] = alert_cause_44_qs;
end
addr_hit[234]: begin
- reg_rdata_next[0] = alert_cause_48_qs;
+ reg_rdata_next[0] = alert_cause_45_qs;
end
addr_hit[235]: begin
- reg_rdata_next[0] = alert_cause_49_qs;
+ reg_rdata_next[0] = alert_cause_46_qs;
end
addr_hit[236]: begin
- reg_rdata_next[0] = alert_cause_50_qs;
+ reg_rdata_next[0] = alert_cause_47_qs;
end
addr_hit[237]: begin
- reg_rdata_next[0] = alert_cause_51_qs;
+ reg_rdata_next[0] = alert_cause_48_qs;
end
addr_hit[238]: begin
- reg_rdata_next[0] = alert_cause_52_qs;
+ reg_rdata_next[0] = alert_cause_49_qs;
end
addr_hit[239]: begin
- reg_rdata_next[0] = alert_cause_53_qs;
+ reg_rdata_next[0] = alert_cause_50_qs;
end
addr_hit[240]: begin
- reg_rdata_next[0] = alert_cause_54_qs;
+ reg_rdata_next[0] = alert_cause_51_qs;
end
addr_hit[241]: begin
- reg_rdata_next[0] = alert_cause_55_qs;
+ reg_rdata_next[0] = alert_cause_52_qs;
end
addr_hit[242]: begin
- reg_rdata_next[0] = alert_cause_56_qs;
+ reg_rdata_next[0] = alert_cause_53_qs;
end
addr_hit[243]: begin
- reg_rdata_next[0] = alert_cause_57_qs;
+ reg_rdata_next[0] = alert_cause_54_qs;
end
addr_hit[244]: begin
- reg_rdata_next[0] = alert_cause_58_qs;
+ reg_rdata_next[0] = alert_cause_55_qs;
end
addr_hit[245]: begin
- reg_rdata_next[0] = alert_cause_59_qs;
+ reg_rdata_next[0] = alert_cause_56_qs;
end
addr_hit[246]: begin
- reg_rdata_next[0] = loc_alert_regwen_0_qs;
+ reg_rdata_next[0] = alert_cause_57_qs;
end
addr_hit[247]: begin
- reg_rdata_next[0] = loc_alert_regwen_1_qs;
+ reg_rdata_next[0] = alert_cause_58_qs;
end
addr_hit[248]: begin
- reg_rdata_next[0] = loc_alert_regwen_2_qs;
+ reg_rdata_next[0] = alert_cause_59_qs;
end
addr_hit[249]: begin
- reg_rdata_next[0] = loc_alert_regwen_3_qs;
+ reg_rdata_next[0] = alert_cause_60_qs;
end
addr_hit[250]: begin
- reg_rdata_next[0] = loc_alert_regwen_4_qs;
+ reg_rdata_next[0] = loc_alert_regwen_0_qs;
end
addr_hit[251]: begin
- reg_rdata_next[0] = loc_alert_regwen_5_qs;
+ reg_rdata_next[0] = loc_alert_regwen_1_qs;
end
addr_hit[252]: begin
- reg_rdata_next[0] = loc_alert_regwen_6_qs;
+ reg_rdata_next[0] = loc_alert_regwen_2_qs;
end
addr_hit[253]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
+ reg_rdata_next[0] = loc_alert_regwen_3_qs;
end
addr_hit[254]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
+ reg_rdata_next[0] = loc_alert_regwen_4_qs;
end
addr_hit[255]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
+ reg_rdata_next[0] = loc_alert_regwen_5_qs;
end
addr_hit[256]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
+ reg_rdata_next[0] = loc_alert_regwen_6_qs;
end
addr_hit[257]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
end
addr_hit[258]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
end
addr_hit[259]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
end
addr_hit[260]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
end
addr_hit[261]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
end
addr_hit[262]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
end
addr_hit[263]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
end
addr_hit[264]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
end
addr_hit[265]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
end
addr_hit[266]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
end
addr_hit[267]: begin
- reg_rdata_next[0] = loc_alert_cause_0_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
end
addr_hit[268]: begin
- reg_rdata_next[0] = loc_alert_cause_1_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
end
addr_hit[269]: begin
- reg_rdata_next[0] = loc_alert_cause_2_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
end
addr_hit[270]: begin
- reg_rdata_next[0] = loc_alert_cause_3_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
end
addr_hit[271]: begin
- reg_rdata_next[0] = loc_alert_cause_4_qs;
+ reg_rdata_next[0] = loc_alert_cause_0_qs;
end
addr_hit[272]: begin
- reg_rdata_next[0] = loc_alert_cause_5_qs;
+ reg_rdata_next[0] = loc_alert_cause_1_qs;
end
addr_hit[273]: begin
- reg_rdata_next[0] = loc_alert_cause_6_qs;
+ reg_rdata_next[0] = loc_alert_cause_2_qs;
end
addr_hit[274]: begin
- reg_rdata_next[0] = classa_regwen_qs;
+ reg_rdata_next[0] = loc_alert_cause_3_qs;
end
addr_hit[275]: begin
+ reg_rdata_next[0] = loc_alert_cause_4_qs;
+ end
+
+ addr_hit[276]: begin
+ reg_rdata_next[0] = loc_alert_cause_5_qs;
+ end
+
+ addr_hit[277]: begin
+ reg_rdata_next[0] = loc_alert_cause_6_qs;
+ end
+
+ addr_hit[278]: begin
+ reg_rdata_next[0] = classa_regwen_qs;
+ end
+
+ addr_hit[279]: begin
reg_rdata_next[0] = classa_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs;
@@ -16105,59 +16283,59 @@
reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs;
end
- addr_hit[276]: begin
+ addr_hit[280]: begin
reg_rdata_next[0] = classa_clr_regwen_qs;
end
- addr_hit[277]: begin
+ addr_hit[281]: begin
reg_rdata_next[0] = classa_clr_shadowed_qs;
end
- addr_hit[278]: begin
+ addr_hit[282]: begin
reg_rdata_next[15:0] = classa_accum_cnt_qs;
end
- addr_hit[279]: begin
+ addr_hit[283]: begin
reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs;
end
- addr_hit[280]: begin
+ addr_hit[284]: begin
reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs;
end
- addr_hit[281]: begin
+ addr_hit[285]: begin
reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs;
end
- addr_hit[282]: begin
+ addr_hit[286]: begin
reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs;
end
- addr_hit[283]: begin
+ addr_hit[287]: begin
reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs;
end
- addr_hit[284]: begin
+ addr_hit[288]: begin
reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs;
end
- addr_hit[285]: begin
+ addr_hit[289]: begin
reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs;
end
- addr_hit[286]: begin
+ addr_hit[290]: begin
reg_rdata_next[31:0] = classa_esc_cnt_qs;
end
- addr_hit[287]: begin
+ addr_hit[291]: begin
reg_rdata_next[2:0] = classa_state_qs;
end
- addr_hit[288]: begin
+ addr_hit[292]: begin
reg_rdata_next[0] = classb_regwen_qs;
end
- addr_hit[289]: begin
+ addr_hit[293]: begin
reg_rdata_next[0] = classb_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs;
@@ -16170,59 +16348,59 @@
reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs;
end
- addr_hit[290]: begin
+ addr_hit[294]: begin
reg_rdata_next[0] = classb_clr_regwen_qs;
end
- addr_hit[291]: begin
+ addr_hit[295]: begin
reg_rdata_next[0] = classb_clr_shadowed_qs;
end
- addr_hit[292]: begin
+ addr_hit[296]: begin
reg_rdata_next[15:0] = classb_accum_cnt_qs;
end
- addr_hit[293]: begin
+ addr_hit[297]: begin
reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs;
end
- addr_hit[294]: begin
+ addr_hit[298]: begin
reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs;
end
- addr_hit[295]: begin
+ addr_hit[299]: begin
reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs;
end
- addr_hit[296]: begin
+ addr_hit[300]: begin
reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs;
end
- addr_hit[297]: begin
+ addr_hit[301]: begin
reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs;
end
- addr_hit[298]: begin
+ addr_hit[302]: begin
reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs;
end
- addr_hit[299]: begin
+ addr_hit[303]: begin
reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs;
end
- addr_hit[300]: begin
+ addr_hit[304]: begin
reg_rdata_next[31:0] = classb_esc_cnt_qs;
end
- addr_hit[301]: begin
+ addr_hit[305]: begin
reg_rdata_next[2:0] = classb_state_qs;
end
- addr_hit[302]: begin
+ addr_hit[306]: begin
reg_rdata_next[0] = classc_regwen_qs;
end
- addr_hit[303]: begin
+ addr_hit[307]: begin
reg_rdata_next[0] = classc_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs;
@@ -16235,59 +16413,59 @@
reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs;
end
- addr_hit[304]: begin
+ addr_hit[308]: begin
reg_rdata_next[0] = classc_clr_regwen_qs;
end
- addr_hit[305]: begin
+ addr_hit[309]: begin
reg_rdata_next[0] = classc_clr_shadowed_qs;
end
- addr_hit[306]: begin
+ addr_hit[310]: begin
reg_rdata_next[15:0] = classc_accum_cnt_qs;
end
- addr_hit[307]: begin
+ addr_hit[311]: begin
reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs;
end
- addr_hit[308]: begin
+ addr_hit[312]: begin
reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs;
end
- addr_hit[309]: begin
+ addr_hit[313]: begin
reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs;
end
- addr_hit[310]: begin
+ addr_hit[314]: begin
reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs;
end
- addr_hit[311]: begin
+ addr_hit[315]: begin
reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs;
end
- addr_hit[312]: begin
+ addr_hit[316]: begin
reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs;
end
- addr_hit[313]: begin
+ addr_hit[317]: begin
reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs;
end
- addr_hit[314]: begin
+ addr_hit[318]: begin
reg_rdata_next[31:0] = classc_esc_cnt_qs;
end
- addr_hit[315]: begin
+ addr_hit[319]: begin
reg_rdata_next[2:0] = classc_state_qs;
end
- addr_hit[316]: begin
+ addr_hit[320]: begin
reg_rdata_next[0] = classd_regwen_qs;
end
- addr_hit[317]: begin
+ addr_hit[321]: begin
reg_rdata_next[0] = classd_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs;
@@ -16300,51 +16478,51 @@
reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs;
end
- addr_hit[318]: begin
+ addr_hit[322]: begin
reg_rdata_next[0] = classd_clr_regwen_qs;
end
- addr_hit[319]: begin
+ addr_hit[323]: begin
reg_rdata_next[0] = classd_clr_shadowed_qs;
end
- addr_hit[320]: begin
+ addr_hit[324]: begin
reg_rdata_next[15:0] = classd_accum_cnt_qs;
end
- addr_hit[321]: begin
+ addr_hit[325]: begin
reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs;
end
- addr_hit[322]: begin
+ addr_hit[326]: begin
reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs;
end
- addr_hit[323]: begin
+ addr_hit[327]: begin
reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs;
end
- addr_hit[324]: begin
+ addr_hit[328]: begin
reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs;
end
- addr_hit[325]: begin
+ addr_hit[329]: begin
reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs;
end
- addr_hit[326]: begin
+ addr_hit[330]: begin
reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs;
end
- addr_hit[327]: begin
+ addr_hit[331]: begin
reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs;
end
- addr_hit[328]: begin
+ addr_hit[332]: begin
reg_rdata_next[31:0] = classd_esc_cnt_qs;
end
- addr_hit[329]: begin
+ addr_hit[333]: begin
reg_rdata_next[2:0] = classd_state_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 4623145..943d4f5 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -2026,7 +2026,7 @@
.rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
);
flash_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:33]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:33]),
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
.RndCnstDataKey(RndCnstFlashCtrlDataKey),
.RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -2051,9 +2051,10 @@
.intr_op_done_o (intr_flash_ctrl_op_done),
.intr_corr_err_o (intr_flash_ctrl_corr_err),
// [33]: recov_err
- // [34]: fatal_err
- .alert_tx_o ( alert_tx[34:33] ),
- .alert_rx_i ( alert_rx[34:33] ),
+ // [34]: fatal_std_err
+ // [35]: fatal_err
+ .alert_tx_o ( alert_tx[35:33] ),
+ .alert_rx_i ( alert_rx[35:33] ),
// Inter-module signals
.otp_o(flash_ctrl_otp_req),
@@ -2096,12 +2097,12 @@
.rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
rv_dm #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:35]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:36]),
.IdcodeValue(RvDmIdcodeValue)
) u_rv_dm (
- // [35]: fatal_fault
- .alert_tx_o ( alert_tx[35:35] ),
- .alert_rx_i ( alert_rx[35:35] ),
+ // [36]: fatal_fault
+ .alert_tx_o ( alert_tx[36:36] ),
+ .alert_rx_i ( alert_rx[36:36] ),
// Inter-module signals
.jtag_i(pinmux_aon_rv_jtag_req),
@@ -2125,11 +2126,11 @@
.rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
);
rv_plic #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:36])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:37])
) u_rv_plic (
- // [36]: fatal_fault
- .alert_tx_o ( alert_tx[36:36] ),
- .alert_rx_i ( alert_rx[36:36] ),
+ // [37]: fatal_fault
+ .alert_tx_o ( alert_tx[37:37] ),
+ .alert_rx_i ( alert_rx[37:37] ),
// Inter-module signals
.irq_o(rv_plic_irq),
@@ -2144,7 +2145,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
aes #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:37]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:38]),
.AES192Enable(1'b1),
.SecMasking(SecAesMasking),
.SecSBoxImpl(SecAesSBoxImpl),
@@ -2157,10 +2158,10 @@
.RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
.RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm)
) u_aes (
- // [37]: recov_ctrl_update_err
- // [38]: fatal_fault
- .alert_tx_o ( alert_tx[38:37] ),
- .alert_rx_i ( alert_rx[38:37] ),
+ // [38]: recov_ctrl_update_err
+ // [39]: fatal_fault
+ .alert_tx_o ( alert_tx[39:38] ),
+ .alert_rx_i ( alert_rx[39:38] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[0]),
@@ -2179,16 +2180,16 @@
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
hmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:39])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40])
) u_hmac (
// Interrupt
.intr_hmac_done_o (intr_hmac_hmac_done),
.intr_fifo_empty_o (intr_hmac_fifo_empty),
.intr_hmac_err_o (intr_hmac_hmac_err),
- // [39]: fatal_fault
- .alert_tx_o ( alert_tx[39:39] ),
- .alert_rx_i ( alert_rx[39:39] ),
+ // [40]: fatal_fault
+ .alert_tx_o ( alert_tx[40:40] ),
+ .alert_rx_i ( alert_rx[40:40] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[1]),
@@ -2200,7 +2201,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
kmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:41]),
.EnMasking(KmacEnMasking),
.ReuseShare(KmacReuseShare),
.SecCmdDelay(SecKmacCmdDelay),
@@ -2215,10 +2216,10 @@
.intr_kmac_done_o (intr_kmac_kmac_done),
.intr_fifo_empty_o (intr_kmac_fifo_empty),
.intr_kmac_err_o (intr_kmac_kmac_err),
- // [40]: recov_operation_err
- // [41]: fatal_fault_err
- .alert_tx_o ( alert_tx[41:40] ),
- .alert_rx_i ( alert_rx[41:40] ),
+ // [41]: recov_operation_err
+ // [42]: fatal_fault_err
+ .alert_tx_o ( alert_tx[42:41] ),
+ .alert_rx_i ( alert_rx[42:41] ),
// Inter-module signals
.keymgr_key_i(keymgr_kmac_key),
@@ -2240,7 +2241,7 @@
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
otbn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]),
.Stub(OtbnStub),
.RegFile(OtbnRegFile),
.RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed),
@@ -2250,10 +2251,10 @@
// Interrupt
.intr_done_o (intr_otbn_done),
- // [42]: fatal
- // [43]: recov
- .alert_tx_o ( alert_tx[43:42] ),
- .alert_rx_i ( alert_rx[43:42] ),
+ // [43]: fatal
+ // [44]: recov
+ .alert_tx_o ( alert_tx[44:43] ),
+ .alert_rx_i ( alert_rx[44:43] ),
// Inter-module signals
.otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
@@ -2278,7 +2279,7 @@
.rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
keymgr #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:44]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
.KmacEnMasking(KeymgrKmacEnMasking),
.RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
.RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
@@ -2297,10 +2298,10 @@
// Interrupt
.intr_op_done_o (intr_keymgr_op_done),
- // [44]: recov_operation_err
- // [45]: fatal_fault_err
- .alert_tx_o ( alert_tx[45:44] ),
- .alert_rx_i ( alert_rx[45:44] ),
+ // [45]: recov_operation_err
+ // [46]: fatal_fault_err
+ .alert_tx_o ( alert_tx[46:45] ),
+ .alert_rx_i ( alert_rx[46:45] ),
// Inter-module signals
.edn_o(edn0_edn_req[0]),
@@ -2328,7 +2329,7 @@
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
csrng #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
.RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
.RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
.SBoxImpl(CsrngSBoxImpl)
@@ -2339,10 +2340,10 @@
.intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
.intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
.intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
- // [46]: recov_alert
- // [47]: fatal_alert
- .alert_tx_o ( alert_tx[47:46] ),
- .alert_rx_i ( alert_rx[47:46] ),
+ // [47]: recov_alert
+ // [48]: fatal_alert
+ .alert_tx_o ( alert_tx[48:47] ),
+ .alert_rx_i ( alert_rx[48:47] ),
// Inter-module signals
.csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2361,7 +2362,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
entropy_src #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]),
.Stub(EntropySrcStub)
) u_entropy_src (
@@ -2370,10 +2371,10 @@
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
.intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
.intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [48]: recov_alert
- // [49]: fatal_alert
- .alert_tx_o ( alert_tx[49:48] ),
- .alert_rx_i ( alert_rx[49:48] ),
+ // [49]: recov_alert
+ // [50]: fatal_alert
+ .alert_tx_o ( alert_tx[50:49] ),
+ .alert_rx_i ( alert_rx[50:49] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2395,16 +2396,16 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51])
) u_edn0 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
- // [50]: recov_alert
- // [51]: fatal_alert
- .alert_tx_o ( alert_tx[51:50] ),
- .alert_rx_i ( alert_rx[51:50] ),
+ // [51]: recov_alert
+ // [52]: fatal_alert
+ .alert_tx_o ( alert_tx[52:51] ),
+ .alert_rx_i ( alert_rx[52:51] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2419,16 +2420,16 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:52])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53])
) u_edn1 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
- // [52]: recov_alert
- // [53]: fatal_alert
- .alert_tx_o ( alert_tx[53:52] ),
- .alert_rx_i ( alert_rx[53:52] ),
+ // [53]: recov_alert
+ // [54]: fatal_alert
+ .alert_tx_o ( alert_tx[54:53] ),
+ .alert_rx_i ( alert_rx[54:53] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2443,7 +2444,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:54]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:55]),
.RndCnstSramKey(RndCnstSramCtrlMainSramKey),
.RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
.RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
@@ -2451,9 +2452,9 @@
.MemSizeRam(131072),
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [54]: fatal_error
- .alert_tx_o ( alert_tx[54:54] ),
- .alert_rx_i ( alert_rx[54:54] ),
+ // [55]: fatal_error
+ .alert_tx_o ( alert_tx[55:55] ),
+ .alert_rx_i ( alert_rx[55:55] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2474,15 +2475,15 @@
.rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
rom_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:55]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:56]),
.BootRomInitFile(RomCtrlBootRomInitFile),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey),
.SecDisableScrambling(SecRomCtrlDisableScrambling)
) u_rom_ctrl (
- // [55]: fatal
- .alert_tx_o ( alert_tx[55:55] ),
- .alert_rx_i ( alert_rx[55:55] ),
+ // [56]: fatal
+ .alert_tx_o ( alert_tx[56:56] ),
+ .alert_rx_i ( alert_rx[56:56] ),
// Inter-module signals
.rom_cfg_i(ast_rom_cfg),
@@ -2500,7 +2501,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
rv_core_ibex #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:56]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:57]),
.RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed),
.RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm),
.RndCnstIbexKeyDefault(RndCnstRvCoreIbexIbexKeyDefault),
@@ -2526,12 +2527,12 @@
.DmExceptionAddr(RvCoreIbexDmExceptionAddr),
.PipeLine(RvCoreIbexPipeLine)
) u_rv_core_ibex (
- // [56]: fatal_sw_err
- // [57]: recov_sw_err
- // [58]: fatal_hw_err
- // [59]: recov_hw_err
- .alert_tx_o ( alert_tx[59:56] ),
- .alert_rx_i ( alert_rx[59:56] ),
+ // [57]: fatal_sw_err
+ // [58]: recov_sw_err
+ // [59]: fatal_hw_err
+ // [60]: recov_hw_err
+ .alert_tx_o ( alert_tx[60:57] ),
+ .alert_rx_i ( alert_rx[60:57] ),
// Inter-module signals
.rst_cpu_n_o(),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index da34294..9a5c301 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -207,7 +207,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[60] = {
+ top_earlgrey_alert_for_peripheral[61] = {
[kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0,
[kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1,
[kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2,
@@ -242,6 +242,7 @@
[kTopEarlgreyAlertIdSensorCtrlFatalAlert] = kTopEarlgreyAlertPeripheralSensorCtrl,
[kTopEarlgreyAlertIdSramCtrlRetAonFatalError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon,
[kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
+ [kTopEarlgreyAlertIdFlashCtrlFatalStdErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdFlashCtrlFatalErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdRvDmFatalFault] = kTopEarlgreyAlertPeripheralRvDm,
[kTopEarlgreyAlertIdRvPlicFatalFault] = kTopEarlgreyAlertPeripheralRvPlic,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index d930751..da564fb 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1314,33 +1314,34 @@
kTopEarlgreyAlertIdSensorCtrlFatalAlert = 31, /**< sensor_ctrl_fatal_alert */
kTopEarlgreyAlertIdSramCtrlRetAonFatalError = 32, /**< sram_ctrl_ret_aon_fatal_error */
kTopEarlgreyAlertIdFlashCtrlRecovErr = 33, /**< flash_ctrl_recov_err */
- kTopEarlgreyAlertIdFlashCtrlFatalErr = 34, /**< flash_ctrl_fatal_err */
- kTopEarlgreyAlertIdRvDmFatalFault = 35, /**< rv_dm_fatal_fault */
- kTopEarlgreyAlertIdRvPlicFatalFault = 36, /**< rv_plic_fatal_fault */
- kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 37, /**< aes_recov_ctrl_update_err */
- kTopEarlgreyAlertIdAesFatalFault = 38, /**< aes_fatal_fault */
- kTopEarlgreyAlertIdHmacFatalFault = 39, /**< hmac_fatal_fault */
- kTopEarlgreyAlertIdKmacRecovOperationErr = 40, /**< kmac_recov_operation_err */
- kTopEarlgreyAlertIdKmacFatalFaultErr = 41, /**< kmac_fatal_fault_err */
- kTopEarlgreyAlertIdOtbnFatal = 42, /**< otbn_fatal */
- kTopEarlgreyAlertIdOtbnRecov = 43, /**< otbn_recov */
- kTopEarlgreyAlertIdKeymgrRecovOperationErr = 44, /**< keymgr_recov_operation_err */
- kTopEarlgreyAlertIdKeymgrFatalFaultErr = 45, /**< keymgr_fatal_fault_err */
- kTopEarlgreyAlertIdCsrngRecovAlert = 46, /**< csrng_recov_alert */
- kTopEarlgreyAlertIdCsrngFatalAlert = 47, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdEntropySrcRecovAlert = 48, /**< entropy_src_recov_alert */
- kTopEarlgreyAlertIdEntropySrcFatalAlert = 49, /**< entropy_src_fatal_alert */
- kTopEarlgreyAlertIdEdn0RecovAlert = 50, /**< edn0_recov_alert */
- kTopEarlgreyAlertIdEdn0FatalAlert = 51, /**< edn0_fatal_alert */
- kTopEarlgreyAlertIdEdn1RecovAlert = 52, /**< edn1_recov_alert */
- kTopEarlgreyAlertIdEdn1FatalAlert = 53, /**< edn1_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalError = 54, /**< sram_ctrl_main_fatal_error */
- kTopEarlgreyAlertIdRomCtrlFatal = 55, /**< rom_ctrl_fatal */
- kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 56, /**< rv_core_ibex_fatal_sw_err */
- kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 57, /**< rv_core_ibex_recov_sw_err */
- kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 58, /**< rv_core_ibex_fatal_hw_err */
- kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 59, /**< rv_core_ibex_recov_hw_err */
- kTopEarlgreyAlertIdLast = 59, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 34, /**< flash_ctrl_fatal_std_err */
+ kTopEarlgreyAlertIdFlashCtrlFatalErr = 35, /**< flash_ctrl_fatal_err */
+ kTopEarlgreyAlertIdRvDmFatalFault = 36, /**< rv_dm_fatal_fault */
+ kTopEarlgreyAlertIdRvPlicFatalFault = 37, /**< rv_plic_fatal_fault */
+ kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 38, /**< aes_recov_ctrl_update_err */
+ kTopEarlgreyAlertIdAesFatalFault = 39, /**< aes_fatal_fault */
+ kTopEarlgreyAlertIdHmacFatalFault = 40, /**< hmac_fatal_fault */
+ kTopEarlgreyAlertIdKmacRecovOperationErr = 41, /**< kmac_recov_operation_err */
+ kTopEarlgreyAlertIdKmacFatalFaultErr = 42, /**< kmac_fatal_fault_err */
+ kTopEarlgreyAlertIdOtbnFatal = 43, /**< otbn_fatal */
+ kTopEarlgreyAlertIdOtbnRecov = 44, /**< otbn_recov */
+ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 45, /**< keymgr_recov_operation_err */
+ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 46, /**< keymgr_fatal_fault_err */
+ kTopEarlgreyAlertIdCsrngRecovAlert = 47, /**< csrng_recov_alert */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 48, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 49, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 50, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdEdn0RecovAlert = 51, /**< edn0_recov_alert */
+ kTopEarlgreyAlertIdEdn0FatalAlert = 52, /**< edn0_fatal_alert */
+ kTopEarlgreyAlertIdEdn1RecovAlert = 53, /**< edn1_recov_alert */
+ kTopEarlgreyAlertIdEdn1FatalAlert = 54, /**< edn1_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalError = 55, /**< sram_ctrl_main_fatal_error */
+ kTopEarlgreyAlertIdRomCtrlFatal = 56, /**< rom_ctrl_fatal */
+ kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 57, /**< rv_core_ibex_fatal_sw_err */
+ kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 58, /**< rv_core_ibex_recov_sw_err */
+ kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 59, /**< rv_core_ibex_fatal_hw_err */
+ kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 60, /**< rv_core_ibex_recov_hw_err */
+ kTopEarlgreyAlertIdLast = 60, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1350,7 +1351,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[60];
+ top_earlgrey_alert_for_peripheral[61];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
diff --git a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c
index aa7ec01..6de940a 100644
--- a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c
+++ b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.c
@@ -33,6 +33,9 @@
case kDifFlashCtrlAlertRecovErr:
alert_idx = FLASH_CTRL_ALERT_TEST_RECOV_ERR_BIT;
break;
+ case kDifFlashCtrlAlertFatalStdErr:
+ alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT;
+ break;
case kDifFlashCtrlAlertFatalErr:
alert_idx = FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT;
break;
diff --git a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h
index dc2fe24..6583633 100644
--- a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h
+++ b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h
@@ -59,9 +59,13 @@
*/
kDifFlashCtrlAlertRecovErr = 0,
/**
+ * Flash standard fatal errors
+ */
+ kDifFlashCtrlAlertFatalStdErr = 1,
+ /**
* Flash fatal errors
*/
- kDifFlashCtrlAlertFatalErr = 1,
+ kDifFlashCtrlAlertFatalErr = 2,
} dif_flash_ctrl_alert_t;
/**
diff --git a/sw/device/lib/dif/dif_flash_ctrl.c b/sw/device/lib/dif/dif_flash_ctrl.c
index 0e0b4c0..ad4cca8 100644
--- a/sw/device/lib/dif/dif_flash_ctrl.c
+++ b/sw/device/lib/dif/dif_flash_ctrl.c
@@ -1169,8 +1169,8 @@
if (handle == NULL || faults_out == NULL) {
return kDifBadArg;
}
- const uint32_t reg = mmio_region_read32(handle->dev.base_addr,
- FLASH_CTRL_FAULT_STATUS_REG_OFFSET);
+ uint32_t reg = mmio_region_read32(handle->dev.base_addr,
+ FLASH_CTRL_FAULT_STATUS_REG_OFFSET);
dif_flash_ctrl_faults_t faults;
faults.memory_properties_error =
bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_MP_ERR_BIT);
@@ -1182,14 +1182,17 @@
bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_PROG_TYPE_ERR_BIT);
faults.flash_phy_error =
bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_FLASH_PHY_ERR_BIT);
+
+ reg = mmio_region_read32(handle->dev.base_addr,
+ FLASH_CTRL_STD_FAULT_STATUS_REG_OFFSET);
faults.register_integrity_error =
- bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_REG_INTG_ERR_BIT);
+ bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT);
faults.phy_integrity_error =
- bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_PHY_INTG_ERR_BIT);
+ bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_PHY_INTG_ERR_BIT);
faults.lifecycle_manager_error =
- bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_LCMGR_ERR_BIT);
+ bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT);
faults.shadow_storage_error =
- bitfield_bit32_read(reg, FLASH_CTRL_FAULT_STATUS_STORAGE_ERR_BIT);
+ bitfield_bit32_read(reg, FLASH_CTRL_STD_FAULT_STATUS_STORAGE_ERR_BIT);
*faults_out = faults;
return kDifOk;
}
diff --git a/sw/device/lib/dif/dif_flash_ctrl_unittest.cc b/sw/device/lib/dif/dif_flash_ctrl_unittest.cc
index ac2a559..21c40d5 100644
--- a/sw/device/lib/dif/dif_flash_ctrl_unittest.cc
+++ b/sw/device/lib/dif/dif_flash_ctrl_unittest.cc
@@ -836,10 +836,13 @@
{FLASH_CTRL_FAULT_STATUS_PROG_WIN_ERR_BIT, 1},
{FLASH_CTRL_FAULT_STATUS_PROG_TYPE_ERR_BIT, 0},
{FLASH_CTRL_FAULT_STATUS_FLASH_PHY_ERR_BIT, 1},
- {FLASH_CTRL_FAULT_STATUS_REG_INTG_ERR_BIT, 0},
- {FLASH_CTRL_FAULT_STATUS_PHY_INTG_ERR_BIT, 1},
- {FLASH_CTRL_FAULT_STATUS_LCMGR_ERR_BIT, 0},
- {FLASH_CTRL_FAULT_STATUS_STORAGE_ERR_BIT, 1},
+ });
+ EXPECT_READ32(FLASH_CTRL_STD_FAULT_STATUS_REG_OFFSET,
+ {
+ {FLASH_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT, 0},
+ {FLASH_CTRL_STD_FAULT_STATUS_PHY_INTG_ERR_BIT, 1},
+ {FLASH_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT, 0},
+ {FLASH_CTRL_STD_FAULT_STATUS_STORAGE_ERR_BIT, 1},
});
EXPECT_DIF_OK(dif_flash_ctrl_get_faults(&dif_flash_ctrl_, &faults));
EXPECT_EQ(faults.memory_properties_error, 1);
diff --git a/sw/device/silicon_creator/lib/drivers/alert_functest.c b/sw/device/silicon_creator/lib/drivers/alert_functest.c
index 61a5fa6..d1bdfe1 100644
--- a/sw/device/silicon_creator/lib/drivers/alert_functest.c
+++ b/sw/device/silicon_creator/lib/drivers/alert_functest.c
@@ -76,7 +76,8 @@
sec_mmio_check_counters(/*expected_check_count=*/3);
LOG_INFO("Generate alert via test regs");
- abs_mmio_write32(kFlashBase + FLASH_CTRL_ALERT_TEST_REG_OFFSET, 2);
+ abs_mmio_write32(kFlashBase + FLASH_CTRL_ALERT_TEST_REG_OFFSET,
+ 1u << FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT);
return kErrorUnknown;
}
