commit 55b2cdfc14ecdfbeec13cacc8b8a4742ebe41a10
author Weicai Yang <weicai@google.com> Fri Apr 10 15:40:30 2020 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Wed Apr 22 16:28:38 2020 -0700
tree e6197e93be70b9fa810312ae605685ea193ab628
parent b61ef1b74625637bc2ee5a84ff45cfbbec5b1ede

[dv] Support WO, RO type for mem

Clean up failures in chip_mem_walk
1. Update reggen&topgen to support WO, RO type for mem
2. Update memory rom, eflash to RO
3. Override uvm_mem::configure to support WO type

Signed-off-by: Weicai Yang <weicai@google.com>

util/topgen.py

diff --git a/util/topgen.py b/util/topgen.py
index 25c244a..c424653 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -371,8 +371,10 @@
             mem.name = item["name"]
             mem.base_addr = int(item["base_addr"], 0)
             mem.limit_addr = int(item["base_addr"], 0) + int(item["size"], 0)
-            # TODO: need to add mem access info for memories in topcfg
-            mem.dvrights = "RW"
+            if "swaccess" in item.keys():
+                mem.dvrights = item["swaccess"]
+            else:
+                mem.dvrights = "RW"
             mem.n_bits = top_block.width
             top_block.wins.append(mem)