commit 55aab3d3d889b26745dfa23057ed821f0c6b406a
author Philipp Wagner <phw@lowrisc.org> Tue Mar 16 20:43:55 2021 +0000
committer Philipp Wagner <mail@philipp-wagner.com> Wed Mar 17 08:15:03 2021 +0000
tree 1b5ebb71de4a841aab05a215eaf79bd5e51b3fb9
parent ff974390dde97789d6a1c47ee8bcab45d6e2c1a0

[rv_plic] Use relative links in documentation

Make the IP block/template relocateable by using relative links in the
documentation where possible. Explicitly mark absolute links (relative
to the project root) as such without relying on the Hugo search path.

Signed-off-by: Philipp Wagner <phw@lowrisc.org>

hw/ip/rv_plic/doc/checklist.md

diff --git a/hw/ip/rv_plic/doc/checklist.md b/hw/ip/rv_plic/doc/checklist.md
index 617a7b2..c72bd4c 100644
--- a/hw/ip/rv_plic/doc/checklist.md
+++ b/hw/ip/rv_plic/doc/checklist.md
@@ -2,7 +2,7 @@
 title: "RV_PLIC Checklist"
 ---
 
-This checklist is for [Hardware Stage]({{<relref "/doc/project/development_stages.md" >}}) transitions for the [RV_PLIC peripheral](../).
+This checklist is for [Hardware Stage]({{<relref "/doc/project/development_stages.md" >}}) transitions for the [RV_PLIC peripheral](..).
 All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md" >}})
 
 ## Design Checklist
@@ -21,7 +21,7 @@
 RTL           | [ASSERT_KNOWN_ADDED][]         | Done        |
 Code Quality  | [LINT_SETUP][]                 | Done        |
 
-[RV_PLIC Spec]: {{<relref "/hw/ip/rv_plic/doc">}}
+[RV_PLIC Spec]: {{<relref ".">}}
 
 [SPEC_COMPLETE]:              {{<relref "/doc/project/checklist.md#spec_complete" >}}
 [CSR_DEFINED]:                {{<relref "/doc/project/checklist.md#csr_defined" >}}

hw/ip/rv_plic/doc/dv/index.md

diff --git a/hw/ip/rv_plic/doc/dv/index.md b/hw/ip/rv_plic/doc/dv/index.md
index fadb95f..d8db4b4 100644
--- a/hw/ip/rv_plic/doc/dv/index.md
+++ b/hw/ip/rv_plic/doc/dv/index.md
@@ -13,22 +13,22 @@
 
 ## Current status
 * [Design & verification stage]({{< relref "hw" >}})
-  * [HW development stages]({{< relref "doc/project/development_stages" >}})
+  * [HW development stages]({{< relref "/doc/project/development_stages" >}})
 * FPV dashboard (link TBD)
 
 ## Design features
 For detailed information on RV_PLIC design features, please see the
-[RV_PLIC design specification]({{< relref "hw/ip/rv_plic/doc" >}}).
+[RV_PLIC design specification]({{< relref ".." >}}).
 
 ## Testbench architecture
 RV_PLIC FPV testbench has been constructed based on the [formal
-architecture]({{< relref "hw/formal/README.md" >}}).
+architecture]({{< relref "/hw/formal/README.md" >}}).
 
 ### Block diagram
 ![Block diagram](fpv.svg)
 
 #### TLUL assertions
-* The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}})
+* The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` binds the `tlul_assert` [assertions]({{< relref "/hw/ip/tlul/doc/TlulProtocolChecker.md" >}})
   to rv_plic to ensure TileLink interface protocol compliance.
 * The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` also binds the `rv_plic_csr_assert_fpv`
   under `hw/rv_plic/fpv/vip/` to check if TileLink writes and reads correct
@@ -45,7 +45,7 @@
 declared two symbolic variables `src_sel` and `tgt_sel` to represent the index for
 interrupt source and interrupt target.
 Detailed explanation is listed in the
-[Symbolic Variables]({{< relref "hw/formal/README.md#symbolic-variables" >}}) section.
+[Symbolic Variables]({{< relref "/hw/formal/README.md#symbolic-variables" >}}) section.
 
 ## DV plan
 {{< incGenFromIpDesc "../../data/rv_plic_fpv_testplan.hjson" "testplan" >}}