commit 54da40610d7f6439e5fad498c5fab27c68a91fa7
author Weicai Yang <weicai@google.com> Wed Mar 10 21:08:24 2021 -0800
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Mon Mar 15 13:07:06 2021 -0700
tree fba04684587102998356045bb742d2b38e8d4730
parent 40030846f0d617fa191ea1fc45a1f7206b1f2dec

[dv] temporarily disable mem test in chip-level

due to #5484
Signed-off-by: Weicai Yang <weicai@google.com>

hw/top_earlgrey/dv/chip_sim_cfg.hjson

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 6ed5f36..88cc38f 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -32,7 +32,8 @@
                 "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
                 "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
+                // TODO #5484, comment this out because spi host memory is dummy
+                // "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                 // xbar tests
                 "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson",