tree: 077a7c732c381642a03b6f970d1a01f994613827 [path history] [tgz]
  1. autogen/
  2. cov/
  3. env/
  4. tb/
  5. tests/
  6. chip_sim.core
  7. chip_sim_cfg.hjson
  8. Makefile
  9. README.md
  10. top_earlgrey_sim_cfgs.hjson
  11. vendor_chip_sim_cfg_sample.hjson
hw/top_earlgrey/dv/README.md

TOP Earl Grey

How to run simulation

Please run the following command to build and run tests: make TEST_NAME=<test-name>

Please see adjoining Makefile file for list of available tests to run. Please see hw/dv/tools/README.md for additional details on options that can be passed (such as enabling waves, running with specific seed etc.).

Note: Currently, ibex core raises an assertion but it doesn't harm UART TX and GPIO functionalities. Please ignore until it is resolved.