[dv/hmac] Adjustment to increase coverage
1. Add more weight to full msg write, so it will be easier to hit fifo_full
cases
2. Add tl_errors_vseq to stress_all test, in order to include error case
toggle coverage. Will remove once tl_errors is integrated to the reset
sequences.
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
index 48b42af..5cd3fd5 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
@@ -16,6 +16,12 @@
[3001:10_000] :/ 1 // temp set to 10KB as max length, spec max size is 2^64 bits
};
}
+ constraint wr_mask_c {
+ $countones(wr_mask) dist {
+ TL_DBW :/ 9,
+ [1:TL_DBW-1] :/ 1
+ };
+ }
virtual task pre_start();
do_back_pressure = 1'b1;
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index 6430c0c..6c9ee4e 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -36,6 +36,13 @@
}
}
+ constraint wr_mask_c {
+ $countones(wr_mask) dist {
+ TL_DBW :/ 1,
+ [1:TL_DBW-1] :/ 1
+ };
+ }
+
constraint wr_mask_size_c {
$countones(wr_mask) <= ('b1 << wr_size);
}
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
index 3c3d666..72bf667 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
@@ -35,7 +35,8 @@
if (seq_names[seq_idx] == "hmac_common_vseq") begin
hmac_common_vseq common_vseq;
`downcast(common_vseq, hmac_vseq)
- common_vseq.common_seq_type = "intr_test";
+ if ($urandom_range(0, 1)) common_vseq.common_seq_type = "intr_test";
+ else common_vseq.common_seq_type = "tl_errors";
end
hmac_vseq.start(p_sequencer);
end
